arch/powerpc/mm/book3s32/hash_low.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  PowerPC version
   4  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   5  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *  Adapted for Power Macintosh by Paul Mackerras.
   8  *  Low-level exception handlers and MMU support
   9  *  rewritten by Paul Mackerras.
  10  *    Copyright (C) 1996 Paul Mackerras.
  11  *
  12  *  This file contains low-level assembler routines for managing
  13  *  the PowerPC MMU hash table.  (PPC 8xx processors don't use a
  14  *  hash table, so this file is not used on them.)
  15  */
  16
  17 #include <asm/reg.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable.h>
  20 #include <asm/cputable.h>
  21 #include <asm/ppc_asm.h>
  22 #include <asm/thread_info.h>
  23 #include <asm/asm-offsets.h>
  24 #include <asm/export.h>
  25 #include <asm/feature-fixups.h>
  26 #include <asm/code-patching-asm.h>
  27
  28 #ifdef CONFIG_SMP
  29         .section .bss
  30         .align  2
  31 mmu_hash_lock:
  32         .space  4
  33 #endif /* CONFIG_SMP */
  34
  35 /*
  36  * Load a PTE into the hash table, if possible.
  37  * The address is in r4, and r3 contains an access flag:
  38  * _PAGE_RW (0x400) if a write.
  39  * r9 contains the SRR1 value, from which we use the MSR_PR bit.
  40  * SPRG_THREAD contains the physical address of the current task's thread.
  41  *
  42  * Returns to the caller if the access is illegal or there is no
  43  * mapping for the address.  Otherwise it places an appropriate PTE
  44  * in the hash table and returns from the exception.
  45  * Uses r0, r3 - r6, r8, r10, ctr, lr.
  46  */
  47         .text
  48 _GLOBAL(hash_page)
  49 #ifdef CONFIG_SMP
  50         lis     r8, (mmu_hash_lock - PAGE_OFFSET)@h
  51         ori     r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l
  52         lis     r0,0x0fff
  53         b       10f
  54 11:     lwz     r6,0(r8)
  55         cmpwi   0,r6,0
  56         bne     11b
  57 10:     lwarx   r6,0,r8
  58         cmpwi   0,r6,0
  59         bne-    11b
  60         stwcx.  r0,0,r8
  61         bne-    10b
  62         isync
  63 #endif
  64         /* Get PTE (linux-style) and check access */
  65         lis     r0,KERNELBASE@h         /* check if kernel address */
  66         cmplw   0,r4,r0
  67         ori     r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
  68         mfspr   r5, SPRN_SPRG_PGDIR     /* phys page-table root */
  69         blt+    112f                    /* assume user more likely */
  70         lis     r5, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, use */
  71         addi    r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l        /* kernel page table */
  72         rlwimi  r3,r9,32-12,29,29       /* MSR_PR -> _PAGE_USER */
  73 112:
  74 #ifndef CONFIG_PTE_64BIT
  75         rlwimi  r5,r4,12,20,29          /* insert top 10 bits of address */
  76         lwz     r8,0(r5)                /* get pmd entry */
  77         rlwinm. r8,r8,0,0,19            /* extract address of pte page */
  78 #else
  79         rlwinm  r8,r4,13,19,29          /* Compute pgdir/pmd offset */
  80         lwzx    r8,r8,r5                /* Get L1 entry */
  81         rlwinm. r8,r8,0,0,20            /* extract pt base address */
  82 #endif
  83 #ifdef CONFIG_SMP
  84         beq-    hash_page_out           /* return if no mapping */
  85 #else
  86         /* XXX it seems like the 601 will give a machine fault on the
  87            rfi if its alignment is wrong (bottom 4 bits of address are
  88            8 or 0xc) and we have had a not-taken conditional branch
  89            to the address following the rfi. */
  90         beqlr-
  91 #endif
  92 #ifndef CONFIG_PTE_64BIT
  93         rlwimi  r8,r4,22,20,29          /* insert next 10 bits of address */
  94 #else
  95         rlwimi  r8,r4,23,20,28          /* compute pte address */
  96 #endif
  97         rlwinm  r0,r3,32-3,24,24        /* _PAGE_RW access -> _PAGE_DIRTY */
  98         ori     r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
  99
 100         /*
 101          * Update the linux PTE atomically.  We do the lwarx up-front
 102          * because almost always, there won't be a permission violation
 103          * and there won't already be an HPTE, and thus we will have
 104          * to update the PTE to set _PAGE_HASHPTE.  -- paulus.
 105          *
 106          * If PTE_64BIT is set, the low word is the flags word; use that
 107          * word for locking since it contains all the interesting bits.
 108          */
 109 #if (PTE_FLAGS_OFFSET != 0)
 110         addi    r8,r8,PTE_FLAGS_OFFSET
 111 #endif
 112 retry:
 113         lwarx   r6,0,r8                 /* get linux-style pte, flag word */
 114         andc.   r5,r3,r6                /* check access & ~permission */
 115 #ifdef CONFIG_SMP
 116         bne-    hash_page_out           /* return if access not permitted */
 117 #else
 118         bnelr-
 119 #endif
 120         or      r5,r0,r6                /* set accessed/dirty bits */
 121 #ifdef CONFIG_PTE_64BIT
 122 #ifdef CONFIG_SMP
 123         subf    r10,r6,r8               /* create false data dependency */
 124         subi    r10,r10,PTE_FLAGS_OFFSET
 125         lwzx    r10,r6,r10              /* Get upper PTE word */
 126 #else
 127         lwz     r10,-PTE_FLAGS_OFFSET(r8)
 128 #endif /* CONFIG_SMP */
 129 #endif /* CONFIG_PTE_64BIT */
 130         stwcx.  r5,0,r8                 /* attempt to update PTE */
 131         bne-    retry                   /* retry if someone got there first */
 132
 133         mfsrin  r3,r4                   /* get segment reg for segment */
 134 #ifndef CONFIG_VMAP_STACK
 135         mfctr   r0
 136         stw     r0,_CTR(r11)
 137 #endif
 138         bl      create_hpte             /* add the hash table entry */
 139
 140 #ifdef CONFIG_SMP
 141         eieio
 142         lis     r8, (mmu_hash_lock - PAGE_OFFSET)@ha
 143         li      r0,0
 144         stw     r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
 145 #endif
 146
 147 #ifdef CONFIG_VMAP_STACK
 148         b       fast_hash_page_return
 149 #else
 150         /* Return from the exception */
 151         lwz     r5,_CTR(r11)
 152         mtctr   r5
 153         lwz     r0,GPR0(r11)
 154         lwz     r8,GPR8(r11)
 155         b       fast_exception_return
 156 #endif
 157
 158 #ifdef CONFIG_SMP
 159 hash_page_out:
 160         eieio
 161         lis     r8, (mmu_hash_lock - PAGE_OFFSET)@ha
 162         li      r0,0
 163         stw     r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
 164         blr
 165 #endif /* CONFIG_SMP */
 166
 167 /*
 168  * Add an entry for a particular page to the hash table.
 169  *
 170  * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
 171  *
 172  * We assume any necessary modifications to the pte (e.g. setting
 173  * the accessed bit) have already been done and that there is actually
 174  * a hash table in use (i.e. we're not on a 603).
 175  */
 176 _GLOBAL(add_hash_page)
 177         mflr    r0
 178         stw     r0,4(r1)
 179
 180         /* Convert context and va to VSID */
 181         mulli   r3,r3,897*16            /* multiply context by context skew */
 182         rlwinm  r0,r4,4,28,31           /* get ESID (top 4 bits of va) */
 183         mulli   r0,r0,0x111             /* multiply by ESID skew */
 184         add     r3,r3,r0                /* note create_hpte trims to 24 bits */
 185
 186 #ifdef CONFIG_SMP
 187         lwz     r8,TASK_CPU(r2)         /* to go in mmu_hash_lock */
 188         oris    r8,r8,12
 189 #endif /* CONFIG_SMP */
 190
 191         /*
 192          * We disable interrupts here, even on UP, because we don't
 193          * want to race with hash_page, and because we want the
 194          * _PAGE_HASHPTE bit to be a reliable indication of whether
 195          * the HPTE exists (or at least whether one did once).
 196          * We also turn off the MMU for data accesses so that we
 197          * we can't take a hash table miss (assuming the code is
 198          * covered by a BAT).  -- paulus
 199          */
 200         mfmsr   r9
 201         SYNC
 202         rlwinm  r0,r9,0,17,15           /* clear bit 16 (MSR_EE) */
 203         rlwinm  r0,r0,0,28,26           /* clear MSR_DR */
 204         mtmsr   r0
 205         SYNC_601
 206         isync
 207
 208 #ifdef CONFIG_SMP
 209         lis     r6, (mmu_hash_lock - PAGE_OFFSET)@ha
 210         addi    r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
 211 10:     lwarx   r0,0,r6                 /* take the mmu_hash_lock */
 212         cmpi    0,r0,0
 213         bne-    11f
 214         stwcx.  r8,0,r6
 215         beq+    12f
 216 11:     lwz     r0,0(r6)
 217         cmpi    0,r0,0
 218         beq     10b
 219         b       11b
 220 12:     isync
 221 #endif
 222
 223         /*
 224          * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
 225          * If _PAGE_HASHPTE was already set, we don't replace the existing
 226          * HPTE, so we just unlock and return.
 227          */
 228         mr      r8,r5
 229 #ifndef CONFIG_PTE_64BIT
 230         rlwimi  r8,r4,22,20,29
 231 #else
 232         rlwimi  r8,r4,23,20,28
 233         addi    r8,r8,PTE_FLAGS_OFFSET
 234 #endif
 235 1:      lwarx   r6,0,r8
 236         andi.   r0,r6,_PAGE_HASHPTE
 237         bne     9f                      /* if HASHPTE already set, done */
 238 #ifdef CONFIG_PTE_64BIT
 239 #ifdef CONFIG_SMP
 240         subf    r10,r6,r8               /* create false data dependency */
 241         subi    r10,r10,PTE_FLAGS_OFFSET
 242         lwzx    r10,r6,r10              /* Get upper PTE word */
 243 #else
 244         lwz     r10,-PTE_FLAGS_OFFSET(r8)
 245 #endif /* CONFIG_SMP */
 246 #endif /* CONFIG_PTE_64BIT */
 247         ori     r5,r6,_PAGE_HASHPTE
 248         stwcx.  r5,0,r8
 249         bne-    1b
 250
 251         bl      create_hpte
 252
 253 9:
 254 #ifdef CONFIG_SMP
 255         lis     r6, (mmu_hash_lock - PAGE_OFFSET)@ha
 256         addi    r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
 257         eieio
 258         li      r0,0
 259         stw     r0,0(r6)                /* clear mmu_hash_lock */
 260 #endif
 261
 262         /* reenable interrupts and DR */
 263         mtmsr   r9
 264         SYNC_601
 265         isync
 266
 267         lwz     r0,4(r1)
 268         mtlr    r0
 269         blr
 270
 271 /*
 272  * This routine adds a hardware PTE to the hash table.
 273  * It is designed to be called with the MMU either on or off.
 274  * r3 contains the VSID, r4 contains the virtual address,
 275  * r5 contains the linux PTE, r6 contains the old value of the
 276  * linux PTE (before setting _PAGE_HASHPTE). r10 contains the
 277  * upper half of the PTE if CONFIG_PTE_64BIT.
 278  * On SMP, the caller should have the mmu_hash_lock held.
 279  * We assume that the caller has (or will) set the _PAGE_HASHPTE
 280  * bit in the linux PTE in memory.  The value passed in r6 should
 281  * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
 282  * this routine will skip the search for an existing HPTE.
 283  * This procedure modifies r0, r3 - r6, r8, cr0.
 284  *  -- paulus.
 285  *
 286  * For speed, 4 of the instructions get patched once the size and
 287  * physical address of the hash table are known.  These definitions
 288  * of Hash_base and Hash_bits below are just an example.
 289  */
 290 Hash_base = 0xc0180000
 291 Hash_bits = 12                          /* e.g. 256kB hash table */
 292 Hash_msk = (((1 << Hash_bits) - 1) * 64)
 293
 294 /* defines for the PTE format for 32-bit PPCs */
 295 #define HPTE_SIZE       8
 296 #define PTEG_SIZE       64
 297 #define LG_PTEG_SIZE    6
 298 #define LDPTEu          lwzu
 299 #define LDPTE           lwz
 300 #define STPTE           stw
 301 #define CMPPTE          cmpw
 302 #define PTE_H           0x40
 303 #define PTE_V           0x80000000
 304 #define TST_V(r)        rlwinm. r,r,0,0,0
 305 #define SET_V(r)        oris r,r,PTE_V@h
 306 #define CLR_V(r,t)      rlwinm r,r,0,1,31
 307
 308 #define HASH_LEFT       31-(LG_PTEG_SIZE+Hash_bits-1)
 309 #define HASH_RIGHT      31-LG_PTEG_SIZE
 310
 311 _GLOBAL(create_hpte)
 312         /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
 313         rlwinm  r8,r5,32-9,30,30        /* _PAGE_RW -> PP msb */
 314         rlwinm  r0,r5,32-6,30,30        /* _PAGE_DIRTY -> PP msb */
 315         and     r8,r8,r0                /* writable if _RW & _DIRTY */
 316         rlwimi  r5,r5,32-1,30,30        /* _PAGE_USER -> PP msb */
 317         rlwimi  r5,r5,32-2,31,31        /* _PAGE_USER -> PP lsb */
 318         ori     r8,r8,0xe04             /* clear out reserved bits */
 319         andc    r8,r5,r8                /* PP = user? (rw&dirty? 1: 3): 0 */
 320 BEGIN_FTR_SECTION
 321         rlwinm  r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
 322 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
 323 #ifdef CONFIG_PTE_64BIT
 324         /* Put the XPN bits into the PTE */
 325         rlwimi  r8,r10,8,20,22
 326         rlwimi  r8,r10,2,29,29
 327 #endif
 328
 329         /* Construct the high word of the PPC-style PTE (r5) */
 330         rlwinm  r5,r3,7,1,24            /* put VSID in 0x7fffff80 bits */
 331         rlwimi  r5,r4,10,26,31          /* put in API (abbrev page index) */
 332         SET_V(r5)                       /* set V (valid) bit */
 333
 334         patch_site      0f, patch__hash_page_A0
 335         patch_site      1f, patch__hash_page_A1
 336         patch_site      2f, patch__hash_page_A2
 337         /* Get the address of the primary PTE group in the hash table (r3) */
 338 0:      lis     r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
 339 1:      rlwimi  r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 340 2:      rlwinm  r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
 341         xor     r3,r3,r0                /* make primary hash */
 342         li      r0,8                    /* PTEs/group */
 343
 344         /*
 345          * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
 346          * if it is clear, meaning that the HPTE isn't there already...
 347          */
 348         andi.   r6,r6,_PAGE_HASHPTE
 349         beq+    10f                     /* no PTE: go look for an empty slot */
 350         tlbie   r4
 351
 352         lis     r4, (htab_hash_searches - PAGE_OFFSET)@ha
 353         lwz     r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
 354         addi    r6,r6,1                 /* count how many searches we do */
 355         stw     r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
 356
 357         /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
 358         mtctr   r0
 359         addi    r4,r3,-HPTE_SIZE
 360 1:      LDPTEu  r6,HPTE_SIZE(r4)        /* get next PTE */
 361         CMPPTE  0,r6,r5
 362         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 363         beq+    found_slot
 364
 365         patch_site      0f, patch__hash_page_B
 366         /* Search the secondary PTEG for a matching PTE */
 367         ori     r5,r5,PTE_H             /* set H (secondary hash) bit */
 368 0:      xoris   r4,r3,Hash_msk>>16      /* compute secondary hash */
 369         xori    r4,r4,(-PTEG_SIZE & 0xffff)
 370         addi    r4,r4,-HPTE_SIZE
 371         mtctr   r0
 372 2:      LDPTEu  r6,HPTE_SIZE(r4)
 373         CMPPTE  0,r6,r5
 374         bdnzf   2,2b
 375         beq+    found_slot
 376         xori    r5,r5,PTE_H             /* clear H bit again */
 377
 378         /* Search the primary PTEG for an empty slot */
 379 10:     mtctr   r0
 380         addi    r4,r3,-HPTE_SIZE        /* search primary PTEG */
 381 1:      LDPTEu  r6,HPTE_SIZE(r4)        /* get next PTE */
 382         TST_V(r6)                       /* test valid bit */
 383         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 384         beq+    found_empty
 385
 386         /* update counter of times that the primary PTEG is full */
 387         lis     r4, (primary_pteg_full - PAGE_OFFSET)@ha
 388         lwz     r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
 389         addi    r6,r6,1
 390         stw     r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
 391
 392         patch_site      0f, patch__hash_page_C
 393         /* Search the secondary PTEG for an empty slot */
 394         ori     r5,r5,PTE_H             /* set H (secondary hash) bit */
 395 0:      xoris   r4,r3,Hash_msk>>16      /* compute secondary hash */
 396         xori    r4,r4,(-PTEG_SIZE & 0xffff)
 397         addi    r4,r4,-HPTE_SIZE
 398         mtctr   r0
 399 2:      LDPTEu  r6,HPTE_SIZE(r4)
 400         TST_V(r6)
 401         bdnzf   2,2b
 402         beq+    found_empty
 403         xori    r5,r5,PTE_H             /* clear H bit again */
 404
 405         /*
 406          * Choose an arbitrary slot in the primary PTEG to overwrite.
 407          * Since both the primary and secondary PTEGs are full, and we
 408          * have no information that the PTEs in the primary PTEG are
 409          * more important or useful than those in the secondary PTEG,
 410          * and we know there is a definite (although small) speed
 411          * advantage to putting the PTE in the primary PTEG, we always
 412          * put the PTE in the primary PTEG.
 413          *
 414          * In addition, we skip any slot that is mapping kernel text in
 415          * order to avoid a deadlock when not using BAT mappings if
 416          * trying to hash in the kernel hash code itself after it has
 417          * already taken the hash table lock. This works in conjunction
 418          * with pre-faulting of the kernel text.
 419          *
 420          * If the hash table bucket is full of kernel text entries, we'll
 421          * lockup here but that shouldn't happen
 422          */
 423
 424 1:      lis     r4, (next_slot - PAGE_OFFSET)@ha        /* get next evict slot */
 425         lwz     r6, (next_slot - PAGE_OFFSET)@l(r4)
 426         addi    r6,r6,HPTE_SIZE                 /* search for candidate */
 427         andi.   r6,r6,7*HPTE_SIZE
 428         stw     r6,next_slot@l(r4)
 429         add     r4,r3,r6
 430         LDPTE   r0,HPTE_SIZE/2(r4)              /* get PTE second word */
 431         clrrwi  r0,r0,12
 432         lis     r6,etext@h
 433         ori     r6,r6,etext@l                   /* get etext */
 434         tophys(r6,r6)
 435         cmpl    cr0,r0,r6                       /* compare and try again */
 436         blt     1b
 437
 438 #ifndef CONFIG_SMP
 439         /* Store PTE in PTEG */
 440 found_empty:
 441         STPTE   r5,0(r4)
 442 found_slot:
 443         STPTE   r8,HPTE_SIZE/2(r4)
 444
 445 #else /* CONFIG_SMP */
 446 /*
 447  * Between the tlbie above and updating the hash table entry below,
 448  * another CPU could read the hash table entry and put it in its TLB.
 449  * There are 3 cases:
 450  * 1. using an empty slot
 451  * 2. updating an earlier entry to change permissions (i.e. enable write)
 452  * 3. taking over the PTE for an unrelated address
 453  *
 454  * In each case it doesn't really matter if the other CPUs have the old
 455  * PTE in their TLB.  So we don't need to bother with another tlbie here,
 456  * which is convenient as we've overwritten the register that had the
 457  * address. :-)  The tlbie above is mainly to make sure that this CPU comes
 458  * and gets the new PTE from the hash table.
 459  *
 460  * We do however have to make sure that the PTE is never in an invalid
 461  * state with the V bit set.
 462  */
 463 found_empty:
 464 found_slot:
 465         CLR_V(r5,r0)            /* clear V (valid) bit in PTE */
 466         STPTE   r5,0(r4)
 467         sync
 468         TLBSYNC
 469         STPTE   r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
 470         sync
 471         SET_V(r5)
 472         STPTE   r5,0(r4)        /* finally set V bit in PTE */
 473 #endif /* CONFIG_SMP */
 474
 475         sync            /* make sure pte updates get to memory */
 476         blr
 477
 478         .section .bss
 479         .align  2
 480 next_slot:
 481         .space  4
 482 primary_pteg_full:
 483         .space  4
 484 htab_hash_searches:
 485         .space  4
 486         .previous
 487
 488 /*
 489  * Flush the entry for a particular page from the hash table.
 490  *
 491  * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
 492  *                  int count)
 493  *
 494  * We assume that there is a hash table in use (Hash != 0).
 495  */
 496 _GLOBAL(flush_hash_pages)
 497         /*
 498          * We disable interrupts here, even on UP, because we want
 499          * the _PAGE_HASHPTE bit to be a reliable indication of
 500          * whether the HPTE exists (or at least whether one did once).
 501          * We also turn off the MMU for data accesses so that we
 502          * we can't take a hash table miss (assuming the code is
 503          * covered by a BAT).  -- paulus
 504          */
 505         mfmsr   r10
 506         SYNC
 507         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 508         rlwinm  r0,r0,0,28,26           /* clear MSR_DR */
 509         mtmsr   r0
 510         SYNC_601
 511         isync
 512
 513         /* First find a PTE in the range that has _PAGE_HASHPTE set */
 514 #ifndef CONFIG_PTE_64BIT
 515         rlwimi  r5,r4,22,20,29
 516 #else
 517         rlwimi  r5,r4,23,20,28
 518 #endif
 519 1:      lwz     r0,PTE_FLAGS_OFFSET(r5)
 520         cmpwi   cr1,r6,1
 521         andi.   r0,r0,_PAGE_HASHPTE
 522         bne     2f
 523         ble     cr1,19f
 524         addi    r4,r4,0x1000
 525         addi    r5,r5,PTE_SIZE
 526         addi    r6,r6,-1
 527         b       1b
 528
 529         /* Convert context and va to VSID */
 530 2:      mulli   r3,r3,897*16            /* multiply context by context skew */
 531         rlwinm  r0,r4,4,28,31           /* get ESID (top 4 bits of va) */
 532         mulli   r0,r0,0x111             /* multiply by ESID skew */
 533         add     r3,r3,r0                /* note code below trims to 24 bits */
 534
 535         /* Construct the high word of the PPC-style PTE (r11) */
 536         rlwinm  r11,r3,7,1,24           /* put VSID in 0x7fffff80 bits */
 537         rlwimi  r11,r4,10,26,31         /* put in API (abbrev page index) */
 538         SET_V(r11)                      /* set V (valid) bit */
 539
 540 #ifdef CONFIG_SMP
 541         lis     r9, (mmu_hash_lock - PAGE_OFFSET)@ha
 542         addi    r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l
 543         tophys  (r8, r2)
 544         lwz     r8, TASK_CPU(r8)
 545         oris    r8,r8,9
 546 10:     lwarx   r0,0,r9
 547         cmpi    0,r0,0
 548         bne-    11f
 549         stwcx.  r8,0,r9
 550         beq+    12f
 551 11:     lwz     r0,0(r9)
 552         cmpi    0,r0,0
 553         beq     10b
 554         b       11b
 555 12:     isync
 556 #endif
 557
 558         /*
 559          * Check the _PAGE_HASHPTE bit in the linux PTE.  If it is
 560          * already clear, we're done (for this pte).  If not,
 561          * clear it (atomically) and proceed.  -- paulus.
 562          */
 563 #if (PTE_FLAGS_OFFSET != 0)
 564         addi    r5,r5,PTE_FLAGS_OFFSET
 565 #endif
 566 33:     lwarx   r8,0,r5                 /* fetch the pte flags word */
 567         andi.   r0,r8,_PAGE_HASHPTE
 568         beq     8f                      /* done if HASHPTE is already clear */
 569         rlwinm  r8,r8,0,31,29           /* clear HASHPTE bit */
 570         stwcx.  r8,0,r5                 /* update the pte */
 571         bne-    33b
 572
 573         patch_site      0f, patch__flush_hash_A0
 574         patch_site      1f, patch__flush_hash_A1
 575         patch_site      2f, patch__flush_hash_A2
 576         /* Get the address of the primary PTE group in the hash table (r3) */
 577 0:      lis     r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
 578 1:      rlwimi  r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 579 2:      rlwinm  r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
 580         xor     r8,r0,r8                /* make primary hash */
 581
 582         /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
 583         li      r0,8                    /* PTEs/group */
 584         mtctr   r0
 585         addi    r12,r8,-HPTE_SIZE
 586 1:      LDPTEu  r0,HPTE_SIZE(r12)       /* get next PTE */
 587         CMPPTE  0,r0,r11
 588         bdnzf   2,1b                    /* loop while ctr != 0 && !cr0.eq */
 589         beq+    3f
 590
 591         patch_site      0f, patch__flush_hash_B
 592         /* Search the secondary PTEG for a matching PTE */
 593         ori     r11,r11,PTE_H           /* set H (secondary hash) bit */
 594         li      r0,8                    /* PTEs/group */
 595 0:      xoris   r12,r8,Hash_msk>>16     /* compute secondary hash */
 596         xori    r12,r12,(-PTEG_SIZE & 0xffff)
 597         addi    r12,r12,-HPTE_SIZE
 598         mtctr   r0
 599 2:      LDPTEu  r0,HPTE_SIZE(r12)
 600         CMPPTE  0,r0,r11
 601         bdnzf   2,2b
 602         xori    r11,r11,PTE_H           /* clear H again */
 603         bne-    4f                      /* should rarely fail to find it */
 604
 605 3:      li      r0,0
 606         STPTE   r0,0(r12)               /* invalidate entry */
 607 4:      sync
 608         tlbie   r4                      /* in hw tlb too */
 609         sync
 610
 611 8:      ble     cr1,9f                  /* if all ptes checked */
 612 81:     addi    r6,r6,-1
 613         addi    r5,r5,PTE_SIZE
 614         addi    r4,r4,0x1000
 615         lwz     r0,0(r5)                /* check next pte */
 616         cmpwi   cr1,r6,1
 617         andi.   r0,r0,_PAGE_HASHPTE
 618         bne     33b
 619         bgt     cr1,81b
 620
 621 9:
 622 #ifdef CONFIG_SMP
 623         TLBSYNC
 624         li      r0,0
 625         stw     r0,0(r9)                /* clear mmu_hash_lock */
 626 #endif
 627
 628 19:     mtmsr   r10
 629         SYNC_601
 630         isync
 631         blr
 632 EXPORT_SYMBOL(flush_hash_pages)
 633
 634 /*
 635  * Flush an entry from the TLB
 636  */
 637 _GLOBAL(_tlbie)
 638 #ifdef CONFIG_SMP
 639         lwz     r8,TASK_CPU(r2)
 640         oris    r8,r8,11
 641         mfmsr   r10
 642         SYNC
 643         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 644         rlwinm  r0,r0,0,28,26           /* clear DR */
 645         mtmsr   r0
 646         SYNC_601
 647         isync
 648         lis     r9,mmu_hash_lock@h
 649         ori     r9,r9,mmu_hash_lock@l
 650         tophys(r9,r9)
 651 10:     lwarx   r7,0,r9
 652         cmpwi   0,r7,0
 653         bne-    10b
 654         stwcx.  r8,0,r9
 655         bne-    10b
 656         eieio
 657         tlbie   r3
 658         sync
 659         TLBSYNC
 660         li      r0,0
 661         stw     r0,0(r9)                /* clear mmu_hash_lock */
 662         mtmsr   r10
 663         SYNC_601
 664         isync
 665 #else /* CONFIG_SMP */
 666         tlbie   r3
 667         sync
 668 #endif /* CONFIG_SMP */
 669         blr
 670
 671 /*
 672  * Flush the entire TLB. 603/603e only
 673  */
 674 _GLOBAL(_tlbia)
 675 #if defined(CONFIG_SMP)
 676         lwz     r8,TASK_CPU(r2)
 677         oris    r8,r8,10
 678         mfmsr   r10
 679         SYNC
 680         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 681         rlwinm  r0,r0,0,28,26           /* clear DR */
 682         mtmsr   r0
 683         SYNC_601
 684         isync
 685         lis     r9,mmu_hash_lock@h
 686         ori     r9,r9,mmu_hash_lock@l
 687         tophys(r9,r9)
 688 10:     lwarx   r7,0,r9
 689         cmpwi   0,r7,0
 690         bne-    10b
 691         stwcx.  r8,0,r9
 692         bne-    10b
 693 #endif /* CONFIG_SMP */
 694         li      r5, 32
 695         lis     r4, KERNELBASE@h
 696         mtctr   r5
 697         sync
 698 0:      tlbie   r4
 699         addi    r4, r4, 0x1000
 700         bdnz    0b
 701         sync
 702 #ifdef CONFIG_SMP
 703         TLBSYNC
 704         li      r0,0
 705         stw     r0,0(r9)                /* clear mmu_hash_lock */
 706         mtmsr   r10
 707         SYNC_601
 708         isync
 709 #endif /* CONFIG_SMP */
 710         blr