]>
git.ipfire.org Git - thirdparty/u-boot.git/blob - arch/ppc/cpu/mpc8xx/fec.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 DECLARE_GLOBAL_DATA_PTR
;
34 #if defined(CONFIG_CMD_NET) && \
35 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
37 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
38 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
39 #define CONFIG_ETHER_ON_FEC1 1
42 /* define WANT_MII when MII support is required */
43 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
52 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
53 #error "CONFIG_MII has to be defined!"
58 #if defined(CONFIG_RMII) && !defined(WANT_MII)
59 #error RMII support is unusable without a working PHY.
62 #ifdef CONFIG_SYS_DISCOVER_PHY
63 static int mii_discover_phy(struct eth_device
*dev
);
66 int fec8xx_miiphy_read(char *devname
, unsigned char addr
,
67 unsigned char reg
, unsigned short *value
);
68 int fec8xx_miiphy_write(char *devname
, unsigned char addr
,
69 unsigned char reg
, unsigned short value
);
71 static struct ether_fcc_info_s
80 #if defined(CONFIG_ETHER_ON_FEC1)
83 offsetof(immap_t
, im_cpm
.cp_fec1
),
84 #if defined(CONFIG_FEC1_PHY)
94 #if defined(CONFIG_ETHER_ON_FEC2)
97 offsetof(immap_t
, im_cpm
.cp_fec2
),
98 #if defined(CONFIG_FEC2_PHY)
109 /* Ethernet Transmit and Receive Buffers */
110 #define DBUF_LENGTH 1520
114 #define TOUT_LOOP 100
116 #define PKT_MAXBUF_SIZE 1518
117 #define PKT_MINBUF_SIZE 64
118 #define PKT_MAXBLR_SIZE 1520
121 static char txbuf
[DBUF_LENGTH
] __attribute__ ((aligned(8)));
123 #error txbuf must be aligned.
126 static uint rxIdx
; /* index of the current RX buffer */
127 static uint txIdx
; /* index of the current TX buffer */
130 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
131 * immr->udata_bd address on Dual-Port RAM
132 * Provide for Double Buffering
135 typedef volatile struct CommonBufferDescriptor
{
136 cbd_t rxbd
[PKTBUFSRX
]; /* Rx BD */
137 cbd_t txbd
[TX_BUF_CNT
]; /* Tx BD */
140 static RTXBD
*rtx
= NULL
;
142 static int fec_send(struct eth_device
* dev
, volatile void *packet
, int length
);
143 static int fec_recv(struct eth_device
* dev
);
144 static int fec_init(struct eth_device
* dev
, bd_t
* bd
);
145 static void fec_halt(struct eth_device
* dev
);
146 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
147 static void __mii_init(void);
150 int fec_initialize(bd_t
*bis
)
152 struct eth_device
* dev
;
153 struct ether_fcc_info_s
*efis
;
156 for (i
= 0; i
< sizeof(ether_fcc_info
) / sizeof(ether_fcc_info
[0]); i
++) {
158 dev
= malloc(sizeof(*dev
));
162 memset(dev
, 0, sizeof(*dev
));
164 /* for FEC1 make sure that the name of the interface is the same
165 as the old one for compatibility reasons */
167 sprintf (dev
->name
, "FEC ETHERNET");
169 sprintf (dev
->name
, "FEC%d ETHERNET",
170 ether_fcc_info
[i
].ether_index
+ 1);
173 efis
= ðer_fcc_info
[i
];
176 * reset actual phy addr
178 efis
->actual_phy_addr
= -1;
181 dev
->init
= fec_init
;
182 dev
->halt
= fec_halt
;
183 dev
->send
= fec_send
;
184 dev
->recv
= fec_recv
;
188 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
189 miiphy_register(dev
->name
,
190 fec8xx_miiphy_read
, fec8xx_miiphy_write
);
196 static int fec_send(struct eth_device
* dev
, volatile void *packet
, int length
)
199 struct ether_fcc_info_s
*efis
= dev
->priv
;
200 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
206 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
<TOUT_LOOP
)) {
211 printf("TX not ready\n");
214 rtx
->txbd
[txIdx
].cbd_bufaddr
= (uint
)packet
;
215 rtx
->txbd
[txIdx
].cbd_datlen
= length
;
216 rtx
->txbd
[txIdx
].cbd_sc
|= BD_ENET_TX_READY
| BD_ENET_TX_LAST
;
219 /* Activate transmit Buffer Descriptor polling */
220 fecp
->fec_x_des_active
= 0x01000000; /* Descriptor polling active */
223 while ((rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_READY
) && (j
<TOUT_LOOP
)) {
224 #if defined(CONFIG_ICU862)
232 printf("TX timeout\n");
235 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
236 __FILE__
,__LINE__
,__FUNCTION__
,j
,rtx
->txbd
[txIdx
].cbd_sc
,
237 (rtx
->txbd
[txIdx
].cbd_sc
& 0x003C)>>2);
239 /* return only status bits */;
240 rc
= (rtx
->txbd
[txIdx
].cbd_sc
& BD_ENET_TX_STATS
);
242 txIdx
= (txIdx
+ 1) % TX_BUF_CNT
;
247 static int fec_recv (struct eth_device
*dev
)
249 struct ether_fcc_info_s
*efis
= dev
->priv
;
250 volatile fec_t
*fecp
=
251 (volatile fec_t
*) (CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
255 /* section 16.9.23.2 */
256 if (rtx
->rxbd
[rxIdx
].cbd_sc
& BD_ENET_RX_EMPTY
) {
258 break; /* nothing received - leave for() loop */
261 length
= rtx
->rxbd
[rxIdx
].cbd_datlen
;
263 if (rtx
->rxbd
[rxIdx
].cbd_sc
& 0x003f) {
265 printf ("%s[%d] err: %x\n",
266 __FUNCTION__
, __LINE__
,
267 rtx
->rxbd
[rxIdx
].cbd_sc
);
270 volatile uchar
*rx
= NetRxPackets
[rxIdx
];
274 #if defined(CONFIG_CMD_CDP)
276 && memcmp ((uchar
*) rx
, NetBcastAddr
, 6) != 0
277 && memcmp ((uchar
*) rx
, NetCDPAddr
, 6) != 0)
281 * Pass the packet up to the protocol layers.
284 NetReceive (rx
, length
);
287 /* Give the buffer back to the FEC. */
288 rtx
->rxbd
[rxIdx
].cbd_datlen
= 0;
290 /* wrap around buffer index when necessary */
291 if ((rxIdx
+ 1) >= PKTBUFSRX
) {
292 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
=
293 (BD_ENET_RX_WRAP
| BD_ENET_RX_EMPTY
);
296 rtx
->rxbd
[rxIdx
].cbd_sc
= BD_ENET_RX_EMPTY
;
302 /* Try to fill Buffer Descriptors */
303 fecp
->fec_r_des_active
= 0x01000000; /* Descriptor polling active */
309 /**************************************************************
311 * FEC Ethernet Initialization Routine
313 *************************************************************/
315 #define FEC_ECNTRL_PINMUX 0x00000004
316 #define FEC_ECNTRL_ETHER_EN 0x00000002
317 #define FEC_ECNTRL_RESET 0x00000001
319 #define FEC_RCNTRL_BC_REJ 0x00000010
320 #define FEC_RCNTRL_PROM 0x00000008
321 #define FEC_RCNTRL_MII_MODE 0x00000004
322 #define FEC_RCNTRL_DRT 0x00000002
323 #define FEC_RCNTRL_LOOP 0x00000001
325 #define FEC_TCNTRL_FDEN 0x00000004
326 #define FEC_TCNTRL_HBC 0x00000002
327 #define FEC_TCNTRL_GTS 0x00000001
329 #define FEC_RESET_DELAY 50
331 #if defined(CONFIG_RMII)
333 static inline void fec_10Mbps(struct eth_device
*dev
)
335 struct ether_fcc_info_s
*efis
= dev
->priv
;
336 int fecidx
= efis
->ether_index
;
337 uint mask
= (fecidx
== 0) ? 0x0000010 : 0x0000008;
339 if ((unsigned int)fecidx
>= 2)
342 ((volatile immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_cptr
|= mask
;
345 static inline void fec_100Mbps(struct eth_device
*dev
)
347 struct ether_fcc_info_s
*efis
= dev
->priv
;
348 int fecidx
= efis
->ether_index
;
349 uint mask
= (fecidx
== 0) ? 0x0000010 : 0x0000008;
351 if ((unsigned int)fecidx
>= 2)
354 ((volatile immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_cptr
&= ~mask
;
359 static inline void fec_full_duplex(struct eth_device
*dev
)
361 struct ether_fcc_info_s
*efis
= dev
->priv
;
362 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
364 fecp
->fec_r_cntrl
&= ~FEC_RCNTRL_DRT
;
365 fecp
->fec_x_cntrl
|= FEC_TCNTRL_FDEN
; /* FD enable */
368 static inline void fec_half_duplex(struct eth_device
*dev
)
370 struct ether_fcc_info_s
*efis
= dev
->priv
;
371 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
373 fecp
->fec_r_cntrl
|= FEC_RCNTRL_DRT
;
374 fecp
->fec_x_cntrl
&= ~FEC_TCNTRL_FDEN
; /* FD disable */
377 static void fec_pin_init(int fecidx
)
380 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
381 volatile fec_t
*fecp
;
384 * only two FECs please
386 if ((unsigned int)fecidx
>= 2)
390 fecp
= &immr
->im_cpm
.cp_fec1
;
392 fecp
= &immr
->im_cpm
.cp_fec2
;
395 * Set MII speed to 2.5 MHz or slightly below.
396 * * According to the MPC860T (Rev. D) Fast ethernet controller user
398 * * the MII management interface clock must be less than or equal
400 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
401 * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
403 * All MII configuration is done via FEC1 registers:
405 immr
->im_cpm
.cp_fec1
.fec_mii_speed
= ((bd
->bi_intfreq
+ 4999999) / 5000000) << 1;
407 #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
408 /* our PHYs are the limit at 2.5 MHz */
409 fecp
->fec_mii_speed
<<= 1;
412 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
413 /* use MDC for MII */
414 immr
->im_ioport
.iop_pdpar
|= 0x0080;
415 immr
->im_ioport
.iop_pddir
&= ~0x0080;
419 #if defined(CONFIG_ETHER_ON_FEC1)
421 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
423 #if !defined(CONFIG_RMII)
425 immr
->im_ioport
.iop_papar
|= 0xf830;
426 immr
->im_ioport
.iop_padir
|= 0x0830;
427 immr
->im_ioport
.iop_padir
&= ~0xf000;
429 immr
->im_cpm
.cp_pbpar
|= 0x00001001;
430 immr
->im_cpm
.cp_pbdir
&= ~0x00001001;
432 immr
->im_ioport
.iop_pcpar
|= 0x000c;
433 immr
->im_ioport
.iop_pcdir
&= ~0x000c;
435 immr
->im_cpm
.cp_pepar
|= 0x00000003;
436 immr
->im_cpm
.cp_pedir
|= 0x00000003;
437 immr
->im_cpm
.cp_peso
&= ~0x00000003;
439 immr
->im_cpm
.cp_cptr
&= ~0x00000100;
443 #if !defined(CONFIG_FEC1_PHY_NORXERR)
444 immr
->im_ioport
.iop_papar
|= 0x1000;
445 immr
->im_ioport
.iop_padir
&= ~0x1000;
447 immr
->im_ioport
.iop_papar
|= 0xe810;
448 immr
->im_ioport
.iop_padir
|= 0x0810;
449 immr
->im_ioport
.iop_padir
&= ~0xe000;
451 immr
->im_cpm
.cp_pbpar
|= 0x00000001;
452 immr
->im_cpm
.cp_pbdir
&= ~0x00000001;
454 immr
->im_cpm
.cp_cptr
|= 0x00000100;
455 immr
->im_cpm
.cp_cptr
&= ~0x00000050;
457 #endif /* !CONFIG_RMII */
459 #elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
461 * Configure all of port D for MII.
463 immr
->im_ioport
.iop_pdpar
= 0x1fff;
466 * Bits moved from Rev. D onward
468 if ((get_immr(0) & 0xffff) < 0x0501)
469 immr
->im_ioport
.iop_pddir
= 0x1c58; /* Pre rev. D */
471 immr
->im_ioport
.iop_pddir
= 0x1fff; /* Rev. D and later */
474 * Configure port A for MII.
477 #if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
480 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
481 * * of CPU, so for this board we need to configure Utopia and
482 * * enable PD8 to MII-MDC function
484 immr
->im_ioport
.iop_pdpar
|= 0x4080;
488 * Has Utopia been configured?
490 if (immr
->im_ioport
.iop_pdpar
& (0x8000 >> 1)) {
492 * YES - Use MUXED mode for UTOPIA bus.
493 * This frees Port A for use by MII (see 862UM table 41-6).
495 immr
->im_ioport
.utmode
&= ~0x80;
498 * NO - set SPLIT mode for UTOPIA bus.
500 * This doesn't really effect UTOPIA (which isn't
501 * enabled anyway) but just tells the 862
502 * to use port A for MII (see 862UM table 41-6).
504 immr
->im_ioport
.utmode
|= 0x80;
506 #endif /* !defined(CONFIG_ICU862) */
508 #endif /* CONFIG_ETHER_ON_FEC1 */
509 } else if (fecidx
== 1) {
511 #if defined(CONFIG_ETHER_ON_FEC2)
513 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
515 #if !defined(CONFIG_RMII)
516 immr
->im_cpm
.cp_pepar
|= 0x0003fffc;
517 immr
->im_cpm
.cp_pedir
|= 0x0003fffc;
518 immr
->im_cpm
.cp_peso
&= ~0x000087fc;
519 immr
->im_cpm
.cp_peso
|= 0x00037800;
521 immr
->im_cpm
.cp_cptr
&= ~0x00000080;
524 #if !defined(CONFIG_FEC2_PHY_NORXERR)
525 immr
->im_cpm
.cp_pepar
|= 0x00000010;
526 immr
->im_cpm
.cp_pedir
|= 0x00000010;
527 immr
->im_cpm
.cp_peso
&= ~0x00000010;
529 immr
->im_cpm
.cp_pepar
|= 0x00039620;
530 immr
->im_cpm
.cp_pedir
|= 0x00039620;
531 immr
->im_cpm
.cp_peso
|= 0x00031000;
532 immr
->im_cpm
.cp_peso
&= ~0x00008620;
534 immr
->im_cpm
.cp_cptr
|= 0x00000080;
535 immr
->im_cpm
.cp_cptr
&= ~0x00000028;
536 #endif /* CONFIG_RMII */
538 #endif /* CONFIG_MPC885_FAMILY */
540 #endif /* CONFIG_ETHER_ON_FEC2 */
545 static int fec_reset(volatile fec_t
*fecp
)
550 * A delay is required between a reset of the FEC block and
551 * initialization of other FEC registers because the reset takes
552 * some time to complete. If you don't delay, subsequent writes
553 * to FEC registers might get killed by the reset routine which is
557 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_RESET
;
559 (fecp
->fec_ecntrl
& FEC_ECNTRL_RESET
) && (i
< FEC_RESET_DELAY
);
563 if (i
== FEC_RESET_DELAY
)
569 static int fec_init (struct eth_device
*dev
, bd_t
* bd
)
571 struct ether_fcc_info_s
*efis
= dev
->priv
;
572 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
573 volatile fec_t
*fecp
=
574 (volatile fec_t
*) (CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
577 if (efis
->ether_index
== 0) {
578 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
579 #if defined(CONFIG_MPC885ADS)
580 *(vu_char
*) BCSR5
&= ~(BCSR5_MII1_EN
| BCSR5_MII1_RST
);
582 /* configure FADS for fast (FEC) ethernet, half-duplex */
583 /* The LXT970 needs about 50ms to recover from reset, so
584 * wait for it by discovering the PHY before leaving eth_init().
587 volatile uint
*bcsr4
= (volatile uint
*) BCSR4
;
589 *bcsr4
= (*bcsr4
& ~(BCSR4_FETH_EN
| BCSR4_FETHCFG1
))
590 | (BCSR4_FETHCFG0
| BCSR4_FETHFDE
|
593 /* reset the LXT970 PHY */
594 *bcsr4
&= ~BCSR4_FETHRST
;
596 *bcsr4
|= BCSR4_FETHRST
;
599 #endif /* CONFIG_MPC885ADS */
600 #endif /* CONFIG_FADS */
603 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
604 /* the MII interface is connected to FEC1
605 * so for the miiphy_xxx function to work we must
606 * call mii_init since fec_halt messes the thing up
608 if (efis
->ether_index
!= 0)
612 if (fec_reset(fecp
) < 0)
613 printf ("FEC_RESET_DELAY timeout\n");
615 /* We use strictly polling mode only
619 /* Clear any pending interrupt
621 fecp
->fec_ievent
= 0xffc0;
623 /* No need to set the IVEC register */
625 /* Set station address
627 #define ea dev->enetaddr
628 fecp
->fec_addr_low
= (ea
[0] << 24) | (ea
[1] << 16) | (ea
[2] << 8) | (ea
[3]);
629 fecp
->fec_addr_high
= (ea
[4] << 8) | (ea
[5]);
632 #if defined(CONFIG_CMD_CDP)
634 * Turn on multicast address hash table
636 fecp
->fec_hash_table_high
= 0xffffffff;
637 fecp
->fec_hash_table_low
= 0xffffffff;
639 /* Clear multicast address hash table
641 fecp
->fec_hash_table_high
= 0;
642 fecp
->fec_hash_table_low
= 0;
645 /* Set maximum receive buffer size.
647 fecp
->fec_r_buff_size
= PKT_MAXBLR_SIZE
;
649 /* Set maximum frame length
651 fecp
->fec_r_hash
= PKT_MAXBUF_SIZE
;
654 * Setup Buffers and Buffer Desriptors
660 #ifdef CONFIG_SYS_ALLOC_DPRAM
661 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+
662 dpram_alloc_align (sizeof (RTXBD
), 8));
664 rtx
= (RTXBD
*) (immr
->im_cpm
.cp_dpmem
+ CPM_FEC_BASE
);
668 * Setup Receiver Buffer Descriptors (13.14.24.18)
672 for (i
= 0; i
< PKTBUFSRX
; i
++) {
673 rtx
->rxbd
[i
].cbd_sc
= BD_ENET_RX_EMPTY
;
674 rtx
->rxbd
[i
].cbd_datlen
= 0; /* Reset */
675 rtx
->rxbd
[i
].cbd_bufaddr
= (uint
) NetRxPackets
[i
];
677 rtx
->rxbd
[PKTBUFSRX
- 1].cbd_sc
|= BD_ENET_RX_WRAP
;
680 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
684 for (i
= 0; i
< TX_BUF_CNT
; i
++) {
685 rtx
->txbd
[i
].cbd_sc
= BD_ENET_TX_LAST
| BD_ENET_TX_TC
;
686 rtx
->txbd
[i
].cbd_datlen
= 0; /* Reset */
687 rtx
->txbd
[i
].cbd_bufaddr
= (uint
) (&txbuf
[0]);
689 rtx
->txbd
[TX_BUF_CNT
- 1].cbd_sc
|= BD_ENET_TX_WRAP
;
691 /* Set receive and transmit descriptor base
693 fecp
->fec_r_des_start
= (unsigned int) (&rtx
->rxbd
[0]);
694 fecp
->fec_x_des_start
= (unsigned int) (&rtx
->txbd
[0]);
698 #if 0 /* Full duplex mode */
699 fecp
->fec_r_cntrl
= FEC_RCNTRL_MII_MODE
;
700 fecp
->fec_x_cntrl
= FEC_TCNTRL_FDEN
;
701 #else /* Half duplex mode */
702 fecp
->fec_r_cntrl
= FEC_RCNTRL_MII_MODE
| FEC_RCNTRL_DRT
;
703 fecp
->fec_x_cntrl
= 0;
706 /* Enable big endian and don't care about SDMA FC.
708 fecp
->fec_fun_code
= 0x78000000;
711 * Setup the pin configuration of the FEC
713 fec_pin_init (efis
->ether_index
);
719 * Now enable the transmit and receive processing
721 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_ETHER_EN
;
723 if (efis
->phy_addr
== -1) {
724 #ifdef CONFIG_SYS_DISCOVER_PHY
726 * wait for the PHY to wake up after reset
728 efis
->actual_phy_addr
= mii_discover_phy (dev
);
730 if (efis
->actual_phy_addr
== -1) {
731 printf ("Unable to discover phy!\n");
735 efis
->actual_phy_addr
= -1;
738 efis
->actual_phy_addr
= efis
->phy_addr
;
741 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
743 * adapt the RMII speed to the speed of the phy
745 if (miiphy_speed (dev
->name
, efis
->actual_phy_addr
) == _100BASET
) {
752 #if defined(CONFIG_MII)
754 * adapt to the half/full speed settings
756 if (miiphy_duplex (dev
->name
, efis
->actual_phy_addr
) == FULL
) {
757 fec_full_duplex (dev
);
759 fec_half_duplex (dev
);
763 /* And last, try to fill Rx Buffer Descriptors */
764 fecp
->fec_r_des_active
= 0x01000000; /* Descriptor polling active */
766 efis
->initialized
= 1;
772 static void fec_halt(struct eth_device
* dev
)
774 struct ether_fcc_info_s
*efis
= dev
->priv
;
775 volatile fec_t
*fecp
= (volatile fec_t
*)(CONFIG_SYS_IMMR
+ efis
->fecp_offset
);
778 /* avoid halt if initialized; mii gets stuck otherwise */
779 if (!efis
->initialized
)
783 * A delay is required between a reset of the FEC block and
784 * initialization of other FEC registers because the reset takes
785 * some time to complete. If you don't delay, subsequent writes
786 * to FEC registers might get killed by the reset routine which is
790 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_RESET
;
792 (fecp
->fec_ecntrl
& FEC_ECNTRL_RESET
) && (i
< FEC_RESET_DELAY
);
796 if (i
== FEC_RESET_DELAY
) {
797 printf ("FEC_RESET_DELAY timeout\n");
801 efis
->initialized
= 0;
804 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
806 /* Make MII read/write commands for the FEC.
809 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
812 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
813 (REG & 0x1f) << 18) | \
816 /* Interrupt events/masks.
818 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
819 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
820 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
821 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
822 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
823 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
824 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
825 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
826 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
827 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
829 /* PHY identification
831 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
832 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
833 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
834 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
835 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
836 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
837 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
838 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
839 #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
841 /* send command to phy using mii, wait for result */
843 mii_send(uint mii_cmd
)
849 ep
= &(((immap_t
*)CONFIG_SYS_IMMR
)->im_cpm
.cp_fec
);
851 ep
->fec_mii_data
= mii_cmd
; /* command to phy */
853 /* wait for mii complete */
855 while (!(ep
->fec_ievent
& FEC_ENET_MII
)) {
857 printf("mii_send STUCK!\n");
861 mii_reply
= ep
->fec_mii_data
; /* result from phy */
862 ep
->fec_ievent
= FEC_ENET_MII
; /* clear MII complete */
864 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
865 __FILE__
,__LINE__
,__FUNCTION__
,mii_cmd
,mii_reply
);
867 return (mii_reply
& 0xffff); /* data read from phy */
871 #if defined(CONFIG_SYS_DISCOVER_PHY)
872 static int mii_discover_phy(struct eth_device
*dev
)
874 #define MAX_PHY_PASSES 11
880 phyaddr
= -1; /* didn't find a PHY yet */
881 for (pass
= 1; pass
<= MAX_PHY_PASSES
&& phyaddr
< 0; ++pass
) {
883 /* PHY may need more time to recover from reset.
884 * The LXT970 needs 50ms typical, no maximum is
885 * specified, so wait 10ms before try again.
886 * With 11 passes this gives it 100ms to wake up.
888 udelay(10000); /* wait 10ms */
890 for (phyno
= 0; phyno
< 32 && phyaddr
< 0; ++phyno
) {
891 phytype
= mii_send(mk_mii_read(phyno
, PHY_PHYIDR2
));
893 printf("PHY type 0x%x pass %d type ", phytype
, pass
);
895 if (phytype
!= 0xffff) {
897 phytype
|= mii_send(mk_mii_read(phyno
,
901 printf("PHY @ 0x%x pass %d type ",phyno
,pass
);
902 switch (phytype
& 0xfffffff0) {
915 case PHY_ID_AMD79C784
:
916 printf("AMD79C784\n");
918 case PHY_ID_LSI80225B
:
919 printf("LSI L80225/B\n");
922 printf("Davicom DM9161\n");
924 case PHY_ID_KSM8995M
:
925 printf("MICREL KS8995M\n");
928 printf("0x%08x\n", phytype
);
936 printf("No PHY device found.\n");
940 #endif /* CONFIG_SYS_DISCOVER_PHY */
942 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
944 /****************************************************************************
945 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
946 * This function is a subset of eth_init
947 ****************************************************************************
949 static void __mii_init(void)
951 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
952 volatile fec_t
*fecp
= &(immr
->im_cpm
.cp_fec
);
954 if (fec_reset(fecp
) < 0)
955 printf ("FEC_RESET_DELAY timeout\n");
957 /* We use strictly polling mode only
961 /* Clear any pending interrupt
963 fecp
->fec_ievent
= 0xffc0;
965 /* Now enable the transmit and receive processing
967 fecp
->fec_ecntrl
= FEC_ECNTRL_PINMUX
| FEC_ECNTRL_ETHER_EN
;
976 /* Setup the pin configuration of the FEC(s)
978 for (i
= 0; i
< sizeof(ether_fcc_info
) / sizeof(ether_fcc_info
[0]); i
++)
979 fec_pin_init(ether_fcc_info
[i
].ether_index
);
982 /*****************************************************************************
983 * Read and write a MII PHY register, routines used by MII Utilities
985 * FIXME: These routines are expected to return 0 on success, but mii_send
986 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
987 * no PHY connected...
988 * For now always return 0.
989 * FIXME: These routines only work after calling eth_init() at least once!
990 * Otherwise they hang in mii_send() !!! Sorry!
991 *****************************************************************************/
993 int fec8xx_miiphy_read(char *devname
, unsigned char addr
,
994 unsigned char reg
, unsigned short *value
)
996 short rdreg
; /* register working value */
999 printf ("miiphy_read(0x%x) @ 0x%x = ", reg
, addr
);
1001 rdreg
= mii_send(mk_mii_read(addr
, reg
));
1005 printf ("0x%04x\n", *value
);
1010 int fec8xx_miiphy_write(char *devname
, unsigned char addr
,
1011 unsigned char reg
, unsigned short value
)
1013 short rdreg
; /* register working value */
1015 printf ("miiphy_write(0x%x) @ 0x%x = ", reg
, addr
);
1017 rdreg
= mii_send(mk_mii_write(addr
, reg
, value
));
1020 printf ("0x%04x\n", value
);