2 * Copyright 2008, 2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
11 #include <asm/fsl_ddr_sdram.h>
15 /* Board-specific functions defined in each board's ddr.c */
16 extern void fsl_ddr_board_options(memctl_options_t
*popts
,
18 unsigned int ctrl_num
);
20 unsigned int populate_memctl_options(int all_DIMMs_registered
,
21 memctl_options_t
*popts
,
23 unsigned int ctrl_num
)
28 /* Chip select options. */
30 /* Pick chip-select local options. */
31 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
32 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
34 /* only for single CS? */
35 popts
->cs_local_opts
[i
].odt_rd_cfg
= 0;
37 popts
->cs_local_opts
[i
].odt_wr_cfg
= 1;
38 popts
->cs_local_opts
[i
].auto_precharge
= 0;
41 /* Pick interleaving mode. */
45 * 1 = interleaving between 2 controllers
47 popts
->memctl_interleaving
= 0;
53 * 3 = superbank (only if CS interleaving is enabled)
55 popts
->memctl_interleaving_mode
= 0;
58 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
59 * 1: page: bit to the left of the column bits selects the memctl
60 * 2: bank: bit to the left of the bank bits selects the memctl
61 * 3: superbank: bit to the left of the chip select selects the memctl
63 * NOTE: ba_intlv (rank interleaving) is independent of memory
64 * controller interleaving; it is only within a memory controller.
65 * Must use superbank interleaving if rank interleaving is used and
66 * memory controller interleaving is enabled.
73 * 0x60 = CS0,CS1 + CS2,CS3
74 * 0x04 = CS0,CS1,CS2,CS3
76 popts
->ba_intlv_ctl
= 0;
78 /* Memory Organization Parameters */
79 popts
->registered_dimm_en
= all_DIMMs_registered
;
81 /* Operational Mode Paramters */
85 popts
->ECC_mode
= 1; /* 0 = disabled, 1 = enabled */
87 popts
->ECC_mode
= 0; /* 0 = disabled, 1 = enabled */
89 popts
->ECC_init_using_memctl
= 1; /* 0 = use DMA, 1 = use memctl */
96 #if defined(CONFIG_FSL_DDR1)
97 popts
->DQS_config
= 0;
98 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
99 popts
->DQS_config
= 1;
102 /* Choose self-refresh during sleep. */
103 popts
->self_refresh_in_sleep
= 1;
105 /* Choose dynamic power management mode. */
106 popts
->dynamic_power
= 0;
108 /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
109 popts
->data_bus_width
= 0;
111 /* Choose burst length. */
112 #if defined(CONFIG_FSL_DDR3)
113 #if defined(CONFIG_E500MC)
114 popts
->OTF_burst_chop_en
= 0; /* on-the-fly burst chop disable */
115 popts
->burst_length
= DDR_BL8
; /* Fixed 8-beat burst len */
117 popts
->OTF_burst_chop_en
= 1; /* on-the-fly burst chop */
118 popts
->burst_length
= DDR_OTF
; /* on-the-fly BC4 and BL8 */
121 popts
->burst_length
= DDR_BL4
; /* has to be 4 for DDR2 */
124 /* Choose ddr controller address mirror mode */
125 #if defined(CONFIG_FSL_DDR3)
126 popts
->mirrored_dimm
= pdimm
[0].mirrored_dimm
;
129 /* Global Timing Parameters. */
130 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
132 /* Pick a caslat override. */
133 popts
->cas_latency_override
= 0;
134 popts
->cas_latency_override_value
= 3;
135 if (popts
->cas_latency_override
) {
136 debug("using caslat override value = %u\n",
137 popts
->cas_latency_override_value
);
140 /* Decide whether to use the computed derated latency */
141 popts
->use_derated_caslat
= 0;
143 /* Choose an additive latency. */
144 popts
->additive_latency_override
= 0;
145 popts
->additive_latency_override_value
= 3;
146 if (popts
->additive_latency_override
) {
147 debug("using additive latency override value = %u\n",
148 popts
->additive_latency_override_value
);
154 * Factors to consider for 2T_EN:
155 * - number of DIMMs installed
156 * - number of components, number of active ranks
157 * - how much time you want to spend playing around
160 popts
->threeT_en
= 0;
163 * BSTTOPRE precharge interval
165 * Set this to 0 for global auto precharge
167 * FIXME: Should this be configured in picoseconds?
168 * Why it should be in ps: better understanding of this
169 * relative to actual DRAM timing parameters such as tRAS.
170 * e.g. tRAS(min) = 40 ns
172 popts
->bstopre
= 0x100;
174 /* Minimum CKE pulse width -- tCKE(MIN) */
175 popts
->tCKE_clock_pulse_width_ps
176 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR
);
179 * Window for four activates -- tFAW
181 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
182 * FIXME: varies depending upon number of column addresses or data
183 * FIXME: width, was considering looking at pdimm->primary_sdram_width
185 #if defined(CONFIG_FSL_DDR1)
186 popts
->tFAW_window_four_activates_ps
= mclk_to_picos(1);
188 #elif defined(CONFIG_FSL_DDR2)
190 * x4/x8; some datasheets have 35000
191 * x16 wide columns only? Use 50000?
193 popts
->tFAW_window_four_activates_ps
= 37500;
195 #elif defined(CONFIG_FSL_DDR3)
196 popts
->tFAW_window_four_activates_ps
= pdimm
[0].tFAW_ps
;
200 #if defined(CONFIG_FSL_DDR3)
202 * due to ddr3 dimm is fly-by topology
203 * we suggest to enable write leveling to
204 * meet the tQDSS under different loading.
207 popts
->wrlvl_override
= 0;
211 * Check interleaving configuration from environment.
212 * Please refer to doc/README.fsl-ddr for the detail.
214 * If memory controller interleaving is enabled, then the data
215 * bus widths must be programmed identically for the 2 memory
218 * XXX: Attempt to set both controllers to the same chip select
219 * interleaving mode. It will do a best effort to get the
220 * requested ranks interleaved together such that the result
221 * should be a subset of the requested configuration.
223 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
224 if ((p
= getenv("memctl_intlv_ctl")) != NULL
) {
225 if (pdimm
[0].n_ranks
== 0) {
226 printf("There is no rank on CS0. Because only rank on "
227 "CS0 and ranks chip-select interleaved with CS0"
228 " are controller interleaved, force non memory "
229 "controller interleaving\n");
230 popts
->memctl_interleaving
= 0;
232 popts
->memctl_interleaving
= 1;
233 if (strcmp(p
, "cacheline") == 0)
234 popts
->memctl_interleaving_mode
=
235 FSL_DDR_CACHE_LINE_INTERLEAVING
;
236 else if (strcmp(p
, "page") == 0)
237 popts
->memctl_interleaving_mode
=
238 FSL_DDR_PAGE_INTERLEAVING
;
239 else if (strcmp(p
, "bank") == 0)
240 popts
->memctl_interleaving_mode
=
241 FSL_DDR_BANK_INTERLEAVING
;
242 else if (strcmp(p
, "superbank") == 0)
243 popts
->memctl_interleaving_mode
=
244 FSL_DDR_SUPERBANK_INTERLEAVING
;
246 popts
->memctl_interleaving_mode
=
247 simple_strtoul(p
, NULL
, 0);
252 if( ((p
= getenv("ba_intlv_ctl")) != NULL
) &&
253 (CONFIG_CHIP_SELECTS_PER_CTRL
> 1)) {
254 if (strcmp(p
, "cs0_cs1") == 0)
255 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1
;
256 else if (strcmp(p
, "cs2_cs3") == 0)
257 popts
->ba_intlv_ctl
= FSL_DDR_CS2_CS3
;
258 else if (strcmp(p
, "cs0_cs1_and_cs2_cs3") == 0)
259 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_AND_CS2_CS3
;
260 else if (strcmp(p
, "cs0_cs1_cs2_cs3") == 0)
261 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_CS2_CS3
;
263 popts
->ba_intlv_ctl
= simple_strtoul(p
, NULL
, 0);
265 switch (popts
->ba_intlv_ctl
& FSL_DDR_CS0_CS1_CS2_CS3
) {
266 case FSL_DDR_CS0_CS1_CS2_CS3
:
267 case FSL_DDR_CS0_CS1
:
268 if (pdimm
[0].n_ranks
!= 2) {
269 popts
->ba_intlv_ctl
= 0;
270 printf("Not enough bank(chip-select) for "
271 "CS0+CS1, force non-interleaving!\n");
274 case FSL_DDR_CS2_CS3
:
275 if (pdimm
[1].n_ranks
!=2){
276 popts
->ba_intlv_ctl
= 0;
277 printf("Not enough bank(CS) for CS2+CS3, "
278 "force non-interleaving!\n");
281 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
282 if ((pdimm
[0].n_ranks
!= 2)||(pdimm
[1].n_ranks
!= 2)) {
283 popts
->ba_intlv_ctl
= 0;
284 printf("Not enough bank(CS) for CS0+CS1 or "
285 "CS2+CS3, force non-interleaving!\n");
289 popts
->ba_intlv_ctl
= 0;
294 fsl_ddr_board_options(popts
, pdimm
, ctrl_num
);