2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 /* define DEBUG for debugging output (obviously ;-)) */
31 #include <asm/processor.h>
33 #include <asm/errno.h>
35 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
36 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
37 defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
39 #include <asm/4xx_pcie.h>
43 PTYPE_LEGACY_ENDPOINT
= 0x1,
44 PTYPE_ROOT_PORT
= 0x4,
51 static struct pci_controller pcie_hose
[CONFIG_SYS_PCIE_NR_PORTS
];
54 * Per default, all cards are present, so we need to check if the
57 int __board_pcie_card_present(int port
)
61 int board_pcie_card_present(int port
)
62 __attribute__((weak
, alias("__board_pcie_card_present")));
65 * Some boards have runtime detection of the first and last PCIe
66 * slot used, so let's provide weak default functions for the
69 int __board_pcie_first(void)
73 int board_pcie_first(void)
74 __attribute__((weak
, alias("__board_pcie_first")));
76 int __board_pcie_last(void)
78 return CONFIG_SYS_PCIE_NR_PORTS
- 1;
80 int board_pcie_last(void)
81 __attribute__((weak
, alias("__board_pcie_last")));
83 void __board_pcie_setup_port(int port
, int rootpoint
)
85 /* noting in this weak default implementation */
87 void board_pcie_setup_port(int port
, int rootpoint
)
88 __attribute__((weak
, alias("__board_pcie_setup_port")));
90 void pcie_setup_hoses(int busno
)
92 struct pci_controller
*hose
;
97 int first
= board_pcie_first();
98 int last
= board_pcie_last();
101 * Assume we're called after the PCI(X) hose(s) are initialized,
102 * which takes bus ID 0... and therefore start numbering PCIe's
103 * from the next number.
107 for (i
= first
; i
<= last
; i
++) {
109 * Some boards (e.g. Katmai) can detects via hardware
110 * if a PCIe card is plugged, so let's check this.
112 if (!board_pcie_card_present(i
))
115 if (is_end_point(i
)) {
116 board_pcie_setup_port(i
, 0);
117 ret
= ppc4xx_init_pcie_endport(i
);
119 board_pcie_setup_port(i
, 1);
120 ret
= ppc4xx_init_pcie_rootport(i
);
125 printf("PCIE%d: initialization as %s failed\n", i
,
126 is_end_point(i
) ? "endpoint" : "root-complex");
130 hose
= &pcie_hose
[i
];
131 hose
->first_busno
= bus
;
132 hose
->last_busno
= bus
;
133 hose
->current_busno
= bus
;
135 /* setup mem resource */
136 pci_set_region(hose
->regions
+ 0,
137 CONFIG_SYS_PCIE_MEMBASE
+ i
* CONFIG_SYS_PCIE_MEMSIZE
,
138 CONFIG_SYS_PCIE_MEMBASE
+ i
* CONFIG_SYS_PCIE_MEMSIZE
,
139 CONFIG_SYS_PCIE_MEMSIZE
,
141 hose
->region_count
= 1;
142 pci_register_hose(hose
);
144 if (is_end_point(i
)) {
145 ppc4xx_setup_pcie_endpoint(hose
, i
);
147 * Reson for no scanning is endpoint can not generate
148 * upstream configuration accesses.
151 ppc4xx_setup_pcie_rootpoint(hose
, i
);
152 env
= getenv ("pciscandelay");
154 delay
= simple_strtoul(env
, NULL
, 10);
156 printf("Warning, expect noticable delay before "
157 "PCIe scan due to 'pciscandelay' value!\n");
158 mdelay(delay
* 1000);
162 * Config access can only go down stream
164 hose
->last_busno
= pci_hose_scan(hose
);
165 bus
= hose
->last_busno
+ 1;
170 static int validate_endpoint(struct pci_controller
*hose
)
172 if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE0_CFGBASE
)
173 return (is_end_point(0));
174 else if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE1_CFGBASE
)
175 return (is_end_point(1));
176 #if CONFIG_SYS_PCIE_NR_PORTS > 2
177 else if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE2_CFGBASE
)
178 return (is_end_point(2));
184 static u8
* pcie_get_base(struct pci_controller
*hose
, unsigned int devfn
)
186 u8
*base
= (u8
*)hose
->cfg_data
;
188 /* use local configuration space for the first bus */
189 if (PCI_BUS(devfn
) == 0) {
190 if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE0_CFGBASE
)
191 base
= (u8
*)CONFIG_SYS_PCIE0_XCFGBASE
;
192 if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE1_CFGBASE
)
193 base
= (u8
*)CONFIG_SYS_PCIE1_XCFGBASE
;
194 #if CONFIG_SYS_PCIE_NR_PORTS > 2
195 if (hose
->cfg_data
== (u8
*)CONFIG_SYS_PCIE2_CFGBASE
)
196 base
= (u8
*)CONFIG_SYS_PCIE2_XCFGBASE
;
203 static void pcie_dmer_disable(void)
205 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE
),
206 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE
)) | GPL_DMER_MASK_DISA
);
207 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE
),
208 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE
)) | GPL_DMER_MASK_DISA
);
209 #if CONFIG_SYS_PCIE_NR_PORTS > 2
210 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE
),
211 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE
)) | GPL_DMER_MASK_DISA
);
215 static void pcie_dmer_enable(void)
217 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE
),
218 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE
)) & ~GPL_DMER_MASK_DISA
);
219 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE
),
220 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE
)) & ~GPL_DMER_MASK_DISA
);
221 #if CONFIG_SYS_PCIE_NR_PORTS > 2
222 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE
),
223 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE
)) & ~GPL_DMER_MASK_DISA
);
227 static int pcie_read_config(struct pci_controller
*hose
, unsigned int devfn
,
228 int offset
, int len
, u32
*val
) {
233 if (validate_endpoint(hose
))
234 return 0; /* No upstream config access */
237 * Bus numbers are relative to hose->first_busno
239 devfn
-= PCI_BDF(hose
->first_busno
, 0, 0);
242 * NOTICE: configuration space ranges are currenlty mapped only for
243 * the first 16 buses, so such limit must be imposed. In case more
244 * buses are required the TLB settings in board/amcc/<board>/init.S
245 * need to be altered accordingly (one bus takes 1 MB of memory space).
247 if (PCI_BUS(devfn
) >= 16)
251 * Only single device/single function is supported for the primary and
252 * secondary buses of the 440SPe host bridge.
254 if ((!((PCI_FUNC(devfn
) == 0) && (PCI_DEV(devfn
) == 0))) &&
255 ((PCI_BUS(devfn
) == 0) || (PCI_BUS(devfn
) == 1)))
258 address
= pcie_get_base(hose
, devfn
);
259 offset
+= devfn
<< 4;
262 * Reading from configuration space of non-existing device can
263 * generate transaction errors. For the read duration we suppress
264 * assertion of machine check exceptions to avoid those.
266 pcie_dmer_disable ();
268 debug("%s: cfg_data=%08x offset=%08x\n", __func__
, hose
->cfg_data
, offset
);
271 *val
= in_8(hose
->cfg_data
+ offset
);
274 *val
= in_le16((u16
*)(hose
->cfg_data
+ offset
));
277 *val
= in_le32((u32
*)(hose
->cfg_data
+ offset
));
286 static int pcie_write_config(struct pci_controller
*hose
, unsigned int devfn
,
287 int offset
, int len
, u32 val
) {
291 if (validate_endpoint(hose
))
292 return 0; /* No upstream config access */
295 * Bus numbers are relative to hose->first_busno
297 devfn
-= PCI_BDF(hose
->first_busno
, 0, 0);
300 * Same constraints as in pcie_read_config().
302 if (PCI_BUS(devfn
) >= 16)
305 if ((!((PCI_FUNC(devfn
) == 0) && (PCI_DEV(devfn
) == 0))) &&
306 ((PCI_BUS(devfn
) == 0) || (PCI_BUS(devfn
) == 1)))
309 address
= pcie_get_base(hose
, devfn
);
310 offset
+= devfn
<< 4;
313 * Suppress MCK exceptions, similar to pcie_read_config()
315 pcie_dmer_disable ();
319 out_8(hose
->cfg_data
+ offset
, val
);
322 out_le16((u16
*)(hose
->cfg_data
+ offset
), val
);
325 out_le32((u32
*)(hose
->cfg_data
+ offset
), val
);
334 int pcie_read_config_byte(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u8
*val
)
339 rv
= pcie_read_config(hose
, dev
, offset
, 1, &v
);
344 int pcie_read_config_word(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u16
*val
)
349 rv
= pcie_read_config(hose
, dev
, offset
, 2, &v
);
354 int pcie_read_config_dword(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u32
*val
)
359 rv
= pcie_read_config(hose
, dev
, offset
, 3, &v
);
364 int pcie_write_config_byte(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u8 val
)
366 return pcie_write_config(hose
,(u32
)dev
,offset
,1,val
);
369 int pcie_write_config_word(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u16 val
)
371 return pcie_write_config(hose
,(u32
)dev
,offset
,2,(u32
)val
);
374 int pcie_write_config_dword(struct pci_controller
*hose
,pci_dev_t dev
,int offset
,u32 val
)
376 return pcie_write_config(hose
,(u32
)dev
,offset
,3,(u32
)val
);
379 #if defined(CONFIG_440SPE)
380 static void ppc4xx_setup_utl(u32 port
) {
382 volatile void *utl_base
= NULL
;
389 mtdcr(DCRN_PEGPL_REGBAH(PCIE0
), 0x0000000c);
390 mtdcr(DCRN_PEGPL_REGBAL(PCIE0
), 0x20000000);
391 mtdcr(DCRN_PEGPL_REGMSK(PCIE0
), 0x00007001);
392 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0
), 0x68782800);
396 mtdcr(DCRN_PEGPL_REGBAH(PCIE1
), 0x0000000c);
397 mtdcr(DCRN_PEGPL_REGBAL(PCIE1
), 0x20001000);
398 mtdcr(DCRN_PEGPL_REGMSK(PCIE1
), 0x00007001);
399 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1
), 0x68782800);
403 mtdcr(DCRN_PEGPL_REGBAH(PCIE2
), 0x0000000c);
404 mtdcr(DCRN_PEGPL_REGBAL(PCIE2
), 0x20002000);
405 mtdcr(DCRN_PEGPL_REGMSK(PCIE2
), 0x00007001);
406 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2
), 0x68782800);
409 utl_base
= (unsigned int *)(CONFIG_SYS_PCIE_BASE
+ 0x1000 * port
);
412 * Set buffer allocations and then assert VRB and TXE.
414 out_be32(utl_base
+ PEUTL_OUTTR
, 0x08000000);
415 out_be32(utl_base
+ PEUTL_INTR
, 0x02000000);
416 out_be32(utl_base
+ PEUTL_OPDBSZ
, 0x10000000);
417 out_be32(utl_base
+ PEUTL_PBBSZ
, 0x53000000);
418 out_be32(utl_base
+ PEUTL_IPHBSZ
, 0x08000000);
419 out_be32(utl_base
+ PEUTL_IPDBSZ
, 0x10000000);
420 out_be32(utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
421 out_be32(utl_base
+ PEUTL_PCTL
, 0x80800066);
424 static int check_error(void)
426 u32 valPE0
, valPE1
, valPE2
;
429 /* SDR0_PEGPLLLCT1 reset */
430 if (!(valPE0
= SDR_READ(PESDR0_PLLLCT1
) & 0x01000000))
431 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0
);
433 valPE0
= SDR_READ(PESDR0_RCSSET
);
434 valPE1
= SDR_READ(PESDR1_RCSSET
);
435 valPE2
= SDR_READ(PESDR2_RCSSET
);
437 /* SDR0_PExRCSSET rstgu */
438 if (!(valPE0
& 0x01000000) ||
439 !(valPE1
& 0x01000000) ||
440 !(valPE2
& 0x01000000)) {
441 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
445 /* SDR0_PExRCSSET rstdl */
446 if (!(valPE0
& 0x00010000) ||
447 !(valPE1
& 0x00010000) ||
448 !(valPE2
& 0x00010000)) {
449 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
453 /* SDR0_PExRCSSET rstpyn */
454 if ((valPE0
& 0x00001000) ||
455 (valPE1
& 0x00001000) ||
456 (valPE2
& 0x00001000)) {
457 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
461 /* SDR0_PExRCSSET hldplb */
462 if ((valPE0
& 0x10000000) ||
463 (valPE1
& 0x10000000) ||
464 (valPE2
& 0x10000000)) {
465 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
469 /* SDR0_PExRCSSET rdy */
470 if ((valPE0
& 0x00100000) ||
471 (valPE1
& 0x00100000) ||
472 (valPE2
& 0x00100000)) {
473 printf("PCIE: SDR0_PExRCSSET rdy error\n");
477 /* SDR0_PExRCSSET shutdown */
478 if ((valPE0
& 0x00000100) ||
479 (valPE1
& 0x00000100) ||
480 (valPE2
& 0x00000100)) {
481 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
488 * Initialize PCI Express core
490 int ppc4xx_init_pcie(void)
494 /* Set PLL clock receiver to LVPECL */
495 SDR_WRITE(PESDR0_PLLLCT1
, SDR_READ(PESDR0_PLLLCT1
) | 1 << 28);
498 printf("ERROR: failed to set PCIe reference clock receiver --"
499 "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1
));
504 /* Did resistance calibration work? */
505 if (!(SDR_READ(PESDR0_PLLLCT2
) & 0x10000)) {
506 printf("ERROR: PCIe resistance calibration failed --"
507 "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2
));
511 /* De-assert reset of PCIe PLL, wait for lock */
512 SDR_WRITE(PESDR0_PLLLCT1
, SDR_READ(PESDR0_PLLLCT1
) & ~(1 << 24));
513 udelay(300); /* 300 uS is maximum time lock should take */
516 if (!(SDR_READ(PESDR0_PLLLCT3
) & 0x10000000)) {
518 udelay(20); /* Wait 20 uS more if needed */
523 printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
524 "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3
));
532 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
533 static void ppc4xx_setup_utl(u32 port
)
535 volatile void *utl_base
= NULL
;
538 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
542 mtdcr(DCRN_PEGPL_REGBAH(PCIE0
), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE
));
543 mtdcr(DCRN_PEGPL_REGBAL(PCIE0
), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE
));
544 mtdcr(DCRN_PEGPL_REGMSK(PCIE0
), 0x00007001); /* BAM 11100000=4KB */
545 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0
), 0);
549 mtdcr(DCRN_PEGPL_REGBAH(PCIE1
), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE
));
550 mtdcr(DCRN_PEGPL_REGBAL(PCIE1
), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE
)
552 mtdcr(DCRN_PEGPL_REGMSK(PCIE1
), 0x00007001); /* BAM 11100000=4KB */
553 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1
), 0);
556 utl_base
= (unsigned int *)(CONFIG_SYS_PCIE_BASE
+ 0x1000 * port
);
559 * Set buffer allocations and then assert VRB and TXE.
561 out_be32(utl_base
+ PEUTL_PBCTL
, 0x0800000c); /* PLBME, CRRE */
562 out_be32(utl_base
+ PEUTL_OUTTR
, 0x08000000);
563 out_be32(utl_base
+ PEUTL_INTR
, 0x02000000);
564 out_be32(utl_base
+ PEUTL_OPDBSZ
, 0x04000000); /* OPD = 512 Bytes */
565 out_be32(utl_base
+ PEUTL_PBBSZ
, 0x00000000); /* Max 512 Bytes */
566 out_be32(utl_base
+ PEUTL_IPHBSZ
, 0x02000000);
567 out_be32(utl_base
+ PEUTL_IPDBSZ
, 0x04000000); /* IPD = 512 Bytes */
568 out_be32(utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
569 out_be32(utl_base
+ PEUTL_PCTL
, 0x80800066); /* VRB,TXE,timeout=default */
573 * TODO: double check PCI express SDR based on the latest user manual
574 * Some registers specified here no longer exist.. has to be
575 * updated based on the final EAS spec.
577 static int check_error(void)
582 valPE0
= SDR_READ(SDRN_PESDR_RCSSET(0));
583 valPE1
= SDR_READ(SDRN_PESDR_RCSSET(1));
585 /* SDR0_PExRCSSET rstgu */
586 if (!(valPE0
& PESDRx_RCSSET_RSTGU
) || !(valPE1
& PESDRx_RCSSET_RSTGU
)) {
587 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
591 /* SDR0_PExRCSSET rstdl */
592 if (!(valPE0
& PESDRx_RCSSET_RSTDL
) || !(valPE1
& PESDRx_RCSSET_RSTDL
)) {
593 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
597 /* SDR0_PExRCSSET rstpyn */
598 if ((valPE0
& PESDRx_RCSSET_RSTPYN
) || (valPE1
& PESDRx_RCSSET_RSTPYN
)) {
599 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
603 /* SDR0_PExRCSSET hldplb */
604 if ((valPE0
& PESDRx_RCSSET_HLDPLB
) || (valPE1
& PESDRx_RCSSET_HLDPLB
)) {
605 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
609 /* SDR0_PExRCSSET rdy */
610 if ((valPE0
& PESDRx_RCSSET_RDY
) || (valPE1
& PESDRx_RCSSET_RDY
)) {
611 printf("PCIE: SDR0_PExRCSSET rdy error\n");
619 * Initialize PCI Express core as described in User Manual
620 * TODO: double check PE SDR PLL Register with the updated user manual.
622 int ppc4xx_init_pcie(void)
629 #endif /* CONFIG_460EX */
631 #if defined(CONFIG_405EX)
632 static void ppc4xx_setup_utl(u32 port
)
637 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
641 mtdcr(DCRN_PEGPL_REGBAH(PCIE0
), 0x00000000);
642 mtdcr(DCRN_PEGPL_REGBAL(PCIE0
), CONFIG_SYS_PCIE0_UTLBASE
);
643 mtdcr(DCRN_PEGPL_REGMSK(PCIE0
), 0x00007001); /* 4k region, valid */
644 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0
), 0);
648 mtdcr(DCRN_PEGPL_REGBAH(PCIE1
), 0x00000000);
649 mtdcr(DCRN_PEGPL_REGBAL(PCIE1
), CONFIG_SYS_PCIE1_UTLBASE
);
650 mtdcr(DCRN_PEGPL_REGMSK(PCIE1
), 0x00007001); /* 4k region, valid */
651 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1
), 0);
655 utl_base
= (port
==0) ? CONFIG_SYS_PCIE0_UTLBASE
: CONFIG_SYS_PCIE1_UTLBASE
;
658 * Set buffer allocations and then assert VRB and TXE.
660 out_be32((u32
*)(utl_base
+ PEUTL_OUTTR
), 0x02000000);
661 out_be32((u32
*)(utl_base
+ PEUTL_INTR
), 0x02000000);
662 out_be32((u32
*)(utl_base
+ PEUTL_OPDBSZ
), 0x04000000);
663 out_be32((u32
*)(utl_base
+ PEUTL_PBBSZ
), 0x21000000);
664 out_be32((u32
*)(utl_base
+ PEUTL_IPHBSZ
), 0x02000000);
665 out_be32((u32
*)(utl_base
+ PEUTL_IPDBSZ
), 0x04000000);
666 out_be32((u32
*)(utl_base
+ PEUTL_RCIRQEN
), 0x00f00000);
667 out_be32((u32
*)(utl_base
+ PEUTL_PCTL
), 0x80800066);
669 out_be32((u32
*)(utl_base
+ PEUTL_PBCTL
), 0x0800000c);
670 out_be32((u32
*)(utl_base
+ PEUTL_RCSTA
),
671 in_be32((u32
*)(utl_base
+ PEUTL_RCSTA
)) | 0x000040000);
674 int ppc4xx_init_pcie(void)
677 * Nothing to do on 405EX
681 #endif /* CONFIG_405EX */
684 * Board-specific pcie initialization
685 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
689 * Initialize various parts of the PCI Express core for our port:
691 * - Set as a root port and enable max width
692 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
693 * - Set up UTL configuration.
694 * - Increase SERDES drive strength to levels suggested by AMCC.
695 * - De-assert RSTPYN, RSTDL and RSTGU.
697 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
698 * with default setting 0x11310000. The register has new fields,
699 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
702 #if defined(CONFIG_440SPE)
703 int __ppc4xx_init_pcie_port_hw(int port
, int rootport
)
709 val
= PTYPE_ROOT_PORT
<< 20;
710 utlset1
= 0x21222222;
712 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
713 utlset1
= 0x20222222;
717 val
|= LNKW_X8
<< 12;
719 val
|= LNKW_X4
<< 12;
721 SDR_WRITE(SDRN_PESDR_DLPSET(port
), val
);
722 SDR_WRITE(SDRN_PESDR_UTLSET1(port
), utlset1
);
723 if (!ppc440spe_revB())
724 SDR_WRITE(SDRN_PESDR_UTLSET2(port
), 0x11000000);
725 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port
), 0x35000000);
726 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port
), 0x35000000);
727 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port
), 0x35000000);
728 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port
), 0x35000000);
730 SDR_WRITE(PESDR0_HSSL4SET1
, 0x35000000);
731 SDR_WRITE(PESDR0_HSSL5SET1
, 0x35000000);
732 SDR_WRITE(PESDR0_HSSL6SET1
, 0x35000000);
733 SDR_WRITE(PESDR0_HSSL7SET1
, 0x35000000);
735 SDR_WRITE(SDRN_PESDR_RCSSET(port
), (SDR_READ(SDRN_PESDR_RCSSET(port
)) &
736 ~(1 << 24 | 1 << 16)) | 1 << 12);
740 #endif /* CONFIG_440SPE */
742 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
743 int __ppc4xx_init_pcie_port_hw(int port
, int rootport
)
749 val
= PTYPE_ROOT_PORT
<< 20;
751 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
754 val
|= LNKW_X1
<< 12;
755 utlset1
= 0x20000000;
757 val
|= LNKW_X4
<< 12;
758 utlset1
= 0x20101101;
761 SDR_WRITE(SDRN_PESDR_DLPSET(port
), val
);
762 SDR_WRITE(SDRN_PESDR_UTLSET1(port
), utlset1
);
763 SDR_WRITE(SDRN_PESDR_UTLSET2(port
), 0x01210000);
767 SDR_WRITE(PESDR0_L0CDRCTL
, 0x00003230);
768 SDR_WRITE(PESDR0_L0DRV
, 0x00000130);
769 SDR_WRITE(PESDR0_L0CLK
, 0x00000006);
771 SDR_WRITE(PESDR0_PHY_CTL_RST
,0x10000000);
775 SDR_WRITE(PESDR1_L0CDRCTL
, 0x00003230);
776 SDR_WRITE(PESDR1_L1CDRCTL
, 0x00003230);
777 SDR_WRITE(PESDR1_L2CDRCTL
, 0x00003230);
778 SDR_WRITE(PESDR1_L3CDRCTL
, 0x00003230);
779 SDR_WRITE(PESDR1_L0DRV
, 0x00000130);
780 SDR_WRITE(PESDR1_L1DRV
, 0x00000130);
781 SDR_WRITE(PESDR1_L2DRV
, 0x00000130);
782 SDR_WRITE(PESDR1_L3DRV
, 0x00000130);
783 SDR_WRITE(PESDR1_L0CLK
, 0x00000006);
784 SDR_WRITE(PESDR1_L1CLK
, 0x00000006);
785 SDR_WRITE(PESDR1_L2CLK
, 0x00000006);
786 SDR_WRITE(PESDR1_L3CLK
, 0x00000006);
788 SDR_WRITE(PESDR1_PHY_CTL_RST
,0x10000000);
792 SDR_WRITE(SDRN_PESDR_RCSSET(port
), SDR_READ(SDRN_PESDR_RCSSET(port
)) |
793 (PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTPYN
));
795 /* Poll for PHY reset */
798 while (!(SDR_READ(PESDR0_RSTSTA
) & 0x1))
802 while (!(SDR_READ(PESDR1_RSTSTA
) & 0x1))
807 SDR_WRITE(SDRN_PESDR_RCSSET(port
),
808 (SDR_READ(SDRN_PESDR_RCSSET(port
)) &
809 ~(PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTDL
)) |
810 PESDRx_RCSSET_RSTPYN
);
814 #endif /* CONFIG_440SPE */
816 #if defined(CONFIG_405EX)
817 int __ppc4xx_init_pcie_port_hw(int port
, int rootport
)
826 SDR_WRITE(SDRN_PESDR_DLPSET(port
), val
);
827 SDR_WRITE(SDRN_PESDR_UTLSET1(port
), 0x00000000);
828 SDR_WRITE(SDRN_PESDR_UTLSET2(port
), 0x01010000);
829 SDR_WRITE(SDRN_PESDR_PHYSET1(port
), 0x720F0000);
830 SDR_WRITE(SDRN_PESDR_PHYSET2(port
), 0x70600003);
832 /* Assert the PE0_PHY reset */
833 SDR_WRITE(SDRN_PESDR_RCSSET(port
), 0x01010000);
836 /* deassert the PE0_hotreset */
837 if (is_end_point(port
))
838 SDR_WRITE(SDRN_PESDR_RCSSET(port
), 0x01111000);
840 SDR_WRITE(SDRN_PESDR_RCSSET(port
), 0x01101000);
842 /* poll for phy !reset */
843 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port
)) & 0x00001000))
846 /* deassert the PE0_gpl_utl_reset */
847 SDR_WRITE(SDRN_PESDR_RCSSET(port
), 0x00101000);
850 mtdcr(DCRN_PEGPL_CFG(PCIE0
), 0x10000000); /* guarded on */
852 mtdcr(DCRN_PEGPL_CFG(PCIE1
), 0x10000000); /* guarded on */
856 #endif /* CONFIG_405EX */
858 int ppc4xx_init_pcie_port_hw(int port
, int rootport
)
859 __attribute__((weak
, alias("__ppc4xx_init_pcie_port_hw")));
862 * We map PCI Express configuration access into the 512MB regions
864 * NOTICE: revB is very strict about PLB real addressess and ranges to
865 * be mapped for config space; it seems to only work with d_nnnn_nnnn
866 * range (hangs the core upon config transaction attempts when set
867 * otherwise) while revA uses c_nnnn_nnnn.
870 * PCIE0: 0xc_4000_0000
871 * PCIE1: 0xc_8000_0000
872 * PCIE2: 0xc_c000_0000
875 * PCIE0: 0xd_0000_0000
876 * PCIE1: 0xd_2000_0000
877 * PCIE2: 0xd_4000_0000
884 * PCIE0: 0xd_0000_0000
885 * PCIE1: 0xd_2000_0000
887 static inline u64
ppc4xx_get_cfgaddr(int port
)
889 #if defined(CONFIG_405EX)
891 return (u64
)CONFIG_SYS_PCIE0_CFGBASE
;
893 return (u64
)CONFIG_SYS_PCIE1_CFGBASE
;
895 #if defined(CONFIG_440SPE)
896 if (ppc440spe_revB()) {
898 default: /* to satisfy compiler */
900 return 0x0000000d00000000ULL
;
902 return 0x0000000d20000000ULL
;
904 return 0x0000000d40000000ULL
;
908 default: /* to satisfy compiler */
910 return 0x0000000c40000000ULL
;
912 return 0x0000000c80000000ULL
;
914 return 0x0000000cc0000000ULL
;
918 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
920 return 0x0000000d00000000ULL
;
922 return 0x0000000d20000000ULL
;
927 * 4xx boards as endpoint and root point setup
929 * testing inbound and out bound windows
931 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
932 * cable which can be used to setup loop back from one port to another port.
933 * Please rememeber that unless there is a endpoint plugged in to root port it
934 * will not initialize. It is the same in case of endpoint , unless there is
935 * root port attached it will not initialize.
937 * In this release of software all the PCI-E ports are configured as either
938 * endpoint or rootpoint.In future we will have support for selective ports
939 * setup as endpoint and root point in single board.
941 * Once your board came up as root point , you can verify by reading
942 * /proc/bus/pci/devices. Where you can see the configuration registers
943 * of endpoint device attached to the port.
945 * Enpoint cofiguration can be verified by connecting 4xx board to any
946 * host or another 4xx board. Then try to scan the device. In case of
947 * linux use "lspci" or appripriate os command.
949 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
950 * in this configuration inbound and outbound windows are setup to access
951 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
952 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
953 * This is waere your POM(PLB out bound memory window) mapped. then
954 * read the data from other 4xx board's u-boot prompt at address
955 * 0x9000 0000(SRAM). Data should match.
956 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
957 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
958 * data at 0x9000 0000(SRAM).Data should match.
960 int ppc4xx_init_pcie_port(int port
, int rootport
)
962 static int core_init
;
963 volatile u32 val
= 0;
969 if (ppc4xx_init_pcie())
975 * Initialize various parts of the PCI Express core for our port
977 ppc4xx_init_pcie_port_hw(port
, rootport
);
980 * Notice: the following delay has critical impact on device
981 * initialization - if too short (<50ms) the link doesn't get up.
985 val
= SDR_READ(SDRN_PESDR_RCSSTS(port
));
986 if (val
& (1 << 20)) {
987 printf("PCIE%d: PGRST failed %08x\n", port
, val
);
994 val
= SDR_READ(SDRN_PESDR_LOOP(port
));
995 if (!(val
& 0x00001000)) {
996 printf("PCIE%d: link is not up.\n", port
);
1001 * Setup UTL registers - but only on revA!
1002 * We use default settings for revB chip.
1004 if (!ppc440spe_revB())
1005 ppc4xx_setup_utl(port
);
1008 * We map PCI Express configuration access into the 512MB regions
1010 addr
= ppc4xx_get_cfgaddr(port
);
1011 low
= U64_TO_U32_LOW(addr
);
1012 high
= U64_TO_U32_HIGH(addr
);
1016 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0
), high
);
1017 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0
), low
);
1018 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0
), 0xe0000001); /* 512MB region, valid */
1021 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1
), high
);
1022 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1
), low
);
1023 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1
), 0xe0000001); /* 512MB region, valid */
1025 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1027 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2
), high
);
1028 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2
), low
);
1029 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2
), 0xe0000001); /* 512MB region, valid */
1035 * Check for VC0 active and assert RDY.
1038 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port
)) & (1 << 16))) {
1039 if (!(attempts
--)) {
1040 printf("PCIE%d: VC0 not active\n", port
);
1045 SDR_WRITE(SDRN_PESDR_RCSSET(port
),
1046 SDR_READ(SDRN_PESDR_RCSSET(port
)) | 1 << 20);
1052 int ppc4xx_init_pcie_rootport(int port
)
1054 return ppc4xx_init_pcie_port(port
, 1);
1057 int ppc4xx_init_pcie_endport(int port
)
1059 return ppc4xx_init_pcie_port(port
, 0);
1062 void ppc4xx_setup_pcie_rootpoint(struct pci_controller
*hose
, int port
)
1064 volatile void *mbase
= NULL
;
1065 volatile void *rmbase
= NULL
;
1068 pcie_read_config_byte
,
1069 pcie_read_config_word
,
1070 pcie_read_config_dword
,
1071 pcie_write_config_byte
,
1072 pcie_write_config_word
,
1073 pcie_write_config_dword
);
1077 mbase
= (u32
*)CONFIG_SYS_PCIE0_XCFGBASE
;
1078 rmbase
= (u32
*)CONFIG_SYS_PCIE0_CFGBASE
;
1079 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE0_CFGBASE
;
1082 mbase
= (u32
*)CONFIG_SYS_PCIE1_XCFGBASE
;
1083 rmbase
= (u32
*)CONFIG_SYS_PCIE1_CFGBASE
;
1084 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE1_CFGBASE
;
1086 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1088 mbase
= (u32
*)CONFIG_SYS_PCIE2_XCFGBASE
;
1089 rmbase
= (u32
*)CONFIG_SYS_PCIE2_CFGBASE
;
1090 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE2_CFGBASE
;
1096 * Set bus numbers on our root port
1098 out_8((u8
*)mbase
+ PCI_PRIMARY_BUS
, 0);
1099 out_8((u8
*)mbase
+ PCI_SECONDARY_BUS
, 1);
1100 out_8((u8
*)mbase
+ PCI_SUBORDINATE_BUS
, 1);
1103 * Set up outbound translation to hose->mem_space from PLB
1104 * addresses at an offset of 0xd_0000_0000. We set the low
1105 * bits of the mask to 11 to turn off splitting into 8
1106 * subregions and to enable the outbound translation.
1108 out_le32(mbase
+ PECFG_POM0LAH
, 0x00000000);
1109 out_le32(mbase
+ PECFG_POM0LAL
, CONFIG_SYS_PCIE_MEMBASE
+
1110 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1111 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase
+ PECFG_POM0LAH
),
1112 in_le32(mbase
+ PECFG_POM0LAL
));
1116 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1117 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0
), CONFIG_SYS_PCIE_MEMBASE
+
1118 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1119 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0
), 0x7fffffff);
1120 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0
),
1121 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1122 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1123 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0
)),
1124 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0
)),
1125 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0
)),
1126 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0
)));
1129 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1130 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1
), CONFIG_SYS_PCIE_MEMBASE
+
1131 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1132 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1
), 0x7fffffff);
1133 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1
),
1134 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1135 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1136 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1
)),
1137 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1
)),
1138 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1
)),
1139 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1
)));
1141 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1143 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1144 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2
), CONFIG_SYS_PCIE_MEMBASE
+
1145 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1146 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2
), 0x7fffffff);
1147 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2
),
1148 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1149 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1150 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2
)),
1151 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2
)),
1152 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2
)),
1153 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2
)));
1158 /* Set up 4GB inbound memory window at 0 */
1159 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, 0);
1160 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, 0);
1161 out_le32(mbase
+ PECFG_BAR0HMPA
, 0x7ffffff);
1162 out_le32(mbase
+ PECFG_BAR0LMPA
, 0);
1164 out_le32(mbase
+ PECFG_PIM01SAH
, 0xffff0000);
1165 out_le32(mbase
+ PECFG_PIM01SAL
, 0x00000000);
1166 out_le32(mbase
+ PECFG_PIM0LAL
, 0);
1167 out_le32(mbase
+ PECFG_PIM0LAH
, 0);
1168 out_le32(mbase
+ PECFG_PIM1LAL
, 0x00000000);
1169 out_le32(mbase
+ PECFG_PIM1LAH
, 0x00000004);
1170 out_le32(mbase
+ PECFG_PIMEN
, 0x1);
1172 /* Enable I/O, Mem, and Busmaster cycles */
1173 out_le16((u16
*)(mbase
+ PCI_COMMAND
),
1174 in_le16((u16
*)(mbase
+ PCI_COMMAND
)) |
1175 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
1177 /* Set Device and Vendor Id */
1178 out_le16(mbase
+ 0x200, 0xaaa0 + port
);
1179 out_le16(mbase
+ 0x202, 0xbed0 + port
);
1181 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1182 out_le32(mbase
+ 0x208, 0x06040001);
1184 printf("PCIE%d: successfully set as root-complex\n", port
);
1187 int ppc4xx_setup_pcie_endpoint(struct pci_controller
*hose
, int port
)
1189 volatile void *mbase
= NULL
;
1193 pcie_read_config_byte
,
1194 pcie_read_config_word
,
1195 pcie_read_config_dword
,
1196 pcie_write_config_byte
,
1197 pcie_write_config_word
,
1198 pcie_write_config_dword
);
1202 mbase
= (u32
*)CONFIG_SYS_PCIE0_XCFGBASE
;
1203 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE0_CFGBASE
;
1206 mbase
= (u32
*)CONFIG_SYS_PCIE1_XCFGBASE
;
1207 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE1_CFGBASE
;
1209 #if defined(CONFIG_SYS_PCIE2_CFGBASE)
1211 mbase
= (u32
*)CONFIG_SYS_PCIE2_XCFGBASE
;
1212 hose
->cfg_data
= (u8
*)CONFIG_SYS_PCIE2_CFGBASE
;
1218 * Set up outbound translation to hose->mem_space from PLB
1219 * addresses at an offset of 0xd_0000_0000. We set the low
1220 * bits of the mask to 11 to turn off splitting into 8
1221 * subregions and to enable the outbound translation.
1223 out_le32(mbase
+ PECFG_POM0LAH
, 0x00001ff8);
1224 out_le32(mbase
+ PECFG_POM0LAL
, 0x00001000);
1228 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1229 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0
), CONFIG_SYS_PCIE_MEMBASE
+
1230 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1231 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0
), 0x7fffffff);
1232 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0
),
1233 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1236 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1237 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1
), CONFIG_SYS_PCIE_MEMBASE
+
1238 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1239 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1
), 0x7fffffff);
1240 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1
),
1241 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1243 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1245 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2
), CONFIG_SYS_PCIE_ADDR_HIGH
);
1246 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2
), CONFIG_SYS_PCIE_MEMBASE
+
1247 port
* CONFIG_SYS_PCIE_MEMSIZE
);
1248 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2
), 0x7fffffff);
1249 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2
),
1250 ~(CONFIG_SYS_PCIE_MEMSIZE
- 1) | 3);
1255 /* Set up 64MB inbound memory window at 0 */
1256 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, 0);
1257 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, 0);
1259 out_le32(mbase
+ PECFG_PIM01SAH
, 0xffffffff);
1260 out_le32(mbase
+ PECFG_PIM01SAL
, 0xfc000000);
1263 out_le32(mbase
+ PECFG_BAR0HMPA
, 0x7fffffff);
1264 out_le32(mbase
+ PECFG_BAR0LMPA
, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64
);
1266 /* Disable BAR1 & BAR2 */
1267 out_le32(mbase
+ PECFG_BAR1MPA
, 0);
1268 out_le32(mbase
+ PECFG_BAR2HMPA
, 0);
1269 out_le32(mbase
+ PECFG_BAR2LMPA
, 0);
1271 out_le32(mbase
+ PECFG_PIM0LAL
, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE
));
1272 out_le32(mbase
+ PECFG_PIM0LAH
, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE
));
1273 out_le32(mbase
+ PECFG_PIMEN
, 0x1);
1275 /* Enable I/O, Mem, and Busmaster cycles */
1276 out_le16((u16
*)(mbase
+ PCI_COMMAND
),
1277 in_le16((u16
*)(mbase
+ PCI_COMMAND
)) |
1278 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
1279 out_le16(mbase
+ 0x200, 0xcaad); /* Setting vendor ID */
1280 out_le16(mbase
+ 0x202, 0xfeed); /* Setting device ID */
1282 /* Set Class Code to Processor/PPC */
1283 out_le32(mbase
+ 0x208, 0x0b200001);
1286 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port
)) & (1 << 8))) {
1287 if (!(attempts
--)) {
1288 printf("PCIE%d: BME not active\n", port
);
1294 printf("PCIE%d: successfully set as endpoint\n", port
);
1298 #endif /* CONFIG_440SPE && CONFIG_PCI */