]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/ppc/cpu/ppc4xx/reginfo.c
2 *(C) Copyright 2005-2009 Netstal Maschinen AG
3 * Bruno Hars (Bruno.Hars@netstal.com)
4 * Niklaus Giger (Niklaus.Giger@netstal.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
23 * reginfo.c - register dump of HW-configuratin register for PPC4xx based board
28 #include <asm/processor.h>
30 #include <asm/ppc4xx-uic.h>
31 #include <ppc4xx_enet.h>
34 IDCR1
, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
35 IDCR2
, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
36 IDCR3
, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
37 IDCR4
, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
38 IDCR5
, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
39 IDCR6
, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
40 MM
/* Directly Accessed MMIO Register */
45 enum REGISTER_TYPE type
;
50 * PPC440EPx registers ordered for output
52 * -------------------------------------------
55 const struct cpu_register ppc4xx_reg
[] = {
56 {"PB0CR", IDCR2
, PB0CR
},
57 {"PB0AP", IDCR2
, PB0AP
},
58 {"PB1CR", IDCR2
, PB1CR
},
59 {"PB1AP", IDCR2
, PB1AP
},
60 {"PB2CR", IDCR2
, PB2CR
},
61 {"PB2AP", IDCR2
, PB2AP
},
62 {"PB3CR", IDCR2
, PB3CR
},
63 {"PB3AP", IDCR2
, PB3AP
},
65 {"PB4CR", IDCR2
, PB4CR
},
66 {"PB4AP", IDCR2
, PB4AP
},
67 #if !defined(CONFIG_405EP)
68 {"PB5CR", IDCR2
, PB5CR
},
69 {"PB5AP", IDCR2
, PB5AP
},
70 {"PB6CR", IDCR2
, PB6CR
},
71 {"PB6AP", IDCR2
, PB6AP
},
72 {"PB7CR", IDCR2
, PB7CR
},
73 {"PB7AP", IDCR2
, PB7AP
},
76 {"PBEAR", IDCR2
, PBEAR
},
77 #if defined(CONFIG_405EP) || defined (CONFIG_405GP)
78 {"PBESR0", IDCR2
, PBESR0
},
79 {"PBESR1", IDCR2
, PBESR1
},
81 {"EBC0_CFG", IDCR2
, EBC0_CFG
},
84 {"SDRAM0_BESR0", IDCR1
, SDRAM0_BESR0
},
85 {"SDRAM0_BESRS0", IDCR1
, SDRAM0_BESRS0
},
86 {"SDRAM0_BESR1", IDCR1
, SDRAM0_BESR1
},
87 {"SDRAM0_BESRS1", IDCR1
, SDRAM0_BESRS1
},
88 {"SDRAM0_BEAR", IDCR1
, SDRAM0_BEAR
},
89 {"SDRAM0_CFG", IDCR1
, SDRAM0_CFG
},
90 {"SDRAM0_RTR", IDCR1
, SDRAM0_RTR
},
91 {"SDRAM0_PMIT", IDCR1
, SDRAM0_PMIT
},
93 {"SDRAM0_B0CR", IDCR1
, SDRAM0_B0CR
},
94 {"SDRAM0_B1CR", IDCR1
, SDRAM0_B1CR
},
95 {"SDRAM0_B2CR", IDCR1
, SDRAM0_B2CR
},
96 {"SDRAM0_B3CR", IDCR1
, SDRAM0_B1CR
},
97 {"SDRAM0_TR", IDCR1
, SDRAM0_TR
},
98 {"SDRAM0_ECCCFG", IDCR1
, SDRAM0_B1CR
},
99 {"SDRAM0_ECCESR", IDCR1
, SDRAM0_ECCESR
},
105 {"SDR0_SDSTP0", IDCR6
, SDR0_SDSTP0
},
106 {"SDR0_SDSTP1", IDCR6
, SDR0_SDSTP1
},
107 {"SDR0_SDSTP2", IDCR6
, SDR0_SDSTP2
},
108 {"SDR0_SDSTP3", IDCR6
, SDR0_SDSTP3
},
109 {"SDR0_CUST0", IDCR6
, SDR0_CUST0
},
110 {"SDR0_CUST1", IDCR6
, SDR0_CUST1
},
111 {"SDR0_EBC0", IDCR6
, SDR0_EBC0
},
112 {"SDR0_AMP0", IDCR6
, SD0_AMP0
},
113 {"SDR0_AMP1", IDCR6
, SD0_AMP1
},
114 {"SDR0_CP440", IDCR6
, SDR0_CP440
},
115 {"SDR0_CRYP0", IDCR6
, SDR0_CRYP0
},
116 {"SDR0_DDRCFG", IDCR6
, SDR0_DDRCFG
},
117 {"SDR0_EMAC0RXST", IDCR6
, SDR0_EMAC0RXST
},
118 {"SDR0_EMAC0TXST", IDCR6
, SDR0_EMAC0TXST
},
119 {"SDR0_MFR", IDCR6
, SDR0_MFR
},
120 {"SDR0_PCI0", IDCR6
, SDR0_PCI0
},
121 {"SDR0_PFC0", IDCR6
, SDR0_PFC0
},
122 {"SDR0_PFC1", IDCR6
, SDR0_PFC1
},
123 {"SDR0_PFC2", IDCR6
, SDR0_PFC2
},
124 {"SDR0_PFC4", IDCR6
, SDR0_PFC4
},
125 {"SDR0_UART0", IDCR6
, SDR0_UART0
},
126 {"SDR0_UART1", IDCR6
, SDR0_UART1
},
127 {"SDR0_UART2", IDCR6
, SDR0_UART2
},
128 {"SDR0_UART3", IDCR6
, SDR0_UART3
},
129 {"DDR0_02", IDCR1
, DDR0_02
},
130 {"DDR0_00", IDCR1
, DDR0_00
},
131 {"DDR0_01", IDCR1
, DDR0_01
},
132 {"DDR0_03", IDCR1
, DDR0_03
},
133 {"DDR0_04", IDCR1
, DDR0_04
},
134 {"DDR0_05", IDCR1
, DDR0_05
},
135 {"DDR0_06", IDCR1
, DDR0_06
},
136 {"DDR0_07", IDCR1
, DDR0_07
},
137 {"DDR0_08", IDCR1
, DDR0_08
},
138 {"DDR0_09", IDCR1
, DDR0_09
},
139 {"DDR0_10", IDCR1
, DDR0_10
},
140 {"DDR0_11", IDCR1
, DDR0_11
},
141 {"DDR0_12", IDCR1
, DDR0_12
},
142 {"DDR0_14", IDCR1
, DDR0_14
},
143 {"DDR0_17", IDCR1
, DDR0_17
},
144 {"DDR0_18", IDCR1
, DDR0_18
},
145 {"DDR0_19", IDCR1
, DDR0_19
},
146 {"DDR0_20", IDCR1
, DDR0_20
},
147 {"DDR0_21", IDCR1
, DDR0_21
},
148 {"DDR0_22", IDCR1
, DDR0_22
},
149 {"DDR0_23", IDCR1
, DDR0_23
},
150 {"DDR0_24", IDCR1
, DDR0_24
},
151 {"DDR0_25", IDCR1
, DDR0_25
},
152 {"DDR0_26", IDCR1
, DDR0_26
},
153 {"DDR0_27", IDCR1
, DDR0_27
},
154 {"DDR0_28", IDCR1
, DDR0_28
},
155 {"DDR0_31", IDCR1
, DDR0_31
},
156 {"DDR0_32", IDCR1
, DDR0_32
},
157 {"DDR0_33", IDCR1
, DDR0_33
},
158 {"DDR0_34", IDCR1
, DDR0_34
},
159 {"DDR0_35", IDCR1
, DDR0_35
},
160 {"DDR0_36", IDCR1
, DDR0_36
},
161 {"DDR0_37", IDCR1
, DDR0_37
},
162 {"DDR0_38", IDCR1
, DDR0_38
},
163 {"DDR0_39", IDCR1
, DDR0_39
},
164 {"DDR0_40", IDCR1
, DDR0_40
},
165 {"DDR0_41", IDCR1
, DDR0_41
},
166 {"DDR0_42", IDCR1
, DDR0_42
},
167 {"DDR0_43", IDCR1
, DDR0_43
},
168 {"DDR0_44", IDCR1
, DDR0_44
},
169 {"CPR0_ICFG", IDCR5
, CPR0_ICFG
},
170 {"CPR0_MALD", IDCR5
, CPR0_MALD
},
171 {"CPR0_OPBD00", IDCR5
, CPR0_OPBD0
},
172 {"CPR0_PERD0", IDCR5
, CPR0_PERD
},
173 {"CPR0_PLLC0", IDCR5
, CPR0_PLLC
},
174 {"CPR0_PLLD0", IDCR5
, CPR0_PLLD
},
175 {"CPR0_PRIMAD0", IDCR5
, CPR0_PRIMAD0
},
176 {"CPR0_PRIMBD0", IDCR5
, CPR0_PRIMBD0
},
177 {"CPR0_SPCID", IDCR5
, CPR0_SPCID
},
178 {"SPI0_MODE", MM
, SPI0_MODE
},
179 {"IIC0_CLKDIV", MM
, PCIL0_PMM1MA
},
180 {"PCIL0_PMM0MA", MM
, PCIL0_PMM0MA
},
181 {"PCIL0_PMM1MA", MM
, PCIL0_PMM1MA
},
182 {"PCIL0_PTM1LA", MM
, PCIL0_PMM1MA
},
183 {"PCIL0_PTM1MS", MM
, PCIL0_PTM1MS
},
184 {"PCIL0_PTM2LA", MM
, PCIL0_PMM1MA
},
185 {"PCIL0_PTM2MS", MM
, PCIL0_PTM2MS
},
186 {"ZMII0_FER", MM
, ZMII0_FER
},
187 {"ZMII0_SSR", MM
, ZMII0_SSR
},
188 {"EMAC0_IPGVR", MM
, EMAC0_IPGVR
},
189 {"EMAC0_MR1", MM
, EMAC0_MR1
},
190 {"EMAC0_PTR", MM
, EMAC0_PTR
},
191 {"EMAC0_RWMR", MM
, EMAC0_RWMR
},
192 {"EMAC0_STACR", MM
, EMAC0_STACR
},
193 {"EMAC0_TMR0", MM
, EMAC0_TMR0
},
194 {"EMAC0_TMR1", MM
, EMAC0_TMR1
},
195 {"EMAC0_TRTR", MM
, EMAC0_TRTR
},
196 {"EMAC1_MR1", MM
, EMAC1_MR1
},
197 {"GPIO0_OR", MM
, GPIO0_OR
},
198 {"GPIO1_OR", MM
, GPIO1_OR
},
199 {"GPIO0_TCR", MM
, GPIO0_TCR
},
200 {"GPIO1_TCR", MM
, GPIO1_TCR
},
201 {"GPIO0_ODR", MM
, GPIO0_ODR
},
202 {"GPIO1_ODR", MM
, GPIO1_ODR
},
203 {"GPIO0_OSRL", MM
, GPIO0_OSRL
},
204 {"GPIO0_OSRH", MM
, GPIO0_OSRH
},
205 {"GPIO1_OSRL", MM
, GPIO1_OSRL
},
206 {"GPIO1_OSRH", MM
, GPIO1_OSRH
},
207 {"GPIO0_TSRL", MM
, GPIO0_TSRL
},
208 {"GPIO0_TSRH", MM
, GPIO0_TSRH
},
209 {"GPIO1_TSRL", MM
, GPIO1_TSRL
},
210 {"GPIO1_TSRH", MM
, GPIO1_TSRH
},
211 {"GPIO0_IR", MM
, GPIO0_IR
},
212 {"GPIO1_IR", MM
, GPIO1_IR
},
213 {"GPIO0_ISR1L", MM
, GPIO0_ISR1L
},
214 {"GPIO0_ISR1H", MM
, GPIO0_ISR1H
},
215 {"GPIO1_ISR1L", MM
, GPIO1_ISR1L
},
216 {"GPIO1_ISR1H", MM
, GPIO1_ISR1H
},
217 {"GPIO0_ISR2L", MM
, GPIO0_ISR2L
},
218 {"GPIO0_ISR2H", MM
, GPIO0_ISR2H
},
219 {"GPIO1_ISR2L", MM
, GPIO1_ISR2L
},
220 {"GPIO1_ISR2H", MM
, GPIO1_ISR2H
},
221 {"GPIO0_ISR3L", MM
, GPIO0_ISR3L
},
222 {"GPIO0_ISR3H", MM
, GPIO0_ISR3H
},
223 {"GPIO1_ISR3L", MM
, GPIO1_ISR3L
},
224 {"GPIO1_ISR3H", MM
, GPIO1_ISR3H
},
225 {"SDR0_USB2PHY0CR", IDCR6
, SDR0_USB2PHY0CR
},
226 {"SDR0_USB2H0CR", IDCR6
, SDR0_USB2H0CR
},
227 {"SDR0_USB2D0CR", IDCR6
, SDR0_USB2D0CR
},
232 * CPU Register dump of PPC4xx HW configuration registers
233 * Output: first all DCR-registers, then in order of struct ppc4xx_reg
235 #define PRINT_DCR(dcr) printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr));
237 void ppc4xx_reginfo(void)
242 enum REGISTER_TYPE type
;
243 #if defined (CONFIG_405EP)
244 printf("Dump PPC405EP HW configuration registers\n\n");
246 printf ("Dump 405GP HW configuration registers\n\n");
248 printf("Dump PPC440EPx HW configuration registers\n\n");
250 printf("MSR: 0x%08x\n", mfmsr());
252 printf ("\nUniversal Interrupt Controller Regs\n");
295 #if defined (CONFIG_405EP) || defined (CONFIG_405GP)
296 printf ("\n\nDMA Channels\n");
326 printf ("\n\nVarious HW-Configuration registers\n");
327 #if defined (CONFIG_440EPX)
331 PRINT_DCR(PLB4A0_ACR
);
332 PRINT_DCR(PLB4A1_ACR
);
333 PRINT_DCR(PLB3A0_ACR
);
334 PRINT_DCR(OPB2PLB40_BCTRL
);
335 PRINT_DCR(P4P3BO0_CFG
);
337 n
= sizeof(ppc4xx_reg
) / sizeof(ppc4xx_reg
[0]);
338 for (i
= 0; i
< n
; i
++) {
340 type
= ppc4xx_reg
[i
].type
;
342 case IDCR1
: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
343 mtdcr(SDRAM0_CFGADDR
, ppc4xx_reg
[i
].address
);
344 value
= mfdcr(SDRAM0_CFGDATA
);
346 case IDCR2
: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
347 mtdcr(EBC0_CFGADDR
, ppc4xx_reg
[i
].address
);
348 value
= mfdcr(EBC0_CFGDATA
);
350 case IDCR5
: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
351 mtdcr(CPR0_CFGADDR
, ppc4xx_reg
[i
].address
);
352 value
= mfdcr(CPR0_CFGDATA
);
354 case IDCR6
: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
355 mtdcr(SDR0_CFGADDR
, ppc4xx_reg
[i
].address
);
356 value
= mfdcr(SDR0_CFGDATA
);
358 case MM
: /* Directly Accessed MMIO Register */
359 value
= in_be32((const volatile unsigned __iomem
*)
360 ppc4xx_reg
[i
].address
);
363 printf("\nERROR: struct entry %d: unknown register"
367 printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg
[i
].address
,
368 ppc4xx_reg
[i
].name
, value
);