arch/ppc/platforms/85xx/stx_gp3.c

   1 /*
   2  * arch/ppc/platforms/85xx/stx_gp3.c
   3  *
   4  * STx GP3 board specific routines
   5  *
   6  * Dan Malek <dan@embeddededge.com>
   7  * Copyright 2004 Embedded Edge, LLC
   8  *
   9  * Copied from mpc8560_ads.c
  10  * Copyright 2002, 2003 Motorola Inc.
  11  *
  12  * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
  13  * Copyright 2004-2005 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  */
  20
  21 #include <linux/config.h>
  22 #include <linux/stddef.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/errno.h>
  26 #include <linux/reboot.h>
  27 #include <linux/pci.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/major.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/console.h>
  32 #include <linux/delay.h>
  33 #include <linux/irq.h>
  34 #include <linux/root_dev.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/serial.h>
  37 #include <linux/initrd.h>
  38 #include <linux/module.h>
  39 #include <linux/fsl_devices.h>
  40 #include <linux/interrupt.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/page.h>
  45 #include <asm/atomic.h>
  46 #include <asm/time.h>
  47 #include <asm/io.h>
  48 #include <asm/machdep.h>
  49 #include <asm/prom.h>
  50 #include <asm/open_pic.h>
  51 #include <asm/bootinfo.h>
  52 #include <asm/pci-bridge.h>
  53 #include <asm/mpc85xx.h>
  54 #include <asm/irq.h>
  55 #include <asm/immap_85xx.h>
  56 #include <asm/immap_cpm2.h>
  57 #include <asm/mpc85xx.h>
  58 #include <asm/ppc_sys.h>
  59
  60 #include <syslib/cpm2_pic.h>
  61 #include <syslib/ppc85xx_common.h>
  62
  63 extern void cpm2_reset(void);
  64
  65 unsigned char __res[sizeof(bd_t)];
  66
  67 #ifndef CONFIG_PCI
  68 unsigned long isa_io_base = 0;
  69 unsigned long isa_mem_base = 0;
  70 unsigned long pci_dram_offset = 0;
  71 #endif
  72
  73 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  74 static u8 gp3_openpic_initsenses[] __initdata = {
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
  86         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
  87         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
  88         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
  89         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
  91         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
  92         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
  93         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
  94         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
  95         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
  96         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
  97         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
  98         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
  99         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
 100         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
 101         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
 102         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
 103         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
 104         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
 105         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
 106         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
 107         0x0,                                            /* External  0: */
 108 #if defined(CONFIG_PCI)
 109         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
 110         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
 111         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
 112         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
 113 #else
 114         0x0,                            /* External  1: */
 115         0x0,                            /* External  2: */
 116         0x0,                            /* External  3: */
 117         0x0,                            /* External  4: */
 118 #endif
 119         0x0,                            /* External  5: */
 120         0x0,                            /* External  6: */
 121         0x0,                            /* External  7: */
 122         0x0,                            /* External  8: */
 123         0x0,                            /* External  9: */
 124         0x0,                            /* External 10: */
 125         0x0,                            /* External 11: */
 126 };
 127
 128 /*
 129  * Setup the architecture
 130  */
 131 static void __init
 132 gp3_setup_arch(void)
 133 {
 134         bd_t *binfo = (bd_t *) __res;
 135         unsigned int freq;
 136         struct gianfar_platform_data *pdata;
 137
 138         cpm2_reset();
 139
 140         /* get the core frequency */
 141         freq = binfo->bi_intfreq;
 142
 143         if (ppc_md.progress)
 144                 ppc_md.progress("gp3_setup_arch()", 0);
 145
 146         /* Set loops_per_jiffy to a half-way reasonable value,
 147            for use until calibrate_delay gets called. */
 148         loops_per_jiffy = freq / HZ;
 149
 150 #ifdef CONFIG_PCI
 151         /* setup PCI host bridges */
 152         mpc85xx_setup_hose();
 153 #endif
 154
 155         /* setup the board related information for the enet controllers */
 156         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 157 /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 158         pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 159         pdata->phyid = 2;
 160         pdata->phy_reg_addr += binfo->bi_immr_base;
 161         memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 162
 163         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 164 /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 165         pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 166         pdata->phyid = 4;
 167         /* fixup phy address */
 168         pdata->phy_reg_addr += binfo->bi_immr_base;
 169         memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 170
 171 #ifdef CONFIG_BLK_DEV_INITRD
 172         if (initrd_start)
 173                 ROOT_DEV = Root_RAM0;
 174         else
 175 #endif
 176 #ifdef  CONFIG_ROOT_NFS
 177                 ROOT_DEV = Root_NFS;
 178 #else
 179                 ROOT_DEV = Root_HDA1;
 180 #endif
 181
 182         printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
 183 }
 184
 185 static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
 186 {
 187         while ((irq = cpm2_get_irq(regs)) >= 0)
 188                 __do_IRQ(irq, regs);
 189
 190         return IRQ_HANDLED;
 191 }
 192
 193 static struct irqaction cpm2_irqaction = {
 194         .handler        = cpm2_cascade,
 195         .flags          = SA_INTERRUPT,
 196         .mask           = CPU_MASK_NONE,
 197         .name           = "cpm2_cascade",
 198 };
 199
 200 static void __init
 201 gp3_init_IRQ(void)
 202 {
 203         int i;
 204         bd_t *binfo = (bd_t *) __res;
 205
 206         /*
 207          * Setup OpenPIC
 208          */
 209
 210         /* Determine the Physical Address of the OpenPIC regs */
 211         phys_addr_t OpenPIC_PAddr =
 212             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 213         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 214         OpenPIC_InitSenses = gp3_openpic_initsenses;
 215         OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
 216
 217         /* Skip reserved space and internal sources */
 218         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 219
 220         /* Map PIC IRQs 0-11 */
 221         openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
 222
 223         /*
 224          * Let openpic interrupts starting from an offset, to
 225          * leave space for cascading interrupts underneath.
 226          */
 227         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 228
 229         /* Setup CPM2 PIC */
 230         cpm2_init_IRQ();
 231
 232         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 233
 234         return;
 235 }
 236
 237 static int
 238 gp3_show_cpuinfo(struct seq_file *m)
 239 {
 240         uint pvid, svid, phid1;
 241         bd_t *binfo = (bd_t *) __res;
 242         uint    memsize;
 243         unsigned int freq;
 244         extern unsigned long total_memory;      /* in mm/init */
 245
 246         /* get the core frequency */
 247         freq = binfo->bi_intfreq;
 248
 249         pvid = mfspr(SPRN_PVR);
 250         svid = mfspr(SPRN_SVR);
 251
 252         memsize = total_memory;
 253
 254         seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
 255         seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
 256         seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
 257                    freq % 1000000);
 258         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 259         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 260
 261         /* Display cpu Pll setting */
 262         phid1 = mfspr(SPRN_HID1);
 263         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 264
 265         /* Display the amount of memory */
 266         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 267
 268         return 0;
 269 }
 270
 271 #ifdef CONFIG_PCI
 272 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 273                     unsigned char pin)
 274 {
 275         static char pci_irq_table[][4] =
 276             /*
 277              *      PCI IDSEL/INTPIN->INTLINE
 278              *        A      B      C      D
 279              */
 280         {
 281                 {PIRQA, PIRQB, PIRQC, PIRQD},
 282                 {PIRQD, PIRQA, PIRQB, PIRQC},
 283                 {PIRQC, PIRQD, PIRQA, PIRQB},
 284                 {PIRQB, PIRQC, PIRQD, PIRQA},
 285         };
 286
 287         const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
 288         return PCI_IRQ_TABLE_LOOKUP;
 289 }
 290
 291 int mpc85xx_exclude_device(u_char bus, u_char devfn)
 292 {
 293         if (bus == 0 && PCI_SLOT(devfn) == 0)
 294                 return PCIBIOS_DEVICE_NOT_FOUND;
 295         else
 296                 return PCIBIOS_SUCCESSFUL;
 297 }
 298 #endif /* CONFIG_PCI */
 299
 300 void __init
 301 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 302               unsigned long r6, unsigned long r7)
 303 {
 304         /* parse_bootinfo must always be called first */
 305         parse_bootinfo(find_bootinfo());
 306
 307         /*
 308          * If we were passed in a board information, copy it into the
 309          * residual data area.
 310          */
 311         if (r3) {
 312                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 313                        sizeof (bd_t));
 314
 315         }
 316 #if defined(CONFIG_BLK_DEV_INITRD)
 317         /*
 318          * If the init RAM disk has been configured in, and there's a valid
 319          * starting address for it, set it up.
 320          */
 321         if (r4) {
 322                 initrd_start = r4 + KERNELBASE;
 323                 initrd_end = r5 + KERNELBASE;
 324         }
 325 #endif                          /* CONFIG_BLK_DEV_INITRD */
 326
 327         /* Copy the kernel command line arguments to a safe place. */
 328
 329         if (r6) {
 330                 *(char *) (r7 + KERNELBASE) = 0;
 331                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 332         }
 333
 334         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 335
 336         /* setup the PowerPC module struct */
 337         ppc_md.setup_arch = gp3_setup_arch;
 338         ppc_md.show_cpuinfo = gp3_show_cpuinfo;
 339
 340         ppc_md.init_IRQ = gp3_init_IRQ;
 341         ppc_md.get_irq = openpic_get_irq;
 342
 343         ppc_md.restart = mpc85xx_restart;
 344         ppc_md.power_off = mpc85xx_power_off;
 345         ppc_md.halt = mpc85xx_halt;
 346
 347         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 348
 349         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 350
 351         if (ppc_md.progress)
 352                 ppc_md.progress("platform_init(): exit", 0);
 353
 354         return;
 355 }