arch/ppc64/kernel/cpu_setup_power4.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <linux/config.h>
  13 #include <asm/processor.h>
  14 #include <asm/page.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/cputable.h>
  17 #include <asm/ppc_asm.h>
  18 #include <asm/offsets.h>
  19 #include <asm/cache.h>
  20
  21 _GLOBAL(__970_cpu_preinit)
  22         /*
  23          * Do nothing if not running in HV mode
  24          */
  25         mfmsr   r0
  26         rldicl. r0,r0,4,63
  27         beqlr
  28
  29         /*
  30          * Deal only with PPC970 and PPC970FX.
  31          */
  32         mfspr   r0,SPRN_PVR
  33         srwi    r0,r0,16
  34         cmpwi   cr0,r0,0x39
  35         cmpwi   cr1,r0,0x3c
  36         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
  37         bnelr
  38
  39         /* Make sure HID4:rm_ci is off before MMU is turned off, that large
  40          * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
  41          * HID5:DCBZ32_ill
  42          */
  43         li      r0,0
  44         mfspr   r3,SPRN_HID4
  45         rldimi  r3,r0,40,23     /* clear bit 23 (rm_ci) */
  46         rldimi  r3,r0,2,61      /* clear bit 61 (lg_pg_en) */
  47         sync
  48         mtspr   SPRN_HID4,r3
  49         isync
  50         sync
  51         mfspr   r3,SPRN_HID5
  52         rldimi  r3,r0,6,56      /* clear bits 56 & 57 (DCBZ*) */
  53         sync
  54         mtspr   SPRN_HID5,r3
  55         isync
  56         sync
  57
  58         /* Setup some basic HID1 features */
  59         mfspr   r0,SPRN_HID1
  60         li      r3,0x1200               /* enable i-fetch cacheability */
  61         sldi    r3,r3,44                /* and prefetch */
  62         or      r0,r0,r3
  63         mtspr   SPRN_HID1,r0
  64         mtspr   SPRN_HID1,r0
  65         isync
  66
  67         /* Clear HIOR */
  68         li      r0,0
  69         sync
  70         mtspr   SPRN_HIOR,0             /* Clear interrupt prefix */
  71         isync
  72         blr
  73
  74 _GLOBAL(__setup_cpu_power4)
  75         blr
  76
  77 _GLOBAL(__setup_cpu_ppc970)
  78         mfspr   r0,SPRN_HID0
  79         li      r11,5                   /* clear DOZE and SLEEP */
  80         rldimi  r0,r11,52,8             /* set NAP and DPM */
  81         mtspr   SPRN_HID0,r0
  82         mfspr   r0,SPRN_HID0
  83         mfspr   r0,SPRN_HID0
  84         mfspr   r0,SPRN_HID0
  85         mfspr   r0,SPRN_HID0
  86         mfspr   r0,SPRN_HID0
  87         mfspr   r0,SPRN_HID0
  88         sync
  89         isync
  90         blr
  91
  92 /* Definitions for the table use to save CPU states */
  93 #define CS_HID0         0
  94 #define CS_HID1         8
  95 #define CS_HID4         16
  96 #define CS_HID5         24
  97 #define CS_SIZE         32
  98
  99         .data
 100         .balign L1_CACHE_BYTES,0
 101 cpu_state_storage:
 102         .space  CS_SIZE
 103         .balign L1_CACHE_BYTES,0
 104         .text
 105
 106 /* Called in normal context to backup CPU 0 state. This
 107  * does not include cache settings. This function is also
 108  * called for machine sleep. This does not include the MMU
 109  * setup, BATs, etc... but rather the "special" registers
 110  * like HID0, HID1, HID4, etc...
 111  */
 112 _GLOBAL(__save_cpu_setup)
 113         /* Some CR fields are volatile, we back it up all */
 114         mfcr    r7
 115
 116         /* Get storage ptr */
 117         LOADADDR(r5,cpu_state_storage)
 118
 119         /* We only deal with 970 for now */
 120         mfspr   r0,SPRN_PVR
 121         srwi    r0,r0,16
 122         cmpwi   cr0,r0,0x39
 123         cmpwi   cr1,r0,0x3c
 124         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 125         bne     1f
 126
 127         /* Save HID0,1,4 and 5 */
 128         mfspr   r3,SPRN_HID0
 129         std     r3,CS_HID0(r5)
 130         mfspr   r3,SPRN_HID1
 131         std     r3,CS_HID1(r5)
 132         mfspr   r3,SPRN_HID4
 133         std     r3,CS_HID4(r5)
 134         mfspr   r3,SPRN_HID5
 135         std     r3,CS_HID5(r5)
 136
 137 1:
 138         mtcr    r7
 139         blr
 140
 141 /* Called with no MMU context (typically MSR:IR/DR off) to
 142  * restore CPU state as backed up by the previous
 143  * function. This does not include cache setting
 144  */
 145 _GLOBAL(__restore_cpu_setup)
 146         /* Get storage ptr (FIXME when using anton reloc as we
 147          * are running with translation disabled here
 148          */
 149         LOADADDR(r5,cpu_state_storage)
 150
 151         /* We only deal with 970 for now */
 152         mfspr   r0,SPRN_PVR
 153         srwi    r0,r0,16
 154         cmpwi   cr0,r0,0x39
 155         cmpwi   cr1,r0,0x3c
 156         cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
 157         bne     1f
 158
 159         /* Before accessing memory, we make sure rm_ci is clear */
 160         li      r0,0
 161         mfspr   r3,SPRN_HID4
 162         rldimi  r3,r0,40,23     /* clear bit 23 (rm_ci) */
 163         sync
 164         mtspr   SPRN_HID4,r3
 165         isync
 166         sync
 167
 168         /* Clear interrupt prefix */
 169         li      r0,0
 170         sync
 171         mtspr   SPRN_HIOR,0
 172         isync
 173
 174         /* Restore HID0 */
 175         ld      r3,CS_HID0(r5)
 176         sync
 177         isync
 178         mtspr   SPRN_HID0,r3
 179         mfspr   r3,SPRN_HID0
 180         mfspr   r3,SPRN_HID0
 181         mfspr   r3,SPRN_HID0
 182         mfspr   r3,SPRN_HID0
 183         mfspr   r3,SPRN_HID0
 184         mfspr   r3,SPRN_HID0
 185         sync
 186         isync
 187
 188         /* Restore HID1 */
 189         ld      r3,CS_HID1(r5)
 190         sync
 191         isync
 192         mtspr   SPRN_HID1,r3
 193         mtspr   SPRN_HID1,r3
 194         sync
 195         isync
 196
 197         /* Restore HID4 */
 198         ld      r3,CS_HID4(r5)
 199         sync
 200         isync
 201         mtspr   SPRN_HID4,r3
 202         sync
 203         isync
 204
 205         /* Restore HID5 */
 206         ld      r3,CS_HID5(r5)
 207         sync
 208         isync
 209         mtspr   SPRN_HID5,r3
 210         sync
 211         isync
 212 1:
 213         blr
 214