arch/riscv/Kconfig

   1 menu "RISC-V architecture"
   2         depends on RISCV
   3
   4 config SYS_ARCH
   5         default "riscv"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_AX25_AE350
  12         bool "Support ax25-ae350"
  13
  14 config TARGET_QEMU_VIRT
  15         bool "Support QEMU Virt Board"
  16
  17 config TARGET_SIFIVE_FU540
  18         bool "Support SiFive FU540 Board"
  19
  20 endchoice
  21
  22 config SYS_ICACHE_OFF
  23         bool "Do not enable icache"
  24         default n
  25         help
  26           Do not enable instruction cache in U-Boot.
  27
  28 config SPL_SYS_ICACHE_OFF
  29         bool "Do not enable icache in SPL"
  30         depends on SPL
  31         default SYS_ICACHE_OFF
  32         help
  33           Do not enable instruction cache in SPL.
  34
  35 config SYS_DCACHE_OFF
  36         bool "Do not enable dcache"
  37         default n
  38         help
  39           Do not enable data cache in U-Boot.
  40
  41 config SPL_SYS_DCACHE_OFF
  42         bool "Do not enable dcache in SPL"
  43         depends on SPL
  44         default SYS_DCACHE_OFF
  45         help
  46           Do not enable data cache in SPL.
  47
  48 # board-specific options below
  49 source "board/AndesTech/ax25-ae350/Kconfig"
  50 source "board/emulation/qemu-riscv/Kconfig"
  51 source "board/sifive/fu540/Kconfig"
  52
  53 # platform-specific options below
  54 source "arch/riscv/cpu/ax25/Kconfig"
  55 source "arch/riscv/cpu/generic/Kconfig"
  56
  57 # architecture-specific options below
  58
  59 choice
  60         prompt "Base ISA"
  61         default ARCH_RV32I
  62
  63 config ARCH_RV32I
  64         bool "RV32I"
  65         select 32BIT
  66         help
  67           Choose this option to target the RV32I base integer instruction set.
  68
  69 config ARCH_RV64I
  70         bool "RV64I"
  71         select 64BIT
  72         select PHYS_64BIT
  73         help
  74           Choose this option to target the RV64I base integer instruction set.
  75
  76 endchoice
  77
  78 choice
  79         prompt "Code Model"
  80         default CMODEL_MEDLOW
  81
  82 config CMODEL_MEDLOW
  83         bool "medium low code model"
  84         help
  85           U-Boot and its statically defined symbols must lie within a single 2 GiB
  86           address range and must lie between absolute addresses -2 GiB and +2 GiB.
  87
  88 config CMODEL_MEDANY
  89         bool "medium any code model"
  90         help
  91           U-Boot and its statically defined symbols must be within any single 2 GiB
  92           address range.
  93
  94 endchoice
  95
  96 choice
  97         prompt "Run Mode"
  98         default RISCV_MMODE
  99
 100 config RISCV_MMODE
 101         bool "Machine"
 102         help
 103           Choose this option to build U-Boot for RISC-V M-Mode.
 104
 105 config RISCV_SMODE
 106         bool "Supervisor"
 107         help
 108           Choose this option to build U-Boot for RISC-V S-Mode.
 109
 110 endchoice
 111
 112 config RISCV_ISA_C
 113         bool "Emit compressed instructions"
 114         default y
 115         help
 116           Adds "C" to the ISA subsets that the toolchain is allowed to emit
 117           when building U-Boot, which results in compressed instructions in the
 118           U-Boot binary.
 119
 120 config RISCV_ISA_A
 121         def_bool y
 122
 123 config 32BIT
 124         bool
 125
 126 config 64BIT
 127         bool
 128
 129 config SIFIVE_CLINT
 130         bool
 131         depends on RISCV_MMODE
 132         select REGMAP
 133         select SYSCON
 134         help
 135           The SiFive CLINT block holds memory-mapped control and status registers
 136           associated with software and timer interrupts.
 137
 138 config ANDES_PLIC
 139         bool
 140         depends on RISCV_MMODE
 141         select REGMAP
 142         select SYSCON
 143         help
 144           The Andes PLIC block holds memory-mapped claim and pending registers
 145           associated with software interrupt.
 146
 147 config ANDES_PLMT
 148         bool
 149         depends on RISCV_MMODE
 150         select REGMAP
 151         select SYSCON
 152         help
 153           The Andes PLMT block holds memory-mapped mtime register
 154           associated with timer tick.
 155
 156 config RISCV_RDTIME
 157         bool
 158         default y if RISCV_SMODE
 159         help
 160           The provides the riscv_get_time() API that is implemented using the
 161           standard rdtime instruction. This is the case for S-mode U-Boot, and
 162           is useful for processors that support rdtime in M-mode too.
 163
 164 config SYS_MALLOC_F_LEN
 165         default 0x1000
 166
 167 config SMP
 168         bool "Symmetric Multi-Processing"
 169         help
 170           This enables support for systems with more than one CPU. If
 171           you say N here, U-Boot will run on single and multiprocessor
 172           machines, but will use only one CPU of a multiprocessor
 173           machine. If you say Y here, U-Boot will run on many, but not
 174           all, single processor machines.
 175
 176 config NR_CPUS
 177         int "Maximum number of CPUs (2-32)"
 178         range 2 32
 179         depends on SMP
 180         default 8
 181         help
 182           On multiprocessor machines, U-Boot sets up a stack for each CPU.
 183           Stack memory is pre-allocated. U-Boot must therefore know the
 184           maximum number of CPUs that may be present.
 185
 186 config SBI_IPI
 187         bool
 188         default y if RISCV_SMODE
 189         depends on SMP
 190
 191 config XIP
 192         bool "XIP mode"
 193         help
 194           XIP (eXecute In Place) is a method for executing code directly
 195           from a NOR flash memory without copying the code to ram.
 196           Say yes here if U-Boot boots from flash directly.
 197
 198 config STACK_SIZE_SHIFT
 199         int
 200         default 13
 201
 202 endmenu