arch/riscv/Kconfig

   1 menu "RISC-V architecture"
   2         depends on RISCV
   3
   4 config SYS_ARCH
   5         default "riscv"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_AX25_AE350
  12         bool "Support ax25-ae350"
  13
  14 config TARGET_QEMU_VIRT
  15         bool "Support QEMU Virt Board"
  16
  17 config TARGET_SIFIVE_FU540
  18         bool "Support SiFive FU540 Board"
  19
  20 endchoice
  21
  22 # board-specific options below
  23 source "board/AndesTech/ax25-ae350/Kconfig"
  24 source "board/emulation/qemu-riscv/Kconfig"
  25 source "board/sifive/fu540/Kconfig"
  26
  27 # platform-specific options below
  28 source "arch/riscv/cpu/ax25/Kconfig"
  29 source "arch/riscv/cpu/generic/Kconfig"
  30
  31 # architecture-specific options below
  32
  33 choice
  34         prompt "Base ISA"
  35         default ARCH_RV32I
  36
  37 config ARCH_RV32I
  38         bool "RV32I"
  39         select 32BIT
  40         help
  41           Choose this option to target the RV32I base integer instruction set.
  42
  43 config ARCH_RV64I
  44         bool "RV64I"
  45         select 64BIT
  46         select PHYS_64BIT
  47         help
  48           Choose this option to target the RV64I base integer instruction set.
  49
  50 endchoice
  51
  52 choice
  53         prompt "Code Model"
  54         default CMODEL_MEDLOW
  55
  56 config CMODEL_MEDLOW
  57         bool "medium low code model"
  58         help
  59           U-Boot and its statically defined symbols must lie within a single 2 GiB
  60           address range and must lie between absolute addresses -2 GiB and +2 GiB.
  61
  62 config CMODEL_MEDANY
  63         bool "medium any code model"
  64         help
  65           U-Boot and its statically defined symbols must be within any single 2 GiB
  66           address range.
  67
  68 endchoice
  69
  70 choice
  71         prompt "Run Mode"
  72         default RISCV_MMODE
  73
  74 config RISCV_MMODE
  75         bool "Machine"
  76         help
  77           Choose this option to build U-Boot for RISC-V M-Mode.
  78
  79 config RISCV_SMODE
  80         bool "Supervisor"
  81         help
  82           Choose this option to build U-Boot for RISC-V S-Mode.
  83
  84 endchoice
  85
  86 config RISCV_ISA_C
  87         bool "Emit compressed instructions"
  88         default y
  89         help
  90           Adds "C" to the ISA subsets that the toolchain is allowed to emit
  91           when building U-Boot, which results in compressed instructions in the
  92           U-Boot binary.
  93
  94 config RISCV_ISA_A
  95         def_bool y
  96
  97 config 32BIT
  98         bool
  99
 100 config 64BIT
 101         bool
 102
 103 config SIFIVE_CLINT
 104         bool
 105         depends on RISCV_MMODE
 106         select REGMAP
 107         select SYSCON
 108         help
 109           The SiFive CLINT block holds memory-mapped control and status registers
 110           associated with software and timer interrupts.
 111
 112 config RISCV_RDTIME
 113         bool
 114         default y if RISCV_SMODE
 115         help
 116           The provides the riscv_get_time() API that is implemented using the
 117           standard rdtime instruction. This is the case for S-mode U-Boot, and
 118           is useful for processors that support rdtime in M-mode too.
 119
 120 config SYS_MALLOC_F_LEN
 121         default 0x1000
 122
 123 config SMP
 124         bool "Symmetric Multi-Processing"
 125         help
 126           This enables support for systems with more than one CPU. If
 127           you say N here, U-Boot will run on single and multiprocessor
 128           machines, but will use only one CPU of a multiprocessor
 129           machine. If you say Y here, U-Boot will run on many, but not
 130           all, single processor machines.
 131
 132 config NR_CPUS
 133         int "Maximum number of CPUs (2-32)"
 134         range 2 32
 135         depends on SMP
 136         default 8
 137         help
 138           On multiprocessor machines, U-Boot sets up a stack for each CPU.
 139           Stack memory is pre-allocated. U-Boot must therefore know the
 140           maximum number of CPUs that may be present.
 141
 142 config SBI_IPI
 143         bool
 144         default y if RISCV_SMODE
 145         depends on SMP
 146
 147 endmenu