arch/riscv/cpu/ax25/cache.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <dm/uclass-internal.h>
  11 #include <cache.h>
  12 #include <asm/csr.h>
  13
  14 #ifdef CONFIG_RISCV_NDS_CACHE
  15 #if CONFIG_IS_ENABLED(RISCV_MMODE)
  16 /* mcctlcommand */
  17 #define CCTL_REG_MCCTLCOMMAND_NUM       0x7cc
  18
  19 /* D-cache operation */
  20 #define CCTL_L1D_WBINVAL_ALL    6
  21 #endif
  22 #endif
  23
  24 #ifdef CONFIG_V5L2_CACHE
  25 static void _cache_enable(void)
  26 {
  27         struct udevice *dev = NULL;
  28
  29         uclass_find_first_device(UCLASS_CACHE, &dev);
  30
  31         if (dev)
  32                 cache_enable(dev);
  33 }
  34
  35 static void _cache_disable(void)
  36 {
  37         struct udevice *dev = NULL;
  38
  39         uclass_find_first_device(UCLASS_CACHE, &dev);
  40
  41         if (dev)
  42                 cache_disable(dev);
  43 }
  44 #endif
  45
  46 void flush_dcache_all(void)
  47 {
  48 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  49 #ifdef CONFIG_RISCV_NDS_CACHE
  50 #if CONFIG_IS_ENABLED(RISCV_MMODE)
  51         csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
  52 #endif
  53 #endif
  54 #endif
  55 }
  56
  57 void flush_dcache_range(unsigned long start, unsigned long end)
  58 {
  59         flush_dcache_all();
  60 }
  61
  62 void invalidate_dcache_range(unsigned long start, unsigned long end)
  63 {
  64         flush_dcache_all();
  65 }
  66
  67 void icache_enable(void)
  68 {
  69 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  70 #ifdef CONFIG_RISCV_NDS_CACHE
  71 #if CONFIG_IS_ENABLED(RISCV_MMODE)
  72         asm volatile (
  73                 "csrr t1, mcache_ctl\n\t"
  74                 "ori t0, t1, 0x1\n\t"
  75                 "csrw mcache_ctl, t0\n\t"
  76         );
  77 #endif
  78 #endif
  79 #endif
  80 }
  81
  82 void icache_disable(void)
  83 {
  84 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  85 #ifdef CONFIG_RISCV_NDS_CACHE
  86 #if CONFIG_IS_ENABLED(RISCV_MMODE)
  87         asm volatile (
  88                 "fence.i\n\t"
  89                 "csrr t1, mcache_ctl\n\t"
  90                 "andi t0, t1, ~0x1\n\t"
  91                 "csrw mcache_ctl, t0\n\t"
  92         );
  93 #endif
  94 #endif
  95 #endif
  96 }
  97
  98 void dcache_enable(void)
  99 {
 100 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 101 #ifdef CONFIG_RISCV_NDS_CACHE
 102 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 103         asm volatile (
 104                 "csrr t1, mcache_ctl\n\t"
 105                 "ori t0, t1, 0x2\n\t"
 106                 "csrw mcache_ctl, t0\n\t"
 107         );
 108 #endif
 109 #ifdef CONFIG_V5L2_CACHE
 110         _cache_enable();
 111 #endif
 112 #endif
 113 #endif
 114 }
 115
 116 void dcache_disable(void)
 117 {
 118 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 119 #ifdef CONFIG_RISCV_NDS_CACHE
 120 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 121         csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
 122         asm volatile (
 123                 "csrr t1, mcache_ctl\n\t"
 124                 "andi t0, t1, ~0x2\n\t"
 125                 "csrw mcache_ctl, t0\n\t"
 126         );
 127 #endif
 128 #ifdef CONFIG_V5L2_CACHE
 129         _cache_disable();
 130 #endif
 131 #endif
 132 #endif
 133 }
 134
 135 int icache_status(void)
 136 {
 137         int ret = 0;
 138
 139 #ifdef CONFIG_RISCV_NDS_CACHE
 140 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 141         asm volatile (
 142                 "csrr t1, mcache_ctl\n\t"
 143                 "andi   %0, t1, 0x01\n\t"
 144                 : "=r" (ret)
 145                 :
 146                 : "memory"
 147         );
 148 #endif
 149 #endif
 150
 151         return ret;
 152 }
 153
 154 int dcache_status(void)
 155 {
 156         int ret = 0;
 157
 158 #ifdef CONFIG_RISCV_NDS_CACHE
 159 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 160         asm volatile (
 161                 "csrr t1, mcache_ctl\n\t"
 162                 "andi   %0, t1, 0x02\n\t"
 163                 : "=r" (ret)
 164                 :
 165                 : "memory"
 166         );
 167 #endif
 168 #endif
 169
 170         return ret;
 171 }