1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * (C) Copyright 2020-2021 SiFive, Inc
6 #include <dt-bindings/reset/sifive-fu740-prci.h>
10 assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
11 assigned-clock-rates = <1200000000>;
14 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
17 cpu0_intc: interrupt-controller {
22 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
24 cpu1_intc: interrupt-controller {
29 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
31 cpu2_intc: interrupt-controller {
36 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
38 cpu3_intc: interrupt-controller {
43 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
45 cpu4_intc: interrupt-controller {
53 clint: clint@2000000 {
54 compatible = "riscv,clint0";
55 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
56 &cpu1_intc 3 &cpu1_intc 7
57 &cpu2_intc 3 &cpu2_intc 7
58 &cpu3_intc 3 &cpu3_intc 7
59 &cpu4_intc 3 &cpu4_intc 7>;
60 reg = <0x0 0x2000000 0x0 0x10000>;
63 prci: clock-controller@10000000 {
65 resets = <&prci PRCI_RST_DDR_CTRL_N>,
66 <&prci PRCI_RST_DDR_AXI_N>,
67 <&prci PRCI_RST_DDR_AHB_N>,
68 <&prci PRCI_RST_DDR_PHY_N>,
69 <&prci PRCI_RST_GEMGXL_N>,
70 <&prci PRCI_RST_CLTX_N>;
71 reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
72 "ddr_phy", "gemgxl_reset", "cltx_reset";
75 compatible = "sifive,fu740-c000-ddr";
76 reg = <0x0 0x100b0000 0x0 0x0800
77 0x0 0x100b2000 0x0 0x2000
78 0x0 0x100b8000 0x0 0x1000>;
79 clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
80 clock-frequency = <933333324>;
103 assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
104 assigned-clock-rates = <125125000>;