1 // SPDX-License-Identifier: GPL-2.0-only
3 * Erratas to be applied for Andes CPU cores
5 * Copyright (C) 2023 Renesas Electronics Corporation.
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
10 #include <linux/memory.h>
11 #include <linux/module.h>
13 #include <asm/alternative.h>
14 #include <asm/cacheflush.h>
15 #include <asm/errata_list.h>
16 #include <asm/patch.h>
17 #include <asm/processor.h>
19 #include <asm/vendorid_list.h>
21 #define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
22 #define ANDESTECH_AX45MP_MIMPID 0x500UL
23 #define ANDESTECH_SBI_EXT_ANDES 0x0900031E
25 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
27 static long ax45mp_iocp_sw_workaround(void)
32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
33 * cache is controllable only then CMO will be applied to the platform.
35 ret
= sbi_ecall(ANDESTECH_SBI_EXT_ANDES
, ANDES_SBI_EXT_IOCP_SW_WORKAROUND
,
38 return ret
.error
? 0 : ret
.value
;
41 static bool errata_probe_iocp(unsigned int stage
, unsigned long arch_id
, unsigned long impid
)
43 if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO
))
46 if (arch_id
!= ANDESTECH_AX45MP_MARCHID
|| impid
!= ANDESTECH_AX45MP_MIMPID
)
49 if (!ax45mp_iocp_sw_workaround())
52 /* Set this just to make core cbo code happy */
53 riscv_cbom_block_size
= 1;
54 riscv_noncoherent_supported();
59 void __init_or_module
andes_errata_patch_func(struct alt_entry
*begin
, struct alt_entry
*end
,
60 unsigned long archid
, unsigned long impid
,
63 errata_probe_iocp(stage
, archid
, impid
);
65 /* we have nothing to patch here ATM so just return back */