arch/riscv/include/asm/hwcap.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copied from arch/arm64/include/asm/hwcap.h
   4  *
   5  * Copyright (C) 2012 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8 #ifndef _ASM_RISCV_HWCAP_H
   9 #define _ASM_RISCV_HWCAP_H
  10
  11 #include <uapi/asm/hwcap.h>
  12
  13 #ifndef __ASSEMBLY__
  14 /*
  15  * This yields a mask that user programs can use to figure out what
  16  * instruction set this cpu supports.
  17  */
  18 #define ELF_HWCAP               (elf_hwcap)
  19
  20 enum {
  21         CAP_HWCAP = 1,
  22 };
  23
  24 extern unsigned long elf_hwcap;
  25 #endif
  26
  27 #endif /* _ASM_RISCV_HWCAP_H */