arch/riscv/include/asm/hwcap.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copied from arch/arm64/include/asm/hwcap.h
   4  *
   5  * Copyright (C) 2012 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8 #ifndef _ASM_RISCV_HWCAP_H
   9 #define _ASM_RISCV_HWCAP_H
  10
  11 #include <asm/alternative-macros.h>
  12 #include <asm/errno.h>
  13 #include <linux/bits.h>
  14 #include <uapi/asm/hwcap.h>
  15
  16 #define RISCV_ISA_EXT_a         ('a' - 'a')
  17 #define RISCV_ISA_EXT_b         ('b' - 'a')
  18 #define RISCV_ISA_EXT_c         ('c' - 'a')
  19 #define RISCV_ISA_EXT_d         ('d' - 'a')
  20 #define RISCV_ISA_EXT_f         ('f' - 'a')
  21 #define RISCV_ISA_EXT_h         ('h' - 'a')
  22 #define RISCV_ISA_EXT_i         ('i' - 'a')
  23 #define RISCV_ISA_EXT_j         ('j' - 'a')
  24 #define RISCV_ISA_EXT_k         ('k' - 'a')
  25 #define RISCV_ISA_EXT_m         ('m' - 'a')
  26 #define RISCV_ISA_EXT_p         ('p' - 'a')
  27 #define RISCV_ISA_EXT_q         ('q' - 'a')
  28 #define RISCV_ISA_EXT_s         ('s' - 'a')
  29 #define RISCV_ISA_EXT_u         ('u' - 'a')
  30 #define RISCV_ISA_EXT_v         ('v' - 'a')
  31
  32 /*
  33  * These macros represent the logical IDs of each multi-letter RISC-V ISA
  34  * extension and are used in the ISA bitmap. The logical IDs start from
  35  * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
  36  * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
  37  * to allocate the bitmap and may be increased when necessary.
  38  *
  39  * New extensions should just be added to the bottom, rather than added
  40  * alphabetically, in order to avoid unnecessary shuffling.
  41  */
  42 #define RISCV_ISA_EXT_BASE              26
  43
  44 #define RISCV_ISA_EXT_SSCOFPMF          26
  45 #define RISCV_ISA_EXT_SSTC              27
  46 #define RISCV_ISA_EXT_SVINVAL           28
  47 #define RISCV_ISA_EXT_SVPBMT            29
  48 #define RISCV_ISA_EXT_ZBB               30
  49 #define RISCV_ISA_EXT_ZICBOM            31
  50 #define RISCV_ISA_EXT_ZIHINTPAUSE       32
  51 #define RISCV_ISA_EXT_SVNAPOT           33
  52 #define RISCV_ISA_EXT_ZICBOZ            34
  53 #define RISCV_ISA_EXT_SMAIA             35
  54 #define RISCV_ISA_EXT_SSAIA             36
  55 #define RISCV_ISA_EXT_ZBA               37
  56 #define RISCV_ISA_EXT_ZBS               38
  57 #define RISCV_ISA_EXT_ZICNTR            39
  58 #define RISCV_ISA_EXT_ZICSR             40
  59 #define RISCV_ISA_EXT_ZIFENCEI          41
  60 #define RISCV_ISA_EXT_ZIHPM             42
  61 #define RISCV_ISA_EXT_SMSTATEEN         43
  62 #define RISCV_ISA_EXT_ZICOND            44
  63
  64 #define RISCV_ISA_EXT_MAX               64
  65
  66 #ifdef CONFIG_RISCV_M_MODE
  67 #define RISCV_ISA_EXT_SxAIA             RISCV_ISA_EXT_SMAIA
  68 #else
  69 #define RISCV_ISA_EXT_SxAIA             RISCV_ISA_EXT_SSAIA
  70 #endif
  71
  72 #ifndef __ASSEMBLY__
  73
  74 #include <linux/jump_label.h>
  75
  76 unsigned long riscv_get_elf_hwcap(void);
  77
  78 struct riscv_isa_ext_data {
  79         const unsigned int id;
  80         const char *name;
  81         const char *property;
  82 };
  83
  84 extern const struct riscv_isa_ext_data riscv_isa_ext[];
  85 extern const size_t riscv_isa_ext_count;
  86 extern bool riscv_isa_fallback;
  87
  88 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
  89
  90 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
  91
  92 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
  93 #define riscv_isa_extension_available(isa_bitmap, ext)  \
  94         __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
  95
  96 static __always_inline bool
  97 riscv_has_extension_likely(const unsigned long ext)
  98 {
  99         compiletime_assert(ext < RISCV_ISA_EXT_MAX,
 100                            "ext must be < RISCV_ISA_EXT_MAX");
 101
 102         if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
 103                 asm_volatile_goto(
 104                 ALTERNATIVE("j  %l[l_no]", "nop", 0, %[ext], 1)
 105                 :
 106                 : [ext] "i" (ext)
 107                 :
 108                 : l_no);
 109         } else {
 110                 if (!__riscv_isa_extension_available(NULL, ext))
 111                         goto l_no;
 112         }
 113
 114         return true;
 115 l_no:
 116         return false;
 117 }
 118
 119 static __always_inline bool
 120 riscv_has_extension_unlikely(const unsigned long ext)
 121 {
 122         compiletime_assert(ext < RISCV_ISA_EXT_MAX,
 123                            "ext must be < RISCV_ISA_EXT_MAX");
 124
 125         if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
 126                 asm_volatile_goto(
 127                 ALTERNATIVE("nop", "j   %l[l_yes]", 0, %[ext], 1)
 128                 :
 129                 : [ext] "i" (ext)
 130                 :
 131                 : l_yes);
 132         } else {
 133                 if (__riscv_isa_extension_available(NULL, ext))
 134                         goto l_yes;
 135         }
 136
 137         return false;
 138 l_yes:
 139         return true;
 140 }
 141
 142 #endif
 143
 144 #endif /* _ASM_RISCV_HWCAP_H */