arch/riscv/include/asm/mmio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
   4  *   which was based on arch/arm/include/io.h
   5  *
   6  * Copyright (C) 1996-2000 Russell King
   7  * Copyright (C) 2012 ARM Ltd.
   8  * Copyright (C) 2014 Regents of the University of California
   9  */
  10
  11 #ifndef _ASM_RISCV_MMIO_H
  12 #define _ASM_RISCV_MMIO_H
  13
  14 #include <linux/types.h>
  15 #include <asm/mmiowb.h>
  16
  17 #ifndef CONFIG_MMU
  18 #define pgprot_noncached(x)     (x)
  19 #define pgprot_writecombine(x)  (x)
  20 #define pgprot_device(x)        (x)
  21 #endif /* CONFIG_MMU */
  22
  23 /* Generic IO read/write.  These perform native-endian accesses. */
  24 #define __raw_writeb __raw_writeb
  25 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  26 {
  27         asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
  28 }
  29
  30 #define __raw_writew __raw_writew
  31 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  32 {
  33         asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
  34 }
  35
  36 #define __raw_writel __raw_writel
  37 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  38 {
  39         asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  40 }
  41
  42 #ifdef CONFIG_64BIT
  43 #define __raw_writeq __raw_writeq
  44 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  45 {
  46         asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
  47 }
  48 #endif
  49
  50 #define __raw_readb __raw_readb
  51 static inline u8 __raw_readb(const volatile void __iomem *addr)
  52 {
  53         u8 val;
  54
  55         asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
  56         return val;
  57 }
  58
  59 #define __raw_readw __raw_readw
  60 static inline u16 __raw_readw(const volatile void __iomem *addr)
  61 {
  62         u16 val;
  63
  64         asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
  65         return val;
  66 }
  67
  68 #define __raw_readl __raw_readl
  69 static inline u32 __raw_readl(const volatile void __iomem *addr)
  70 {
  71         u32 val;
  72
  73         asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  74         return val;
  75 }
  76
  77 #ifdef CONFIG_64BIT
  78 #define __raw_readq __raw_readq
  79 static inline u64 __raw_readq(const volatile void __iomem *addr)
  80 {
  81         u64 val;
  82
  83         asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
  84         return val;
  85 }
  86 #endif
  87
  88 /*
  89  * Unordered I/O memory access primitives.  These are even more relaxed than
  90  * the relaxed versions, as they don't even order accesses between successive
  91  * operations to the I/O regions.
  92  */
  93 #define readb_cpu(c)            ({ u8  __r = __raw_readb(c); __r; })
  94 #define readw_cpu(c)            ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
  95 #define readl_cpu(c)            ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
  96
  97 #define writeb_cpu(v, c)        ((void)__raw_writeb((v), (c)))
  98 #define writew_cpu(v, c)        ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
  99 #define writel_cpu(v, c)        ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
 100
 101 #ifdef CONFIG_64BIT
 102 #define readq_cpu(c)            ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
 103 #define writeq_cpu(v, c)        ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
 104 #endif
 105
 106 /*
 107  * Relaxed I/O memory access primitives. These follow the Device memory
 108  * ordering rules but do not guarantee any ordering relative to Normal memory
 109  * accesses.  These are defined to order the indicated access (either a read or
 110  * write) with all other I/O memory accesses. Since the platform specification
 111  * defines that all I/O regions are strongly ordered on channel 2, no explicit
 112  * fences are required to enforce this ordering.
 113  */
 114 /* FIXME: These are now the same as asm-generic */
 115 #define __io_rbr()              do {} while (0)
 116 #define __io_rar()              do {} while (0)
 117 #define __io_rbw()              do {} while (0)
 118 #define __io_raw()              do {} while (0)
 119
 120 #define readb_relaxed(c)        ({ u8  __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
 121 #define readw_relaxed(c)        ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
 122 #define readl_relaxed(c)        ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
 123
 124 #define writeb_relaxed(v, c)    ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
 125 #define writew_relaxed(v, c)    ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
 126 #define writel_relaxed(v, c)    ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
 127
 128 #ifdef CONFIG_64BIT
 129 #define readq_relaxed(c)        ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
 130 #define writeq_relaxed(v, c)    ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
 131 #endif
 132
 133 /*
 134  * I/O memory access primitives. Reads are ordered relative to any
 135  * following Normal memory access. Writes are ordered relative to any prior
 136  * Normal memory access.  The memory barriers here are necessary as RISC-V
 137  * doesn't define any ordering between the memory space and the I/O space.
 138  */
 139 #define __io_br()       do {} while (0)
 140 #define __io_ar(v)      __asm__ __volatile__ ("fence i,r" : : : "memory")
 141 #define __io_bw()       __asm__ __volatile__ ("fence w,o" : : : "memory")
 142 #define __io_aw()       mmiowb_set_pending()
 143
 144 #define readb(c)        ({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
 145 #define readw(c)        ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
 146 #define readl(c)        ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
 147
 148 #define writeb(v, c)    ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
 149 #define writew(v, c)    ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
 150 #define writel(v, c)    ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
 151
 152 #ifdef CONFIG_64BIT
 153 #define readq(c)        ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
 154 #define writeq(v, c)    ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
 155 #endif
 156
 157 #endif /* _ASM_RISCV_MMIO_H */