arch/riscv/include/asm/mmio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
   4  *   which was based on arch/arm/include/io.h
   5  *
   6  * Copyright (C) 1996-2000 Russell King
   7  * Copyright (C) 2012 ARM Ltd.
   8  * Copyright (C) 2014 Regents of the University of California
   9  */
  10
  11 #ifndef _ASM_RISCV_MMIO_H
  12 #define _ASM_RISCV_MMIO_H
  13
  14 #include <linux/types.h>
  15 #include <asm/mmiowb.h>
  16
  17 #ifndef CONFIG_MMU
  18 #define pgprot_noncached(x)     (x)
  19 #endif /* CONFIG_MMU */
  20
  21 /* Generic IO read/write.  These perform native-endian accesses. */
  22 #define __raw_writeb __raw_writeb
  23 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  24 {
  25         asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
  26 }
  27
  28 #define __raw_writew __raw_writew
  29 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  30 {
  31         asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
  32 }
  33
  34 #define __raw_writel __raw_writel
  35 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  36 {
  37         asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  38 }
  39
  40 #ifdef CONFIG_64BIT
  41 #define __raw_writeq __raw_writeq
  42 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  43 {
  44         asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
  45 }
  46 #endif
  47
  48 #define __raw_readb __raw_readb
  49 static inline u8 __raw_readb(const volatile void __iomem *addr)
  50 {
  51         u8 val;
  52
  53         asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
  54         return val;
  55 }
  56
  57 #define __raw_readw __raw_readw
  58 static inline u16 __raw_readw(const volatile void __iomem *addr)
  59 {
  60         u16 val;
  61
  62         asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
  63         return val;
  64 }
  65
  66 #define __raw_readl __raw_readl
  67 static inline u32 __raw_readl(const volatile void __iomem *addr)
  68 {
  69         u32 val;
  70
  71         asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  72         return val;
  73 }
  74
  75 #ifdef CONFIG_64BIT
  76 #define __raw_readq __raw_readq
  77 static inline u64 __raw_readq(const volatile void __iomem *addr)
  78 {
  79         u64 val;
  80
  81         asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
  82         return val;
  83 }
  84 #endif
  85
  86 /*
  87  * Unordered I/O memory access primitives.  These are even more relaxed than
  88  * the relaxed versions, as they don't even order accesses between successive
  89  * operations to the I/O regions.
  90  */
  91 #define readb_cpu(c)            ({ u8  __r = __raw_readb(c); __r; })
  92 #define readw_cpu(c)            ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
  93 #define readl_cpu(c)            ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
  94
  95 #define writeb_cpu(v, c)        ((void)__raw_writeb((v), (c)))
  96 #define writew_cpu(v, c)        ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
  97 #define writel_cpu(v, c)        ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
  98
  99 #ifdef CONFIG_64BIT
 100 #define readq_cpu(c)            ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
 101 #define writeq_cpu(v, c)        ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
 102 #endif
 103
 104 /*
 105  * Relaxed I/O memory access primitives. These follow the Device memory
 106  * ordering rules but do not guarantee any ordering relative to Normal memory
 107  * accesses.  These are defined to order the indicated access (either a read or
 108  * write) with all other I/O memory accesses. Since the platform specification
 109  * defines that all I/O regions are strongly ordered on channel 2, no explicit
 110  * fences are required to enforce this ordering.
 111  */
 112 /* FIXME: These are now the same as asm-generic */
 113 #define __io_rbr()              do {} while (0)
 114 #define __io_rar()              do {} while (0)
 115 #define __io_rbw()              do {} while (0)
 116 #define __io_raw()              do {} while (0)
 117
 118 #define readb_relaxed(c)        ({ u8  __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
 119 #define readw_relaxed(c)        ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
 120 #define readl_relaxed(c)        ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
 121
 122 #define writeb_relaxed(v, c)    ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
 123 #define writew_relaxed(v, c)    ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
 124 #define writel_relaxed(v, c)    ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
 125
 126 #ifdef CONFIG_64BIT
 127 #define readq_relaxed(c)        ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
 128 #define writeq_relaxed(v, c)    ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
 129 #endif
 130
 131 /*
 132  * I/O memory access primitives. Reads are ordered relative to any
 133  * following Normal memory access. Writes are ordered relative to any prior
 134  * Normal memory access.  The memory barriers here are necessary as RISC-V
 135  * doesn't define any ordering between the memory space and the I/O space.
 136  */
 137 #define __io_br()       do {} while (0)
 138 #define __io_ar(v)      __asm__ __volatile__ ("fence i,r" : : : "memory")
 139 #define __io_bw()       __asm__ __volatile__ ("fence w,o" : : : "memory")
 140 #define __io_aw()       mmiowb_set_pending()
 141
 142 #define readb(c)        ({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
 143 #define readw(c)        ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
 144 #define readl(c)        ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
 145
 146 #define writeb(v, c)    ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
 147 #define writew(v, c)    ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
 148 #define writel(v, c)    ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
 149
 150 #ifdef CONFIG_64BIT
 151 #define readq(c)        ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
 152 #define writeq(v, c)    ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
 153 #endif
 154
 155 #endif /* _ASM_RISCV_MMIO_H */