arch/riscv/include/uapi/asm/hwprobe.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright 2023 Rivos, Inc
   4  */
   5
   6 #ifndef _UAPI_ASM_HWPROBE_H
   7 #define _UAPI_ASM_HWPROBE_H
   8
   9 #include <linux/types.h>
  10
  11 /*
  12  * Interface for probing hardware capabilities from userspace, see
  13  * Documentation/arch/riscv/hwprobe.rst for more information.
  14  */
  15 struct riscv_hwprobe {
  16         __s64 key;
  17         __u64 value;
  18 };
  19
  20 #define RISCV_HWPROBE_KEY_MVENDORID     0
  21 #define RISCV_HWPROBE_KEY_MARCHID       1
  22 #define RISCV_HWPROBE_KEY_MIMPID        2
  23 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
  24 #define         RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
  25 #define RISCV_HWPROBE_KEY_IMA_EXT_0     4
  26 #define         RISCV_HWPROBE_IMA_FD            (1 << 0)
  27 #define         RISCV_HWPROBE_IMA_C             (1 << 1)
  28 #define         RISCV_HWPROBE_IMA_V             (1 << 2)
  29 #define         RISCV_HWPROBE_EXT_ZBA           (1 << 3)
  30 #define         RISCV_HWPROBE_EXT_ZBB           (1 << 4)
  31 #define         RISCV_HWPROBE_EXT_ZBS           (1 << 5)
  32 #define         RISCV_HWPROBE_EXT_ZICBOZ        (1 << 6)
  33 #define RISCV_HWPROBE_KEY_CPUPERF_0     5
  34 #define         RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
  35 #define         RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
  36 #define         RISCV_HWPROBE_MISALIGNED_SLOW           (2 << 0)
  37 #define         RISCV_HWPROBE_MISALIGNED_FAST           (3 << 0)
  38 #define         RISCV_HWPROBE_MISALIGNED_UNSUPPORTED    (4 << 0)
  39 #define         RISCV_HWPROBE_MISALIGNED_MASK           (7 << 0)
  40 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE     6
  41 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
  42
  43 #endif