arch/sh/cpu/sh4/watchdog.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation; either version 2 of
   5  * the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  15  * MA 02111-1307 USA
  16  */
  17
  18 #include <common.h>
  19 #include <asm/processor.h>
  20 #include <asm/system.h>
  21 #include <asm/io.h>
  22
  23 #define WDT_BASE        WTCNT
  24
  25 #define WDT_WD          (1 << 6)
  26 #define WDT_RST_P       (0)
  27 #define WDT_RST_M       (1 << 5)
  28 #define WDT_ENABLE      (1 << 7)
  29
  30 #if defined(CONFIG_WATCHDOG)
  31 static unsigned char csr_read(void)
  32 {
  33         return inb(WDT_BASE + 0x04);
  34 }
  35
  36 static void cnt_write(unsigned char value)
  37 {
  38         outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
  39 }
  40
  41 static void csr_write(unsigned char value)
  42 {
  43         outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
  44 }
  45
  46 void watchdog_reset(void)
  47 {
  48         outl(0x55000000, WDT_BASE + 0x08);
  49 }
  50
  51 int watchdog_init(void)
  52 {
  53         /* Set overflow time*/
  54         cnt_write(0);
  55         /* Power on reset */
  56         csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
  57
  58         return 0;
  59 }
  60
  61 int watchdog_disable(void)
  62 {
  63         csr_write(csr_read() & ~WDT_ENABLE);
  64         return 0;
  65 }
  66 #endif
  67
  68 void reset_cpu(unsigned long ignored)
  69 {
  70         /* Address error with SR.BL=1 first. */
  71         trigger_address_error();
  72
  73         while (1)
  74                 ;
  75 }