arch/sh/include/asm/cpu_sh7723.h

   1 /*
   2  * (C) Copyright 2008 Renesas Solutions Corp.
   3  *
   4  * SH7723 Internal I/O register
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef _ASM_CPU_SH7723_H_
  23 #define _ASM_CPU_SH7723_H_
  24
  25 #define CACHE_OC_NUM_WAYS       4
  26 #define CCR_CACHE_INIT  0x0000090d
  27
  28 /* EXP */
  29 #define TRA             0xFF000020
  30 #define EXPEVT  0xFF000024
  31 #define INTEVT  0xFF000028
  32
  33 /* MMU */
  34 #define PTEH    0xFF000000
  35 #define PTEL    0xFF000004
  36 #define TTB             0xFF000008
  37 #define TEA             0xFF00000C
  38 #define MMUCR   0xFF000010
  39 #define PASCR   0xFF000070
  40 #define IRMCR   0xFF000078
  41
  42 /* CACHE */
  43 #define CCR             0xFF00001C
  44 #define RAMCR   0xFF000074
  45
  46 /* INTC */
  47
  48 /* BSC */
  49 #define CMNCR           0xFEC10000
  50 #define CS0BCR          0xFEC10004
  51 #define CS2BCR          0xFEC10008
  52 #define CS4BCR          0xFEC10010
  53 #define CS5ABCR         0xFEC10014
  54 #define CS5BBCR         0xFEC10018
  55 #define CS6ABCR         0xFEC1001C
  56 #define CS6BBCR         0xFEC10020
  57 #define CS0WCR          0xFEC10024
  58 #define CS2WCR          0xFEC10028
  59 #define CS4WCR          0xFEC10030
  60 #define CS5AWCR         0xFEC10034
  61 #define CS5BWCR         0xFEC10038
  62 #define CS6AWCR         0xFEC1003C
  63 #define CS6BWCR         0xFEC10040
  64 #define RBWTCNT         0xFEC10054
  65
  66 /* SBSC */
  67 #define SBSC_SDCR       0xFE400008
  68 #define SBSC_SDWCR      0xFE40000C
  69 #define SBSC_SDPCR      0xFE400010
  70 #define SBSC_RTCSR      0xFE400014
  71 #define SBSC_RTCNT      0xFE400018
  72 #define SBSC_RTCOR      0xFE40001C
  73 #define SBSC_RFCR       0xFE400020
  74
  75 /* DMAC */
  76
  77 /* CPG */
  78 #define FRQCR       0xA4150000
  79 #define VCLKCR      0xA4150004
  80 #define SCLKACR     0xA4150008
  81 #define SCLKBCR     0xA415000C
  82 #define IRDACLKCR   0xA4150018
  83 #define PLLCR       0xA4150024
  84 #define DLLFRQ      0xA4150050
  85
  86 /* LOW POWER MODE */
  87 #define STBCR       0xA4150020
  88 #define MSTPCR0     0xA4150030
  89 #define MSTPCR1     0xA4150034
  90 #define MSTPCR2     0xA4150038
  91
  92 /* RWDT */
  93 #define RWTCNT      0xA4520000
  94 #define RWTCSR      0xA4520004
  95 #define WTCNT           RWTCNT
  96
  97 /* TMU */
  98 #define TMU_BASE        0xFFD80000
  99
 100 /* TPU */
 101
 102 /* CMT */
 103 #define CMSTR       0xA44A0000
 104 #define CMCSR       0xA44A0060
 105 #define CMCNT       0xA44A0064
 106 #define CMCOR       0xA44A0068
 107
 108 /* MSIOF */
 109
 110 /* SCIF */
 111 #define SCIF0_BASE  0xFFE00000
 112 #define SCIF1_BASE  0xFFE10000
 113 #define SCIF2_BASE  0xFFE20000
 114 #define SCIF3_BASE  0xa4e30000
 115 #define SCIF4_BASE  0xa4e40000
 116 #define SCIF5_BASE  0xa4e50000
 117
 118 /* RTC */
 119 /* IrDA */
 120 /* KEYSC */
 121 /* USB */
 122 /* IIC */
 123 /* FLCTL */
 124 /* VPU */
 125 /* VIO(CEU) */
 126 /* VIO(VEU) */
 127 /* VIO(BEU) */
 128 /* 2DG */
 129 /* LCDC */
 130 /* VOU */
 131 /* TSIF */
 132 /* SIU */
 133 /* ATAPI */
 134
 135 /* PFC */
 136 #define PACR        0xA4050100
 137 #define PBCR        0xA4050102
 138 #define PCCR        0xA4050104
 139 #define PDCR        0xA4050106
 140 #define PECR        0xA4050108
 141 #define PFCR        0xA405010A
 142 #define PGCR        0xA405010C
 143 #define PHCR        0xA405010E
 144 #define PJCR        0xA4050110
 145 #define PKCR        0xA4050112
 146 #define PLCR        0xA4050114
 147 #define PMCR        0xA4050116
 148 #define PNCR        0xA4050118
 149 #define PQCR        0xA405011A
 150 #define PRCR        0xA405011C
 151 #define PSCR        0xA405011E
 152 #define PTCR        0xA4050140
 153 #define PUCR        0xA4050142
 154 #define PVCR        0xA4050144
 155 #define PWCR        0xA4050146
 156 #define PXCR        0xA4050148
 157 #define PYCR        0xA405014A
 158 #define PZCR        0xA405014C
 159 #define PSELA       0xA405014E
 160 #define PSELB       0xA4050150
 161 #define PSELC       0xA4050152
 162 #define PSELD       0xA4050154
 163 #define HIZCRA      0xA4050158
 164 #define HIZCRB      0xA405015A
 165 #define HIZCRC      0xA405015C
 166 #define HIZCRD      0xA405015E
 167 #define MSELCRA     0xA4050180
 168 #define MSELCRB     0xA4050182
 169 #define PULCR       0xA4050184
 170 #define DRVCRA      0xA405018A
 171 #define DRVCRB      0xA405018C
 172
 173 /* I/O Port */
 174 #define PADR        0xA4050120
 175 #define PBDR        0xA4050122
 176 #define PCDR        0xA4050124
 177 #define PDDR        0xA4050126
 178 #define PEDR        0xA4050128
 179 #define PFDR        0xA405012A
 180 #define PGDR        0xA405012C
 181 #define PHDR        0xA405012E
 182 #define PJDR        0xA4050130
 183 #define PKDR        0xA4050132
 184 #define PLDR        0xA4050134
 185 #define PMDR        0xA4050136
 186 #define PNDR        0xA4050138
 187 #define PQDR        0xA405013A
 188 #define PRDR        0xA405013C
 189 #define PSDR        0xA405013E
 190 #define PTDR        0xA4050160
 191 #define PUDR        0xA4050162
 192 #define PVDR        0xA4050164
 193 #define PWDR        0xA4050166
 194 #define PYDR        0xA4050168
 195 #define PZDR        0xA405016A
 196
 197 /* UBC */
 198 /* H-UDI */
 199
 200 #endif /* _ASM_CPU_SH7723_H_ */