arch/sparc/cpu/leon3/usb_uhci.h

   1 /*
   2  * (C) Copyright 2001
   3  * Denis Peter, MPL AG Switzerland
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Note: Part of this code has been derived from linux
  24  *
  25  */
  26 #ifndef _USB_UHCI_H_
  27 #define _USB_UHCI_H_
  28
  29 /* Command register */
  30 #define USBCMD          0
  31 #define   USBCMD_RS       0x0001        /* Run/Stop */
  32 #define   USBCMD_HCRESET  0x0002        /* Host reset */
  33 #define   USBCMD_GRESET   0x0004        /* Global reset */
  34 #define   USBCMD_EGSM     0x0008        /* Global Suspend Mode */
  35 #define   USBCMD_FGR      0x0010        /* Force Global Resume */
  36 #define   USBCMD_SWDBG    0x0020        /* SW Debug mode */
  37 #define   USBCMD_CF       0x0040        /* Config Flag (sw only) */
  38 #define   USBCMD_MAXP     0x0080        /* Max Packet (0 = 32, 1 = 64) */
  39
  40 /* Status register */
  41 #define USBSTS          2
  42 #define   USBSTS_USBINT   0x0001        /* Interrupt due to IOC */
  43 #define   USBSTS_ERROR    0x0002        /* Interrupt due to error */
  44 #define   USBSTS_RD       0x0004        /* Resume Detect */
  45 #define   USBSTS_HSE      0x0008        /* Host System Error - basically PCI problems */
  46 #define   USBSTS_HCPE     0x0010        /* Host Controller Process Error - the scripts were buggy */
  47 #define   USBSTS_HCH      0x0020        /* HC Halted */
  48
  49 /* Interrupt enable register */
  50 #define USBINTR         4
  51 #define   USBINTR_TIMEOUT 0x0001        /* Timeout/CRC error enable */
  52 #define   USBINTR_RESUME  0x0002        /* Resume interrupt enable */
  53 #define   USBINTR_IOC     0x0004        /* Interrupt On Complete enable */
  54 #define   USBINTR_SP      0x0008        /* Short packet interrupt enable */
  55
  56 #define USBFRNUM      6
  57 #define USBFLBASEADD  8
  58 #define USBSOF        12
  59
  60 /* USB port status and control registers */
  61 #define USBPORTSC1      16
  62 #define USBPORTSC2      18
  63 #define   USBPORTSC_CCS   0x0001        /* Current Connect Status ("device present") */
  64 #define   USBPORTSC_CSC   0x0002        /* Connect Status Change */
  65 #define   USBPORTSC_PE    0x0004        /* Port Enable */
  66 #define   USBPORTSC_PEC   0x0008        /* Port Enable Change */
  67 #define   USBPORTSC_LS    0x0030        /* Line Status */
  68 #define   USBPORTSC_RD    0x0040        /* Resume Detect */
  69 #define   USBPORTSC_LSDA  0x0100        /* Low Speed Device Attached */
  70 #define   USBPORTSC_PR    0x0200        /* Port Reset */
  71 #define   USBPORTSC_SUSP  0x1000        /* Suspend */
  72
  73 /* Legacy support register */
  74 #define USBLEGSUP 0xc0
  75 #define USBLEGSUP_DEFAULT 0x2000        /* only PIRQ enable set */
  76
  77 #define UHCI_NULL_DATA_SIZE 0x7ff       /* for UHCI controller TD */
  78 #define UHCI_PID            0xff        /* PID MASK */
  79
  80 #define UHCI_PTR_BITS       0x000F
  81 #define UHCI_PTR_TERM       0x0001
  82 #define UHCI_PTR_QH         0x0002
  83 #define UHCI_PTR_DEPTH      0x0004
  84
  85 /* for TD <status>: */
  86 #define TD_CTRL_SPD         (1 << 29)   /* Short Packet Detect */
  87 #define TD_CTRL_C_ERR_MASK  (3 << 27)   /* Error Counter bits */
  88 #define TD_CTRL_LS          (1 << 26)   /* Low Speed Device */
  89 #define TD_CTRL_IOS         (1 << 25)   /* Isochronous Select */
  90 #define TD_CTRL_IOC         (1 << 24)   /* Interrupt on Complete */
  91 #define TD_CTRL_ACTIVE      (1 << 23)   /* TD Active */
  92 #define TD_CTRL_STALLED     (1 << 22)   /* TD Stalled */
  93 #define TD_CTRL_DBUFERR     (1 << 21)   /* Data Buffer Error */
  94 #define TD_CTRL_BABBLE      (1 << 20)   /* Babble Detected */
  95 #define TD_CTRL_NAK         (1 << 19)   /* NAK Received */
  96 #define TD_CTRL_CRCTIMEO    (1 << 18)   /* CRC/Time Out Error */
  97 #define TD_CTRL_BITSTUFF    (1 << 17)   /* Bit Stuff Error */
  98 #define TD_CTRL_ACTLEN_MASK 0x7ff       /* actual length, encoded as n - 1 */
  99
 100 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 101                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
 102
 103 #define TD_TOKEN_TOGGLE         19
 104
 105 /* ------------------------------------------------------------------------------------
 106    Virtual Root HUB
 107    ------------------------------------------------------------------------------------ */
 108 /* destination of request */
 109 #define RH_INTERFACE               0x01
 110 #define RH_ENDPOINT                0x02
 111 #define RH_OTHER                   0x03
 112
 113 #define RH_CLASS                   0x20
 114 #define RH_VENDOR                  0x40
 115
 116 /* Requests: bRequest << 8 | bmRequestType */
 117 #define RH_GET_STATUS           0x0080
 118 #define RH_CLEAR_FEATURE        0x0100
 119 #define RH_SET_FEATURE          0x0300
 120 #define RH_SET_ADDRESS          0x0500
 121 #define RH_GET_DESCRIPTOR       0x0680
 122 #define RH_SET_DESCRIPTOR       0x0700
 123 #define RH_GET_CONFIGURATION    0x0880
 124 #define RH_SET_CONFIGURATION    0x0900
 125 #define RH_GET_STATE            0x0280
 126 #define RH_GET_INTERFACE        0x0A80
 127 #define RH_SET_INTERFACE        0x0B00
 128 #define RH_SYNC_FRAME           0x0C80
 129 /* Our Vendor Specific Request */
 130 #define RH_SET_EP               0x2000
 131
 132 /* Hub port features */
 133 #define RH_PORT_CONNECTION         0x00
 134 #define RH_PORT_ENABLE             0x01
 135 #define RH_PORT_SUSPEND            0x02
 136 #define RH_PORT_OVER_CURRENT       0x03
 137 #define RH_PORT_RESET              0x04
 138 #define RH_PORT_POWER              0x08
 139 #define RH_PORT_LOW_SPEED          0x09
 140 #define RH_C_PORT_CONNECTION       0x10
 141 #define RH_C_PORT_ENABLE           0x11
 142 #define RH_C_PORT_SUSPEND          0x12
 143 #define RH_C_PORT_OVER_CURRENT     0x13
 144 #define RH_C_PORT_RESET            0x14
 145
 146 /* Hub features */
 147 #define RH_C_HUB_LOCAL_POWER       0x00
 148 #define RH_C_HUB_OVER_CURRENT      0x01
 149
 150 #define RH_DEVICE_REMOTE_WAKEUP    0x00
 151 #define RH_ENDPOINT_STALL          0x01
 152
 153 /* Our Vendor Specific feature */
 154 #define RH_REMOVE_EP               0x00
 155
 156 #define RH_ACK                     0x01
 157 #define RH_REQ_ERR                 -1
 158 #define RH_NACK                    0x00
 159
 160 /* Transfer descriptor structure */
 161 typedef struct {
 162         unsigned long link;     /* next td/qh (LE) */
 163         unsigned long status;   /* status of the td */
 164         unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
 165         unsigned long buffer;   /* pointer to data buffer (LE) */
 166         unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
 167         unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
 168 } uhci_td_t, *puhci_td_t;
 169
 170 /* Queue Header structure */
 171 typedef struct {
 172         unsigned long head;     /* Next QH (LE) */
 173         unsigned long element;  /* Queue element pointer (LE) */
 174         unsigned long res[5];   /* reserved */
 175         unsigned long dev_ptr;  /* if 0 no tds have been assigned to this qh */
 176 } uhci_qh_t, *puhci_qh_t;
 177
 178 struct virt_root_hub {
 179         int devnum;             /* Address of Root Hub endpoint */
 180         int numports;           /* number of ports */
 181         int c_p_r[8];           /* C_PORT_RESET */
 182 };
 183
 184 #endif                          /* _USB_UHCI_H_ */