arch/sparc/include/asm/psr.h

   1 /* psr.h: This file holds the macros for masking off various parts of
   2  *        the processor status register on the Sparc. This is valid
   3  *        for Version 8. On the V9 this is renamed to the PSTATE
   4  *        register and its members are accessed as fields like
   5  *        PSTATE.PRIV for the current CPU privilege level.
   6  *
   7  * taken from the SPARC port of Linux,
   8  *
   9  * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
  10  * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __SPARC_PSR_H__
  16 #define __SPARC_PSR_H__
  17
  18 /* The Sparc PSR fields are laid out as the following:
  19  *
  20  *  ------------------------------------------------------------------------
  21  *  | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
  22  *  | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  23  *  ------------------------------------------------------------------------
  24  */
  25 #define PSR_CWP     0x0000001f  /* current window pointer     */
  26 #define PSR_ET      0x00000020  /* enable traps field         */
  27 #define PSR_PS      0x00000040  /* previous privilege level   */
  28 #define PSR_S       0x00000080  /* current privilege level    */
  29 #define PSR_PIL     0x00000f00  /* processor interrupt level  */
  30 #define PSR_EF      0x00001000  /* enable floating point      */
  31 #define PSR_EC      0x00002000  /* enable co-processor        */
  32 #define PSR_LE      0x00008000  /* SuperSparcII little-endian */
  33 #define PSR_ICC     0x00f00000  /* integer condition codes    */
  34 #define PSR_C       0x00100000  /* carry bit                  */
  35 #define PSR_V       0x00200000  /* overflow bit               */
  36 #define PSR_Z       0x00400000  /* zero bit                   */
  37 #define PSR_N       0x00800000  /* negative bit               */
  38 #define PSR_VERS    0x0f000000  /* cpu-version field          */
  39 #define PSR_IMPL    0xf0000000  /* cpu-implementation field   */
  40
  41 #define PSR_PIL_OFS  8
  42
  43 #ifndef __ASSEMBLY__
  44 /* Get the %psr register. */
  45 extern __inline__ unsigned int get_psr(void)
  46 {
  47         unsigned int psr;
  48         __asm__ __volatile__("rd        %%psr, %0\n\t"
  49                              "nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr)
  50                              :  /* no inputs */
  51                              :"memory");
  52
  53         return psr;
  54 }
  55
  56 extern __inline__ void put_psr(unsigned int new_psr)
  57 {
  58         __asm__ __volatile__("wr        %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t":      /* no outputs */
  59                              :"r"(new_psr)
  60                              :"memory", "cc");
  61 }
  62
  63 /* Get the %fsr register.  Be careful, make sure the floating point
  64  * enable bit is set in the %psr when you execute this or you will
  65  * incur a trap.
  66  */
  67
  68 extern unsigned int fsr_storage;
  69
  70 extern __inline__ unsigned int get_fsr(void)
  71 {
  72         unsigned int fsr = 0;
  73
  74         __asm__ __volatile__("st        %%fsr, %1\n\t"
  75                              "ld        %1, %0\n\t":"=r"(fsr)
  76                              :"m"(fsr_storage));
  77
  78         return fsr;
  79 }
  80
  81 #endif                          /* !(__ASSEMBLY__) */
  82
  83 #endif                          /* !(__SPARC_PSR_H__) */