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1 /* SPARC stack layout Macros and structures,
2 * mainly taken from BCC (the Bare C compiler for
3 * SPARC LEON2/3) sources.
4 *
5 * (C) Copyright 2007
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __SPARC_STACK_H__
12 #define __SPARC_STACK_H__
13
14 #include <asm/ptrace.h>
15
16 #ifndef __ASSEMBLER__
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 #define PT_REGS_SZ sizeof(struct pt_regs)
23
24 /* A Sparc stack frame */
25 struct sparc_stackframe_regs {
26 unsigned long sf_locals[8];
27 unsigned long sf_ins[6];
28 struct sparc_stackframe_regs *sf_fp;
29 unsigned long sf_callers_pc;
30 char *sf_structptr;
31 unsigned long sf_xargs[6];
32 unsigned long sf_xxargs[1];
33 };
34 #define SF_REGS_SZ sizeof(struct sparc_stackframe_regs)
35
36 /* A register window */
37 struct sparc_regwindow_regs {
38 unsigned long locals[8];
39 unsigned long ins[8];
40 };
41 #define RW_REGS_SZ sizeof(struct sparc_regwindow_regs)
42
43 /* A fpu window */
44 struct sparc_fpuwindow_regs {
45 unsigned long locals[32];
46 unsigned long fsr;
47 unsigned long lastctx;
48 };
49 #define FW_REGS_SZ sizeof(struct sparc_fpuwindow_regs)
50
51 #ifdef __cplusplus
52 }
53 #endif
54 #else
55 #define PT_REGS_SZ 0x50 /* 20*4 */
56 #define SF_REGS_SZ 0x60 /* 24*4 */
57 #define RW_REGS_SZ 0x20 /* 16*4 */
58 #define FW_REGS_SZ 0x88 /* 34*4 */
59 #endif /* !ASM */
60
61 /* These are for pt_regs. */
62 #define PT_PSR 0x0
63 #define PT_PC 0x4
64 #define PT_NPC 0x8
65 #define PT_Y 0xc
66 #define PT_G0 0x10
67 #define PT_WIM PT_G0
68 #define PT_G1 0x14
69 #define PT_G2 0x18
70 #define PT_G3 0x1c
71 #define PT_G4 0x20
72 #define PT_G5 0x24
73 #define PT_G6 0x28
74 #define PT_G7 0x2c
75 #define PT_I0 0x30
76 #define PT_I1 0x34
77 #define PT_I2 0x38
78 #define PT_I3 0x3c
79 #define PT_I4 0x40
80 #define PT_I5 0x44
81 #define PT_I6 0x48
82 #define PT_FP PT_I6
83 #define PT_I7 0x4c
84
85 /* Stack_frame offsets */
86 #define SF_L0 0x00
87 #define SF_L1 0x04
88 #define SF_L2 0x08
89 #define SF_L3 0x0c
90 #define SF_L4 0x10
91 #define SF_L5 0x14
92 #define SF_L6 0x18
93 #define SF_L7 0x1c
94 #define SF_I0 0x20
95 #define SF_I1 0x24
96 #define SF_I2 0x28
97 #define SF_I3 0x2c
98 #define SF_I4 0x30
99 #define SF_I5 0x34
100 #define SF_FP 0x38
101 #define SF_PC 0x3c
102 #define SF_RETP 0x40
103 #define SF_XARG0 0x44
104 #define SF_XARG1 0x48
105 #define SF_XARG2 0x4c
106 #define SF_XARG3 0x50
107 #define SF_XARG4 0x54
108 #define SF_XARG5 0x58
109 #define SF_XXARG 0x5c
110
111 /* Reg_window offsets */
112 #define RW_L0 0x00
113 #define RW_L1 0x04
114 #define RW_L2 0x08
115 #define RW_L3 0x0c
116 #define RW_L4 0x10
117 #define RW_L5 0x14
118 #define RW_L6 0x18
119 #define RW_L7 0x1c
120 #define RW_I0 0x20
121 #define RW_I1 0x24
122 #define RW_I2 0x28
123 #define RW_I3 0x2c
124 #define RW_I4 0x30
125 #define RW_I5 0x34
126 #define RW_I6 0x38
127 #define RW_I7 0x3c
128
129 /* Fpu_window offsets */
130 #define FW_F0 0x00
131 #define FW_F2 0x08
132 #define FW_F4 0x10
133 #define FW_F6 0x18
134 #define FW_F8 0x20
135 #define FW_F10 0x28
136 #define FW_F12 0x30
137 #define FW_F14 0x38
138 #define FW_F16 0x40
139 #define FW_F18 0x48
140 #define FW_F20 0x50
141 #define FW_F22 0x58
142 #define FW_F24 0x60
143 #define FW_F26 0x68
144 #define FW_F28 0x70
145 #define FW_F30 0x78
146 #define FW_FSR 0x80
147
148 #endif