arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Run U-Boot in 32/64-bit mode"
   9         default X86_RUN_32BIT
  10         help
  11           U-Boot can be built as a 32-bit binary which runs in 32-bit mode
  12           even on 64-bit machines. In this case SPL is not used, and U-Boot
  13           runs directly from the reset vector (via 16-bit start-up).
  14
  15           Alternatively it can be run as a 64-bit binary, thus requiring a
  16           64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
  17           start-up) then jumps to U-Boot in 64-bit mode.
  18
  19           For now, 32-bit mode is recommended, as 64-bit is still
  20           experimental and is missing a lot of features.
  21
  22 config X86_RUN_32BIT
  23         bool "32-bit"
  24         help
  25           Build U-Boot as a 32-bit binary with no SPL. This is the currently
  26           supported normal setup. U-Boot will stay in 32-bit mode even on
  27           64-bit machines. When booting a 64-bit kernel, U-Boot will switch
  28           to 64-bit just before starting the kernel. Only the bottom 4GB of
  29           memory can be accessed through normal means, although
  30           arch_phys_memset() can be used for basic access to other memory.
  31
  32 config X86_RUN_64BIT
  33         bool "64-bit"
  34         select X86_64
  35         select SPL
  36         select SPL_SEPARATE_BSS
  37         help
  38           Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
  39           experimental and many features are missing. U-Boot SPL starts up,
  40           runs through the 16-bit and 32-bit init, then switches to 64-bit
  41           mode and jumps to U-Boot proper.
  42
  43 endchoice
  44
  45 config X86_64
  46         bool
  47
  48 config SPL_X86_64
  49         bool
  50         depends on SPL
  51
  52 choice
  53         prompt "Mainboard vendor"
  54         default VENDOR_EMULATION
  55
  56 config VENDOR_ADVANTECH
  57         bool "advantech"
  58
  59 config VENDOR_CONGATEC
  60         bool "congatec"
  61
  62 config VENDOR_COREBOOT
  63         bool "coreboot"
  64
  65 config VENDOR_DFI
  66         bool "dfi"
  67
  68 config VENDOR_EFI
  69         bool "efi"
  70
  71 config VENDOR_EMULATION
  72         bool "emulation"
  73
  74 config VENDOR_GOOGLE
  75         bool "Google"
  76
  77 config VENDOR_INTEL
  78         bool "Intel"
  79
  80 endchoice
  81
  82 # subarchitectures-specific options below
  83 config INTEL_MID
  84         bool "Intel MID platform support"
  85         select REGMAP
  86         select SYSCON
  87         help
  88           Select to build a U-Boot capable of supporting Intel MID
  89           (Mobile Internet Device) platform systems which do not have
  90           the PCI legacy interfaces.
  91
  92           If you are building for a PC class system say N here.
  93
  94           Intel MID platforms are based on an Intel processor and
  95           chipset which consume less power than most of the x86
  96           derivatives.
  97
  98 # board-specific options below
  99 source "board/advantech/Kconfig"
 100 source "board/congatec/Kconfig"
 101 source "board/coreboot/Kconfig"
 102 source "board/dfi/Kconfig"
 103 source "board/efi/Kconfig"
 104 source "board/emulation/Kconfig"
 105 source "board/google/Kconfig"
 106 source "board/intel/Kconfig"
 107
 108 # platform-specific options below
 109 source "arch/x86/cpu/apollolake/Kconfig"
 110 source "arch/x86/cpu/baytrail/Kconfig"
 111 source "arch/x86/cpu/braswell/Kconfig"
 112 source "arch/x86/cpu/broadwell/Kconfig"
 113 source "arch/x86/cpu/coreboot/Kconfig"
 114 source "arch/x86/cpu/ivybridge/Kconfig"
 115 source "arch/x86/cpu/efi/Kconfig"
 116 source "arch/x86/cpu/qemu/Kconfig"
 117 source "arch/x86/cpu/quark/Kconfig"
 118 source "arch/x86/cpu/queensbay/Kconfig"
 119 source "arch/x86/cpu/slimbootloader/Kconfig"
 120 source "arch/x86/cpu/tangier/Kconfig"
 121
 122 # architecture-specific options below
 123
 124 config AHCI
 125         default y
 126
 127 config SYS_MALLOC_F_LEN
 128         default 0x800
 129
 130 config RAMBASE
 131         hex
 132         default 0x100000
 133
 134 config XIP_ROM_SIZE
 135         hex
 136         depends on X86_RESET_VECTOR
 137         default ROM_SIZE
 138
 139 config CPU_ADDR_BITS
 140         int
 141         default 36
 142
 143 config HPET_ADDRESS
 144         hex
 145         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
 146
 147 config SMM_TSEG
 148         bool
 149
 150 config SMM_TSEG_SIZE
 151         hex
 152
 153 config X86_RESET_VECTOR
 154         bool
 155         select BINMAN
 156
 157 # The following options control where the 16-bit and 32-bit init lies
 158 # If SPL is enabled then it normally holds this init code, and U-Boot proper
 159 # is normally a 64-bit build.
 160 #
 161 # The 16-bit init refers to the reset vector and the small amount of code to
 162 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
 163 # or missing altogether if U-Boot is started from EFI or coreboot.
 164 #
 165 # The 32-bit init refers to processor init, running binary blobs including
 166 # FSP, setting up interrupts and anything else that needs to be done in
 167 # 32-bit code. It is normally in the same place as 16-bit init if that is
 168 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
 169 config X86_16BIT_INIT
 170         bool
 171         depends on X86_RESET_VECTOR
 172         default y if X86_RESET_VECTOR && !SPL
 173         help
 174           This is enabled when 16-bit init is in U-Boot proper
 175
 176 config SPL_X86_16BIT_INIT
 177         bool
 178         depends on X86_RESET_VECTOR
 179         default y if X86_RESET_VECTOR && SPL && !TPL
 180         help
 181           This is enabled when 16-bit init is in SPL
 182
 183 config TPL_X86_16BIT_INIT
 184         bool
 185         depends on X86_RESET_VECTOR
 186         default y if X86_RESET_VECTOR && TPL
 187         help
 188           This is enabled when 16-bit init is in TPL
 189
 190 config X86_32BIT_INIT
 191         bool
 192         depends on X86_RESET_VECTOR
 193         default y if X86_RESET_VECTOR && !SPL
 194         help
 195           This is enabled when 32-bit init is in U-Boot proper
 196
 197 config SPL_X86_32BIT_INIT
 198         bool
 199         depends on X86_RESET_VECTOR
 200         default y if X86_RESET_VECTOR && SPL
 201         help
 202           This is enabled when 32-bit init is in SPL
 203
 204 config USE_EARLY_BOARD_INIT
 205         bool
 206
 207 config RESET_SEG_START
 208         hex
 209         depends on X86_RESET_VECTOR
 210         default 0xffff0000
 211
 212 config RESET_VEC_LOC
 213         hex
 214         depends on X86_RESET_VECTOR
 215         default 0xfffffff0
 216
 217 config SYS_X86_START16
 218         hex
 219         depends on X86_RESET_VECTOR
 220         default 0xfffff800
 221
 222 config HAVE_X86_FIT
 223         bool
 224         help
 225           Enable inclusion of an Intel Firmware Interface Table (FIT) into the
 226           image. This table is supposed to point to microcode and the like. So
 227           far it is just a fixed table with the minimum set of headers, so that
 228           it is actually present.
 229
 230 config X86_LOAD_FROM_32_BIT
 231         bool "Boot from a 32-bit program"
 232         help
 233           Define this to boot U-Boot from a 32-bit program which sets
 234           the GDT differently. This can be used to boot directly from
 235           any stage of coreboot, for example, bypassing the normal
 236           payload-loading feature.
 237
 238 config BOARD_ROMSIZE_KB_512
 239         bool
 240 config BOARD_ROMSIZE_KB_1024
 241         bool
 242 config BOARD_ROMSIZE_KB_2048
 243         bool
 244 config BOARD_ROMSIZE_KB_4096
 245         bool
 246 config BOARD_ROMSIZE_KB_8192
 247         bool
 248 config BOARD_ROMSIZE_KB_16384
 249         bool
 250
 251 choice
 252         prompt "ROM chip size"
 253         depends on X86_RESET_VECTOR
 254         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 255         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 256         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 257         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 258         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 259         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 260         help
 261           Select the size of the ROM chip you intend to flash U-Boot on.
 262
 263           The build system will take care of creating a u-boot.rom file
 264           of the matching size.
 265
 266 config UBOOT_ROMSIZE_KB_512
 267         bool "512 KB"
 268         help
 269           Choose this option if you have a 512 KB ROM chip.
 270
 271 config UBOOT_ROMSIZE_KB_1024
 272         bool "1024 KB (1 MB)"
 273         help
 274           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 275
 276 config UBOOT_ROMSIZE_KB_2048
 277         bool "2048 KB (2 MB)"
 278         help
 279           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 280
 281 config UBOOT_ROMSIZE_KB_4096
 282         bool "4096 KB (4 MB)"
 283         help
 284           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 285
 286 config UBOOT_ROMSIZE_KB_8192
 287         bool "8192 KB (8 MB)"
 288         help
 289           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 290
 291 config UBOOT_ROMSIZE_KB_16384
 292         bool "16384 KB (16 MB)"
 293         help
 294           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 295
 296 endchoice
 297
 298 # Map the config names to an integer (KB).
 299 config UBOOT_ROMSIZE_KB
 300         int
 301         default 512 if UBOOT_ROMSIZE_KB_512
 302         default 1024 if UBOOT_ROMSIZE_KB_1024
 303         default 2048 if UBOOT_ROMSIZE_KB_2048
 304         default 4096 if UBOOT_ROMSIZE_KB_4096
 305         default 8192 if UBOOT_ROMSIZE_KB_8192
 306         default 16384 if UBOOT_ROMSIZE_KB_16384
 307
 308 # Map the config names to a hex value (bytes).
 309 config ROM_SIZE
 310         hex
 311         default 0x80000 if UBOOT_ROMSIZE_KB_512
 312         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 313         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 314         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 315         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 316         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 317         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 318
 319 config HAVE_INTEL_ME
 320         bool "Platform requires Intel Management Engine"
 321         help
 322           Newer higher-end devices have an Intel Management Engine (ME)
 323           which is a very large binary blob (typically 1.5MB) which is
 324           required for the platform to work. This enforces a particular
 325           SPI flash format. You will need to supply the me.bin file in
 326           your board directory.
 327
 328 config X86_RAMTEST
 329         bool "Perform a simple RAM test after SDRAM initialisation"
 330         help
 331           If there is something wrong with SDRAM then the platform will
 332           often crash within U-Boot or the kernel. This option enables a
 333           very simple RAM test that quickly checks whether the SDRAM seems
 334           to work correctly. It is not exhaustive but can save time by
 335           detecting obvious failures.
 336
 337 config FLASH_DESCRIPTOR_FILE
 338         string "Flash descriptor binary filename"
 339         depends on HAVE_INTEL_ME || FSP_VERSION2
 340         default "descriptor.bin"
 341         help
 342           The filename of the file to use as flash descriptor in the
 343           board directory.
 344
 345 config INTEL_ME_FILE
 346         string "Intel Management Engine binary filename"
 347         depends on HAVE_INTEL_ME
 348         default "me.bin"
 349         help
 350           The filename of the file to use as Intel Management Engine in the
 351           board directory.
 352
 353 config USE_HOB
 354         bool "Use HOB (Hand-Off Block)"
 355         help
 356           Select this option to access HOB (Hand-Off Block) data structures
 357           and parse HOBs. This HOB infra structure can be reused with
 358           different solutions across different platforms.
 359
 360 config HAVE_FSP
 361         bool "Add an Firmware Support Package binary"
 362         depends on !EFI
 363         select USE_HOB
 364         select HAS_ROM
 365         help
 366           Select this option to add an Firmware Support Package binary to
 367           the resulting U-Boot image. It is a binary blob which U-Boot uses
 368           to set up SDRAM and other chipset specific initialization.
 369
 370           Note: Without this binary U-Boot will not be able to set up its
 371           SDRAM so will not boot.
 372
 373 config USE_CAR
 374         bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
 375         default y if !HAVE_FSP
 376         help
 377           Select this option if your board uses CAR init code, typically in a
 378           car.S file, to get some initial memory for code execution. This is
 379           common with Intel CPUs which don't use FSP.
 380
 381 choice
 382         prompt "FSP version"
 383         depends on HAVE_FSP
 384         default FSP_VERSION1
 385         help
 386           Selects the FSP version to use. Intel has published several versions
 387           of the FSP External Architecture Specification and this allows
 388           selection of the version number used by a particular SoC.
 389
 390 config FSP_VERSION1
 391         bool "FSP version 1.x"
 392         help
 393           This covers versions 1.0 and 1.1a. See here for details:
 394           https://github.com/IntelFsp/fsp/wiki
 395
 396 config FSP_VERSION2
 397         bool "FSP version 2.x"
 398         help
 399           This covers versions 2.0 and 2.1. See here for details:
 400           https://github.com/IntelFsp/fsp/wiki
 401
 402 endchoice
 403
 404 config FSP_FILE
 405         string "Firmware Support Package binary filename"
 406         depends on FSP_VERSION1
 407         default "fsp.bin"
 408         help
 409           The filename of the file to use as Firmware Support Package binary
 410           in the board directory.
 411
 412 config FSP_ADDR
 413         hex "Firmware Support Package binary location"
 414         depends on FSP_VERSION1
 415         default 0xfffc0000
 416         help
 417           FSP is not Position Independent Code (PIC) and the whole FSP has to
 418           be rebased if it is placed at a location which is different from the
 419           perferred base address specified during the FSP build. Use Intel's
 420           Binary Configuration Tool (BCT) to do the rebase.
 421
 422           The default base address of 0xfffc0000 indicates that the binary must
 423           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 424
 425 if FSP_VERSION2
 426
 427 config FSP_FILE_T
 428         string "Firmware Support Package binary filename (Temp RAM)"
 429         default "fsp_t.bin"
 430         help
 431           The filename of the file to use for the temporary-RAM init phase from
 432           the Firmware Support Package binary. Put this in the board directory.
 433           It is used to set up an initial area of RAM which can be used for the
 434           stack and other purposes, while bringing up the main system DRAM.
 435
 436 config FSP_ADDR_T
 437         hex "Firmware Support Package binary location (Temp RAM)"
 438         default 0xffff8000
 439         help
 440           FSP is not Position-Independent Code (PIC) and FSP components have to
 441           be rebased if placed at a location which is different from the
 442           perferred base address specified during the FSP build. Use Intel's
 443           Binary Configuration Tool (BCT) to do the rebase.
 444
 445 config FSP_FILE_M
 446         string "Firmware Support Package binary filename (Memory Init)"
 447         default "fsp_m.bin"
 448         help
 449           The filename of the file to use for the RAM init phase from the
 450           Firmware Support Package binary. Put this in the board directory.
 451           It is used to set up the main system DRAM and runs in SPL, once
 452           temporary RAM (CAR) is working.
 453
 454 config FSP_FILE_S
 455         string "Firmware Support Package binary filename (Silicon Init)"
 456         default "fsp_s.bin"
 457         help
 458           The filename of the file to use for the Silicon init phase from the
 459           Firmware Support Package binary. Put this in the board directory.
 460           It is used to set up the silicon to work correctly and must be
 461           executed after DRAM is running.
 462
 463 config IFWI_INPUT_FILE
 464         string "Filename containing FIT (Firmware Interface Table) with IFWI"
 465         default "fitimage.bin"
 466         help
 467           The IFWI is obtained by running a tool on this file to extract the
 468           IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
 469           microcode and other internal items.
 470
 471 endif
 472
 473 config FSP_TEMP_RAM_ADDR
 474         hex
 475         depends on FSP_VERSION1
 476         default 0x2000000
 477         help
 478           Stack top address which is used in fsp_init() after DRAM is ready and
 479           CAR is disabled.
 480
 481 config FSP_SYS_MALLOC_F_LEN
 482         hex
 483         depends on FSP_VERSION1
 484         default 0x100000
 485         help
 486           Additional size of malloc() pool before relocation.
 487
 488 config FSP_USE_UPD
 489         bool
 490         depends on FSP_VERSION1
 491         default y if !NORTHBRIDGE_INTEL_IVYBRIDGE
 492         help
 493           Most FSPs use UPD data region for some FSP customization. But there
 494           are still some FSPs that might not even have UPD. For such FSPs,
 495           override this to n in their platform Kconfig files.
 496
 497 config FSP_BROKEN_HOB
 498         bool
 499         depends on FSP_VERSION1
 500         help
 501           Indicate some buggy FSPs that does not report memory used by FSP
 502           itself as reserved in the resource descriptor HOB. Select this to
 503           tell U-Boot to do some additional work to ensure U-Boot relocation
 504           do not overwrite the important boot service data which is used by
 505           FSP, otherwise the subsequent call to fsp_notify() will fail.
 506
 507 config ENABLE_MRC_CACHE
 508         bool "Enable MRC cache"
 509         depends on !EFI && !SYS_COREBOOT
 510         help
 511           Enable this feature to cause MRC data to be cached in NV storage
 512           to be used for speeding up boot time on future reboots and/or
 513           power cycles.
 514
 515           For platforms that use Intel FSP for the memory initialization,
 516           please check FSP output HOB via U-Boot command 'fsp hob' to see
 517           if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
 518           If such GUID does not exist, MRC cache is not available on such
 519           platform (eg: Intel Queensbay), which means selecting this option
 520           here does not make any difference.
 521
 522 config HAVE_MRC
 523         bool "Add a System Agent binary"
 524         select HAS_ROM
 525         depends on !HAVE_FSP
 526         help
 527           Select this option to add a System Agent binary to
 528           the resulting U-Boot image. MRC stands for Memory Reference Code.
 529           It is a binary blob which U-Boot uses to set up SDRAM.
 530
 531           Note: Without this binary U-Boot will not be able to set up its
 532           SDRAM so will not boot.
 533
 534 config CACHE_MRC_BIN
 535         bool
 536         depends on HAVE_MRC
 537         help
 538           Enable caching for the memory reference code binary. This uses an
 539           MTRR (memory type range register) to turn on caching for the section
 540           of SPI flash that contains the memory reference code. This makes
 541           SDRAM init run faster.
 542
 543 config CACHE_MRC_SIZE_KB
 544         int
 545         depends on HAVE_MRC
 546         default 512
 547         help
 548           Sets the size of the cached area for the memory reference code.
 549           This ends at the end of SPI flash (address 0xffffffff) and is
 550           measured in KB. Typically this is set to 512, providing for 0.5MB
 551           of cached space.
 552
 553 config DCACHE_RAM_BASE
 554         hex
 555         depends on HAVE_MRC
 556         help
 557           Sets the base of the data cache area in memory space. This is the
 558           start address of the cache-as-RAM (CAR) area and the address varies
 559           depending on the CPU. Once CAR is set up, read/write memory becomes
 560           available at this address and can be used temporarily until SDRAM
 561           is working.
 562
 563 config DCACHE_RAM_SIZE
 564         hex
 565         depends on HAVE_MRC
 566         default 0x40000
 567         help
 568           Sets the total size of the data cache area in memory space. This
 569           sets the size of the cache-as-RAM (CAR) area. Note that much of the
 570           CAR space is required by the MRC. The CAR space available to U-Boot
 571           is normally at the start and typically extends to 1/4 or 1/2 of the
 572           available size.
 573
 574 config DCACHE_RAM_MRC_VAR_SIZE
 575         hex
 576         depends on HAVE_MRC
 577         help
 578           This is the amount of CAR (Cache as RAM) reserved for use by the
 579           memory reference code. This depends on the implementation of the
 580           memory reference code and must be set correctly or the board will
 581           not boot.
 582
 583 config HAVE_REFCODE
 584         bool "Add a Reference Code binary"
 585         help
 586           Select this option to add a Reference Code binary to the resulting
 587           U-Boot image. This is an Intel binary blob that handles system
 588           initialisation, in this case the PCH and System Agent.
 589
 590           Note: Without this binary (on platforms that need it such as
 591           broadwell) U-Boot will be missing some critical setup steps.
 592           Various peripherals may fail to work.
 593
 594 config HAVE_MICROCODE
 595         bool "Board requires a microcode binary"
 596         default y if !FSP_VERSION2
 597         help
 598           Enable this if the board requires microcode to be loaded on boot.
 599           Typically this is handed by the FSP for modern boards, but for
 600           some older boards, it must be programmed by U-Boot, and that form
 601           part of the image.
 602
 603 config SMP
 604         bool "Enable Symmetric Multiprocessing"
 605         help
 606           Enable use of more than one CPU in U-Boot and the Operating System
 607           when loaded. Each CPU will be started up and information can be
 608           obtained using the 'cpu' command. If this option is disabled, then
 609           only one CPU will be enabled regardless of the number of CPUs
 610           available.
 611
 612 config SMP_AP_WORK
 613         bool
 614         depends on SMP
 615         help
 616          Allow APs to do other work after initialisation instead of going
 617          to sleep.
 618
 619 config MAX_CPUS
 620         int "Maximum number of CPUs permitted"
 621         depends on SMP
 622         default 4
 623         help
 624           When using multi-CPU chips it is possible for U-Boot to start up
 625           more than one CPU. The stack memory used by all of these CPUs is
 626           pre-allocated so at present U-Boot wants to know the maximum
 627           number of CPUs that may be present. Set this to at least as high
 628           as the number of CPUs in your system (it uses about 4KB of RAM for
 629           each CPU).
 630
 631 config AP_STACK_SIZE
 632         hex
 633         depends on SMP
 634         default 0x1000
 635         help
 636           Each additional CPU started by U-Boot requires its own stack. This
 637           option sets the stack size used by each CPU and directly affects
 638           the memory used by this initialisation process. Typically 4KB is
 639           enough space.
 640
 641 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 642         bool
 643         help
 644           This option indicates that the turbo mode setting is not package
 645           scoped. i.e. turbo_enable() needs to be called on not just the
 646           bootstrap processor (BSP).
 647
 648 config HAVE_VGA_BIOS
 649         bool "Add a VGA BIOS image"
 650         help
 651           Select this option if you have a VGA BIOS image that you would
 652           like to add to your ROM.
 653
 654 config VGA_BIOS_FILE
 655         string "VGA BIOS image filename"
 656         depends on HAVE_VGA_BIOS
 657         default "vga.bin"
 658         help
 659           The filename of the VGA BIOS image in the board directory.
 660
 661 config VGA_BIOS_ADDR
 662         hex "VGA BIOS image location"
 663         depends on HAVE_VGA_BIOS
 664         default 0xfff90000
 665         help
 666           The location of VGA BIOS image in the SPI flash. For example, base
 667           address of 0xfff90000 indicates that the image will be put at offset
 668           0x90000 from the beginning of a 1MB flash device.
 669
 670 config HAVE_VBT
 671         bool "Add a Video BIOS Table (VBT) image"
 672         depends on HAVE_FSP
 673         help
 674           Select this option if you have a Video BIOS Table (VBT) image that
 675           you would like to add to your ROM. This is normally required if you
 676           are using an Intel FSP firmware that is complaint with spec 1.1 or
 677           later to initialize the integrated graphics device (IGD).
 678
 679           Video BIOS Table, or VBT, provides platform and board specific
 680           configuration information to the driver that is not discoverable
 681           or available through other means. By other means the most used
 682           method here is to read EDID table from the attached monitor, over
 683           Display Data Channel (DDC) using two pin I2C serial interface. VBT
 684           configuration is related to display hardware and is available via
 685           the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
 686
 687 config VBT_FILE
 688         string "Video BIOS Table (VBT) image filename"
 689         depends on HAVE_VBT
 690         default "vbt.bin"
 691         help
 692           The filename of the file to use as Video BIOS Table (VBT) image
 693           in the board directory.
 694
 695 config VBT_ADDR
 696         hex "Video BIOS Table (VBT) image location"
 697         depends on HAVE_VBT
 698         default 0xfff90000
 699         help
 700           The location of Video BIOS Table (VBT) image in the SPI flash. For
 701           example, base address of 0xfff90000 indicates that the image will
 702           be put at offset 0x90000 from the beginning of a 1MB flash device.
 703
 704 config VIDEO_FSP
 705         bool "Enable FSP framebuffer driver support"
 706         depends on HAVE_VBT && VIDEO
 707         help
 708           Turn on this option to enable a framebuffer driver when U-Boot is
 709           using Video BIOS Table (VBT) image for FSP firmware to initialize
 710           the integrated graphics device.
 711
 712 config ROM_TABLE_ADDR
 713         hex
 714         default 0xf0000
 715         help
 716           All x86 tables happen to like the address range from 0x0f0000
 717           to 0x100000. We use 0xf0000 as the starting address to store
 718           those tables, including PIRQ routing table, Multi-Processor
 719           table and ACPI table.
 720
 721 config ROM_TABLE_SIZE
 722         hex
 723         default 0x10000
 724
 725 config HAVE_ITSS
 726         bool "Enable ITSS"
 727         help
 728           Select this to include the driver for the Interrupt Timer
 729           Subsystem (ITSS) which is found on several Intel devices.
 730
 731 config HAVE_P2SB
 732         bool "Enable P2SB"
 733         depends on P2SB
 734         help
 735           Select this to include the driver for the Primary to
 736           Sideband Bridge (P2SB) which is found on several Intel
 737           devices.
 738
 739 menu "System tables"
 740         depends on !EFI && !SYS_COREBOOT
 741
 742 config GENERATE_PIRQ_TABLE
 743         bool "Generate a PIRQ table"
 744         help
 745           Generate a PIRQ routing table for this board. The PIRQ routing table
 746           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 747           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 748           It specifies the interrupt router information as well how all the PCI
 749           devices' interrupt pins are wired to PIRQs.
 750
 751 config GENERATE_SFI_TABLE
 752         bool "Generate a SFI (Simple Firmware Interface) table"
 753         help
 754           The Simple Firmware Interface (SFI) provides a lightweight method
 755           for platform firmware to pass information to the operating system
 756           via static tables in memory.  Kernel SFI support is required to
 757           boot on SFI-only platforms.  If you have ACPI tables then these are
 758           used instead.
 759
 760           U-Boot writes this table in write_sfi_table() just before booting
 761           the OS.
 762
 763           For more information, see http://simplefirmware.org
 764
 765 config GENERATE_MP_TABLE
 766         bool "Generate an MP (Multi-Processor) table"
 767         help
 768           Generate an MP (Multi-Processor) table for this board. The MP table
 769           provides a way for the operating system to support for symmetric
 770           multiprocessing as well as symmetric I/O interrupt handling with
 771           the local APIC and I/O APIC.
 772
 773 config ACPI_GNVS_EXTERNAL
 774         bool
 775         help
 776           Put the GNVS (Global Non-Volatile Sleeping) table separate from the
 777           DSDT and add a pointer to the table from the DSDT. This allows
 778           U-Boot to better control the address of the GNVS.
 779
 780 endmenu
 781
 782 config HAVE_ACPI_RESUME
 783         bool "Enable ACPI S3 resume"
 784         select ENABLE_MRC_CACHE
 785         help
 786           Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
 787           state where all system context is lost except system memory. U-Boot
 788           is responsible for restoring the machine state as it was before sleep.
 789           It needs restore the memory controller, without overwriting memory
 790           which is not marked as reserved. For the peripherals which lose their
 791           registers, U-Boot needs to write the original value. When everything
 792           is done, U-Boot needs to find out the wakeup vector provided by OSes
 793           and jump there.
 794
 795 config S3_VGA_ROM_RUN
 796         bool "Re-run VGA option ROMs on S3 resume"
 797         depends on HAVE_ACPI_RESUME
 798         help
 799           Execute VGA option ROMs in U-Boot when resuming from S3. Normally
 800           this is needed when graphics console is being used in the kernel.
 801
 802           Turning it off can reduce some resume time, but be aware that your
 803           graphics console won't work without VGA options ROMs. Set it to N
 804           if your kernel is only on a serial console.
 805
 806 config STACK_SIZE_RESUME
 807         hex
 808         depends on HAVE_ACPI_RESUME
 809         default 0x1000
 810         help
 811           Estimated U-Boot's runtime stack size that needs to be reserved
 812           during an ACPI S3 resume.
 813
 814 config MAX_PIRQ_LINKS
 815         int
 816         default 8
 817         help
 818           This variable specifies the number of PIRQ interrupt links which are
 819           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 820           Some newer chipsets offer more than four links, commonly up to PIRQH.
 821
 822 config IRQ_SLOT_COUNT
 823         int
 824         default 128
 825         help
 826           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 827           which in turns forms a table of exact 4KiB. The default value 128
 828           should be enough for most boards. If this does not fit your board,
 829           change it according to your needs.
 830
 831 config PCIE_ECAM_BASE
 832         hex
 833         default 0xe0000000
 834         help
 835           This is the memory-mapped address of PCI configuration space, which
 836           is only available through the Enhanced Configuration Access
 837           Mechanism (ECAM) with PCI Express. It can be set up almost
 838           anywhere. Before it is set up, it is possible to access PCI
 839           configuration space through I/O access, but memory access is more
 840           convenient. Using this, PCI can be scanned and configured. This
 841           should be set to a region that does not conflict with memory
 842           assigned to PCI devices - i.e. the memory and prefetch regions, as
 843           passed to pci_set_region().
 844
 845 config PCIE_ECAM_SIZE
 846         hex
 847         default 0x10000000
 848         help
 849           This is the size of memory-mapped address of PCI configuration space,
 850           which is only available through the Enhanced Configuration Access
 851           Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
 852           so a default 0x10000000 size covers all of the 256 buses which is the
 853           maximum number of PCI buses as defined by the PCI specification.
 854
 855 config I8259_PIC
 856         bool "Enable Intel 8259 compatible interrupt controller"
 857         default y
 858         help
 859           Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 860           slave) interrupt controllers. Include this to have U-Boot set up
 861           the interrupt correctly.
 862
 863 config APIC
 864         bool "Enable Intel Advanced Programmable Interrupt Controller"
 865         default y
 866         help
 867           The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
 868           for catching interrupts and distributing them to one or more CPU
 869           cores. In most cases there are some LAPICs (local) for each core and
 870           one I/O APIC. This conjunction is found on most modern x86 systems.
 871
 872 config PINCTRL_ICH6
 873         bool
 874         help
 875           Intel ICH6 compatible chipset pinctrl driver. It needs to work
 876           together with the ICH6 compatible gpio driver.
 877
 878 config I8254_TIMER
 879         bool
 880         default y
 881         help
 882           Intel 8254 timer contains three counters which have fixed uses.
 883           Include this to have U-Boot set up the timer correctly.
 884
 885 config SEABIOS
 886         bool "Support booting SeaBIOS"
 887         help
 888           SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
 889           It can run in an emulator or natively on X86 hardware with the use
 890           of coreboot/U-Boot. By turning on this option, U-Boot prepares
 891           all the configuration tables that are necessary to boot SeaBIOS.
 892
 893           Check http://www.seabios.org/SeaBIOS for details.
 894
 895 config HIGH_TABLE_SIZE
 896         hex "Size of configuration tables which reside in high memory"
 897         default 0x10000
 898         depends on SEABIOS
 899         help
 900           SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
 901           configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
 902           puts a copy of configuration tables in high memory region which
 903           is reserved on the stack before relocation. The region size is
 904           determined by this option.
 905
 906           Increse it if the default size does not fit the board's needs.
 907           This is most likely due to a large ACPI DSDT table is used.
 908
 909 config INTEL_CAR_CQOS
 910         bool "Support Intel Cache Quality of Service"
 911         help
 912           Cache Quality of Service allows more fine-grained control of cache
 913           usage. As result, it is possible to set up a portion of L2 cache for
 914           CAR and use the remainder for actual caching.
 915
 916 #
 917 # Each bit in QOS mask controls this many bytes. This is calculated as:
 918 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
 919 #
 920 config CACHE_QOS_SIZE_PER_BIT
 921         hex
 922         depends on INTEL_CAR_CQOS
 923         default 0x20000 # 128 KB
 924
 925 config X86_OFFSET_U_BOOT
 926         hex "Offset of U-Boot in ROM image"
 927         depends on HAVE_TEXT_BASE
 928         default TEXT_BASE
 929
 930 config X86_OFFSET_SPL
 931         hex "Offset of SPL in ROM image"
 932         depends on SPL && X86
 933         default SPL_TEXT_BASE
 934
 935 config ACPI_GPE
 936         bool "Support ACPI general-purpose events"
 937         help
 938           Enable a driver for ACPI GPEs to allow peripherals to send interrupts
 939           via ACPI to the OS. In U-Boot this is only used when U-Boot itself
 940           needs access to these interrupts. This can happen when it uses a
 941           peripheral that is set up to use GPEs and so cannot use the normal
 942           GPIO mechanism for polling an input.
 943
 944           See https://queue.acm.org/blogposting.cfm?id=18977 for more info
 945
 946 config SPL_ACPI_GPE
 947         bool "Support ACPI general-purpose events in SPL"
 948         depends on SPL
 949         help
 950           Enable a driver for ACPI GPEs to allow peripherals to send interrupts
 951           via ACPI to the OS. In U-Boot this is only used when U-Boot itself
 952           needs access to these interrupts. This can happen when it uses a
 953           peripheral that is set up to use GPEs and so cannot use the normal
 954           GPIO mechanism for polling an input.
 955
 956           See https://queue.acm.org/blogposting.cfm?id=18977 for more info
 957
 958 config TPL_ACPI_GPE
 959         bool "Support ACPI general-purpose events in TPL"
 960         depends on TPL
 961         help
 962           Enable a driver for ACPI GPEs to allow peripherals to send interrupts
 963           via ACPI to the OS. In U-Boot this is only used when U-Boot itself
 964           needs access to these interrupts. This can happen when it uses a
 965           peripheral that is set up to use GPEs and so cannot use the normal
 966           GPIO mechanism for polling an input.
 967
 968           See https://queue.acm.org/blogposting.cfm?id=18977 for more info
 969
 970 config SA_PCIEX_LENGTH
 971         hex
 972         default 0x10000000 if (PCIEX_LENGTH_256MB)
 973         default 0x8000000 if (PCIEX_LENGTH_128MB)
 974         default 0x4000000 if (PCIEX_LENGTH_64MB)
 975         default 0x10000000
 976         help
 977           This option allows you to select length of PCIEX region.
 978
 979 config PCIEX_LENGTH_256MB
 980         bool
 981
 982 config PCIEX_LENGTH_128MB
 983         bool
 984
 985 config PCIEX_LENGTH_64MB
 986         bool
 987
 988 config INTEL_SOC
 989         bool
 990         help
 991           This is enabled on Intel SoCs that can support various advanced
 992           features such as power management (requiring asm/arch/pm.h), system
 993           agent (asm/arch/systemagent.h) and an I/O map for ACPI
 994           (asm/arch/iomap.h).
 995
 996           This cannot be selected in a defconfig file. It must be enabled by a
 997           'select' in the SoC's Kconfig.
 998
 999 if INTEL_SOC
1000
1001 config INTEL_ACPIGEN
1002         bool "Support ACPI table generation for Intel SoCs"
1003         depends on ACPIGEN
1004         help
1005           This option adds some functions used for programmatic generation of
1006           ACPI tables on Intel SoCs. This provides features for writing CPU
1007           information such as P states and T stages. Also included is a way
1008           to create a GNVS table and set it up.
1009
1010 config INTEL_GMA_ACPI
1011         bool "Generate ACPI table for Intel GMA graphics"
1012         help
1013           The Intel GMA graphics driver in Linux expects an ACPI table
1014           which describes the layout of the registers and the display
1015           connected to the device. Enable this option to create this
1016           table so that graphics works correctly.
1017
1018 config INTEL_GENERIC_WIFI
1019         bool "Enable generation of ACPI tables for Intel WiFi"
1020         help
1021           Select this option to provide code to a build generic WiFi ACPI table
1022           for Intel WiFi devices. This is not a WiFi driver and offers no
1023           network functionality. It is only here to generate the ACPI tables
1024           required by Linux.
1025
1026 config INTEL_GMA_SWSMISCI
1027         bool
1028         help
1029           Select this option for Atom-based platforms which use the SWSMISCI
1030           register (0xe0) rather than the SWSCI register (0xe8).
1031
1032 endif # INTEL_SOC
1033
1034 config COREBOOT_SYSINFO
1035         bool "Support reading coreboot sysinfo"
1036         default y if SYS_COREBOOT
1037         help
1038           Select this option to read the coreboot sysinfo table on start-up,
1039           if present. This is written by coreboot before it exits and provides
1040           various pieces of information about the running system, including
1041           display, memory and build information. It is stored in
1042           struct sysinfo_t after parsing by get_coreboot_info().
1043
1044 config SPL_COREBOOT_SYSINFO
1045         bool "Support reading coreboot sysinfo"
1046         depends on SPL
1047         default y if COREBOOT_SYSINFO
1048         help
1049           Select this option to read the coreboot sysinfo table in SPL,
1050           if present. This is written by coreboot before it exits and provides
1051           various pieces of information about the running system, including
1052           display, memory and build information. It is stored in
1053           struct sysinfo_t after parsing by get_coreboot_info().
1054
1055 endmenu