arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Mainboard vendor"
   9         default VENDOR_EMULATION
  10
  11 config VENDOR_COREBOOT
  12         bool "coreboot"
  13
  14 config VENDOR_EFI
  15         bool "efi"
  16
  17 config VENDOR_EMULATION
  18         bool "emulation"
  19
  20 config VENDOR_GOOGLE
  21         bool "Google"
  22
  23 config VENDOR_INTEL
  24         bool "Intel"
  25
  26 endchoice
  27
  28 # board-specific options below
  29 source "board/coreboot/Kconfig"
  30 source "board/efi/Kconfig"
  31 source "board/emulation/Kconfig"
  32 source "board/google/Kconfig"
  33 source "board/intel/Kconfig"
  34
  35 # platform-specific options below
  36 source "arch/x86/cpu/baytrail/Kconfig"
  37 source "arch/x86/cpu/coreboot/Kconfig"
  38 source "arch/x86/cpu/ivybridge/Kconfig"
  39 source "arch/x86/cpu/qemu/Kconfig"
  40 source "arch/x86/cpu/quark/Kconfig"
  41 source "arch/x86/cpu/queensbay/Kconfig"
  42
  43 # architecture-specific options below
  44
  45 config SYS_MALLOC_F_LEN
  46         default 0x800
  47
  48 config RAMBASE
  49         hex
  50         default 0x100000
  51
  52 config XIP_ROM_SIZE
  53         hex
  54         depends on X86_RESET_VECTOR
  55         default ROM_SIZE
  56
  57 config CPU_ADDR_BITS
  58         int
  59         default 36
  60
  61 config HPET_ADDRESS
  62         hex
  63         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  64
  65 config SMM_TSEG
  66         bool
  67         default n
  68
  69 config SMM_TSEG_SIZE
  70         hex
  71
  72 config X86_RESET_VECTOR
  73         bool
  74         default n
  75
  76 config RESET_SEG_START
  77         hex
  78         depends on X86_RESET_VECTOR
  79         default 0xffff0000
  80
  81 config RESET_SEG_SIZE
  82         hex
  83         depends on X86_RESET_VECTOR
  84         default 0x10000
  85
  86 config RESET_VEC_LOC
  87         hex
  88         depends on X86_RESET_VECTOR
  89         default 0xfffffff0
  90
  91 config SYS_X86_START16
  92         hex
  93         depends on X86_RESET_VECTOR
  94         default 0xfffff800
  95
  96 config BOARD_ROMSIZE_KB_512
  97         bool
  98 config BOARD_ROMSIZE_KB_1024
  99         bool
 100 config BOARD_ROMSIZE_KB_2048
 101         bool
 102 config BOARD_ROMSIZE_KB_4096
 103         bool
 104 config BOARD_ROMSIZE_KB_8192
 105         bool
 106 config BOARD_ROMSIZE_KB_16384
 107         bool
 108
 109 choice
 110         prompt "ROM chip size"
 111         depends on X86_RESET_VECTOR
 112         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 113         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 114         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 115         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 116         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 117         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 118         help
 119           Select the size of the ROM chip you intend to flash U-Boot on.
 120
 121           The build system will take care of creating a u-boot.rom file
 122           of the matching size.
 123
 124 config UBOOT_ROMSIZE_KB_512
 125         bool "512 KB"
 126         help
 127           Choose this option if you have a 512 KB ROM chip.
 128
 129 config UBOOT_ROMSIZE_KB_1024
 130         bool "1024 KB (1 MB)"
 131         help
 132           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 133
 134 config UBOOT_ROMSIZE_KB_2048
 135         bool "2048 KB (2 MB)"
 136         help
 137           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 138
 139 config UBOOT_ROMSIZE_KB_4096
 140         bool "4096 KB (4 MB)"
 141         help
 142           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 143
 144 config UBOOT_ROMSIZE_KB_8192
 145         bool "8192 KB (8 MB)"
 146         help
 147           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 148
 149 config UBOOT_ROMSIZE_KB_16384
 150         bool "16384 KB (16 MB)"
 151         help
 152           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 153
 154 endchoice
 155
 156 # Map the config names to an integer (KB).
 157 config UBOOT_ROMSIZE_KB
 158         int
 159         default 512 if UBOOT_ROMSIZE_KB_512
 160         default 1024 if UBOOT_ROMSIZE_KB_1024
 161         default 2048 if UBOOT_ROMSIZE_KB_2048
 162         default 4096 if UBOOT_ROMSIZE_KB_4096
 163         default 8192 if UBOOT_ROMSIZE_KB_8192
 164         default 16384 if UBOOT_ROMSIZE_KB_16384
 165
 166 # Map the config names to a hex value (bytes).
 167 config ROM_SIZE
 168         hex
 169         default 0x80000 if UBOOT_ROMSIZE_KB_512
 170         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 171         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 172         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 173         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 174         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 175         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 176
 177 config HAVE_INTEL_ME
 178         bool "Platform requires Intel Management Engine"
 179         help
 180           Newer higher-end devices have an Intel Management Engine (ME)
 181           which is a very large binary blob (typically 1.5MB) which is
 182           required for the platform to work. This enforces a particular
 183           SPI flash format. You will need to supply the me.bin file in
 184           your board directory.
 185
 186 config X86_RAMTEST
 187         bool "Perform a simple RAM test after SDRAM initialisation"
 188         help
 189           If there is something wrong with SDRAM then the platform will
 190           often crash within U-Boot or the kernel. This option enables a
 191           very simple RAM test that quickly checks whether the SDRAM seems
 192           to work correctly. It is not exhaustive but can save time by
 193           detecting obvious failures.
 194
 195 config HAVE_FSP
 196         bool "Add an Firmware Support Package binary"
 197         depends on !EFI
 198         help
 199           Select this option to add an Firmware Support Package binary to
 200           the resulting U-Boot image. It is a binary blob which U-Boot uses
 201           to set up SDRAM and other chipset specific initialization.
 202
 203           Note: Without this binary U-Boot will not be able to set up its
 204           SDRAM so will not boot.
 205
 206 config FSP_FILE
 207         string "Firmware Support Package binary filename"
 208         depends on HAVE_FSP
 209         default "fsp.bin"
 210         help
 211           The filename of the file to use as Firmware Support Package binary
 212           in the board directory.
 213
 214 config FSP_ADDR
 215         hex "Firmware Support Package binary location"
 216         depends on HAVE_FSP
 217         default 0xfffc0000
 218         help
 219           FSP is not Position Independent Code (PIC) and the whole FSP has to
 220           be rebased if it is placed at a location which is different from the
 221           perferred base address specified during the FSP build. Use Intel's
 222           Binary Configuration Tool (BCT) to do the rebase.
 223
 224           The default base address of 0xfffc0000 indicates that the binary must
 225           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 226
 227 config FSP_TEMP_RAM_ADDR
 228         hex
 229         depends on HAVE_FSP
 230         default 0x2000000
 231         help
 232           Stack top address which is used in fsp_init() after DRAM is ready and
 233           CAR is disabled.
 234
 235 config FSP_SYS_MALLOC_F_LEN
 236         hex
 237         depends on HAVE_FSP
 238         default 0x100000
 239         help
 240           Additional size of malloc() pool before relocation.
 241
 242 config ENABLE_MRC_CACHE
 243         bool "Enable MRC cache"
 244         depends on !EFI && !SYS_COREBOOT
 245         help
 246           Enable this feature to cause MRC data to be cached in NV storage
 247           to be used for speeding up boot time on future reboots and/or
 248           power cycles.
 249
 250 config SMP
 251         bool "Enable Symmetric Multiprocessing"
 252         default n
 253         help
 254           Enable use of more than one CPU in U-Boot and the Operating System
 255           when loaded. Each CPU will be started up and information can be
 256           obtained using the 'cpu' command. If this option is disabled, then
 257           only one CPU will be enabled regardless of the number of CPUs
 258           available.
 259
 260 config MAX_CPUS
 261         int "Maximum number of CPUs permitted"
 262         depends on SMP
 263         default 4
 264         help
 265           When using multi-CPU chips it is possible for U-Boot to start up
 266           more than one CPU. The stack memory used by all of these CPUs is
 267           pre-allocated so at present U-Boot wants to know the maximum
 268           number of CPUs that may be present. Set this to at least as high
 269           as the number of CPUs in your system (it uses about 4KB of RAM for
 270           each CPU).
 271
 272 config AP_STACK_SIZE
 273         hex
 274         depends on SMP
 275         default 0x1000
 276         help
 277           Each additional CPU started by U-Boot requires its own stack. This
 278           option sets the stack size used by each CPU and directly affects
 279           the memory used by this initialisation process. Typically 4KB is
 280           enough space.
 281
 282 config TSC_CALIBRATION_BYPASS
 283         bool "Bypass Time-Stamp Counter (TSC) calibration"
 284         default n
 285         help
 286           By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
 287           running frequency via Model-Specific Register (MSR) and Programmable
 288           Interval Timer (PIT). If the calibration does not work on your board,
 289           select this option and provide a hardcoded TSC running frequency with
 290           CONFIG_TSC_FREQ_IN_MHZ below.
 291
 292           Normally this option should be turned on in a simulation environment
 293           like qemu.
 294
 295 config TSC_FREQ_IN_MHZ
 296         int "Time-Stamp Counter (TSC) running frequency in MHz"
 297         depends on TSC_CALIBRATION_BYPASS
 298         default 1000
 299         help
 300           The running frequency in MHz of Time-Stamp Counter (TSC).
 301
 302 config HAVE_VGA_BIOS
 303         bool "Add a VGA BIOS image"
 304         help
 305           Select this option if you have a VGA BIOS image that you would
 306           like to add to your ROM.
 307
 308 config VGA_BIOS_FILE
 309         string "VGA BIOS image filename"
 310         depends on HAVE_VGA_BIOS
 311         default "vga.bin"
 312         help
 313           The filename of the VGA BIOS image in the board directory.
 314
 315 config VGA_BIOS_ADDR
 316         hex "VGA BIOS image location"
 317         depends on HAVE_VGA_BIOS
 318         default 0xfff90000
 319         help
 320           The location of VGA BIOS image in the SPI flash. For example, base
 321           address of 0xfff90000 indicates that the image will be put at offset
 322           0x90000 from the beginning of a 1MB flash device.
 323
 324 menu "System tables"
 325         depends on !EFI && !SYS_COREBOOT
 326
 327 config GENERATE_PIRQ_TABLE
 328         bool "Generate a PIRQ table"
 329         default n
 330         help
 331           Generate a PIRQ routing table for this board. The PIRQ routing table
 332           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 333           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 334           It specifies the interrupt router information as well how all the PCI
 335           devices' interrupt pins are wired to PIRQs.
 336
 337 config GENERATE_SFI_TABLE
 338         bool "Generate a SFI (Simple Firmware Interface) table"
 339         help
 340           The Simple Firmware Interface (SFI) provides a lightweight method
 341           for platform firmware to pass information to the operating system
 342           via static tables in memory.  Kernel SFI support is required to
 343           boot on SFI-only platforms.  If you have ACPI tables then these are
 344           used instead.
 345
 346           U-Boot writes this table in write_sfi_table() just before booting
 347           the OS.
 348
 349           For more information, see http://simplefirmware.org
 350
 351 config GENERATE_MP_TABLE
 352         bool "Generate an MP (Multi-Processor) table"
 353         default n
 354         help
 355           Generate an MP (Multi-Processor) table for this board. The MP table
 356           provides a way for the operating system to support for symmetric
 357           multiprocessing as well as symmetric I/O interrupt handling with
 358           the local APIC and I/O APIC.
 359
 360 config GENERATE_ACPI_TABLE
 361         bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 362         default n
 363         help
 364           The Advanced Configuration and Power Interface (ACPI) specification
 365           provides an open standard for device configuration and management
 366           by the operating system. It defines platform-independent interfaces
 367           for configuration and power management monitoring.
 368
 369 config GENERATE_SMBIOS_TABLE
 370         bool "Generate an SMBIOS (System Management BIOS) table"
 371         default y
 372         help
 373           The System Management BIOS (SMBIOS) specification addresses how
 374           motherboard and system vendors present management information about
 375           their products in a standard format by extending the BIOS interface
 376           on Intel architecture systems.
 377
 378           Check http://www.dmtf.org/standards/smbios for details.
 379
 380 endmenu
 381
 382 config MAX_PIRQ_LINKS
 383         int
 384         default 8
 385         help
 386           This variable specifies the number of PIRQ interrupt links which are
 387           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 388           Some newer chipsets offer more than four links, commonly up to PIRQH.
 389
 390 config IRQ_SLOT_COUNT
 391         int
 392         default 128
 393         help
 394           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 395           which in turns forms a table of exact 4KiB. The default value 128
 396           should be enough for most boards. If this does not fit your board,
 397           change it according to your needs.
 398
 399 config PCIE_ECAM_BASE
 400         hex
 401         default 0xe0000000
 402         help
 403           This is the memory-mapped address of PCI configuration space, which
 404           is only available through the Enhanced Configuration Access
 405           Mechanism (ECAM) with PCI Express. It can be set up almost
 406           anywhere. Before it is set up, it is possible to access PCI
 407           configuration space through I/O access, but memory access is more
 408           convenient. Using this, PCI can be scanned and configured. This
 409           should be set to a region that does not conflict with memory
 410           assigned to PCI devices - i.e. the memory and prefetch regions, as
 411           passed to pci_set_region().
 412
 413 config PCIE_ECAM_SIZE
 414         hex
 415         default 0x10000000
 416         help
 417           This is the size of memory-mapped address of PCI configuration space,
 418           which is only available through the Enhanced Configuration Access
 419           Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
 420           so a default 0x10000000 size covers all of the 256 buses which is the
 421           maximum number of PCI buses as defined by the PCI specification.
 422
 423 config I8259_PIC
 424         bool
 425         default y
 426         help
 427           Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 428           slave) interrupt controllers. Include this to have U-Boot set up
 429           the interrupt correctly.
 430
 431 config I8254_TIMER
 432         bool
 433         default y
 434         help
 435           Intel 8254 timer contains three counters which have fixed uses.
 436           Include this to have U-Boot set up the timer correctly.
 437
 438 source "arch/x86/lib/efi/Kconfig"
 439
 440 endmenu