arch/x86/Kconfig

   1 menu "x86 architecture"
   2         depends on X86
   3
   4 config SYS_ARCH
   5         default "x86"
   6
   7 choice
   8         prompt "Mainboard vendor"
   9         default VENDOR_EMULATION
  10
  11 config VENDOR_ADVANTECH
  12         bool "advantech"
  13
  14 config VENDOR_CONGATEC
  15         bool "congatec"
  16
  17 config VENDOR_COREBOOT
  18         bool "coreboot"
  19
  20 config VENDOR_EFI
  21         bool "efi"
  22
  23 config VENDOR_EMULATION
  24         bool "emulation"
  25
  26 config VENDOR_GOOGLE
  27         bool "Google"
  28
  29 config VENDOR_INTEL
  30         bool "Intel"
  31
  32 endchoice
  33
  34 # board-specific options below
  35 source "board/advantech/Kconfig"
  36 source "board/congatec/Kconfig"
  37 source "board/coreboot/Kconfig"
  38 source "board/efi/Kconfig"
  39 source "board/emulation/Kconfig"
  40 source "board/google/Kconfig"
  41 source "board/intel/Kconfig"
  42
  43 # platform-specific options below
  44 source "arch/x86/cpu/baytrail/Kconfig"
  45 source "arch/x86/cpu/broadwell/Kconfig"
  46 source "arch/x86/cpu/coreboot/Kconfig"
  47 source "arch/x86/cpu/ivybridge/Kconfig"
  48 source "arch/x86/cpu/qemu/Kconfig"
  49 source "arch/x86/cpu/quark/Kconfig"
  50 source "arch/x86/cpu/queensbay/Kconfig"
  51
  52 # architecture-specific options below
  53
  54 config AHCI
  55         default y
  56
  57 config SYS_MALLOC_F_LEN
  58         default 0x800
  59
  60 config RAMBASE
  61         hex
  62         default 0x100000
  63
  64 config XIP_ROM_SIZE
  65         hex
  66         depends on X86_RESET_VECTOR
  67         default ROM_SIZE
  68
  69 config CPU_ADDR_BITS
  70         int
  71         default 36
  72
  73 config HPET_ADDRESS
  74         hex
  75         default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  76
  77 config SMM_TSEG
  78         bool
  79         default n
  80
  81 config SMM_TSEG_SIZE
  82         hex
  83
  84 config X86_RESET_VECTOR
  85         bool
  86         default n
  87
  88 config RESET_SEG_START
  89         hex
  90         depends on X86_RESET_VECTOR
  91         default 0xffff0000
  92
  93 config RESET_SEG_SIZE
  94         hex
  95         depends on X86_RESET_VECTOR
  96         default 0x10000
  97
  98 config RESET_VEC_LOC
  99         hex
 100         depends on X86_RESET_VECTOR
 101         default 0xfffffff0
 102
 103 config SYS_X86_START16
 104         hex
 105         depends on X86_RESET_VECTOR
 106         default 0xfffff800
 107
 108 config BOARD_ROMSIZE_KB_512
 109         bool
 110 config BOARD_ROMSIZE_KB_1024
 111         bool
 112 config BOARD_ROMSIZE_KB_2048
 113         bool
 114 config BOARD_ROMSIZE_KB_4096
 115         bool
 116 config BOARD_ROMSIZE_KB_8192
 117         bool
 118 config BOARD_ROMSIZE_KB_16384
 119         bool
 120
 121 choice
 122         prompt "ROM chip size"
 123         depends on X86_RESET_VECTOR
 124         default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
 125         default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 126         default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 127         default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
 128         default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 129         default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
 130         help
 131           Select the size of the ROM chip you intend to flash U-Boot on.
 132
 133           The build system will take care of creating a u-boot.rom file
 134           of the matching size.
 135
 136 config UBOOT_ROMSIZE_KB_512
 137         bool "512 KB"
 138         help
 139           Choose this option if you have a 512 KB ROM chip.
 140
 141 config UBOOT_ROMSIZE_KB_1024
 142         bool "1024 KB (1 MB)"
 143         help
 144           Choose this option if you have a 1024 KB (1 MB) ROM chip.
 145
 146 config UBOOT_ROMSIZE_KB_2048
 147         bool "2048 KB (2 MB)"
 148         help
 149           Choose this option if you have a 2048 KB (2 MB) ROM chip.
 150
 151 config UBOOT_ROMSIZE_KB_4096
 152         bool "4096 KB (4 MB)"
 153         help
 154           Choose this option if you have a 4096 KB (4 MB) ROM chip.
 155
 156 config UBOOT_ROMSIZE_KB_8192
 157         bool "8192 KB (8 MB)"
 158         help
 159           Choose this option if you have a 8192 KB (8 MB) ROM chip.
 160
 161 config UBOOT_ROMSIZE_KB_16384
 162         bool "16384 KB (16 MB)"
 163         help
 164           Choose this option if you have a 16384 KB (16 MB) ROM chip.
 165
 166 endchoice
 167
 168 # Map the config names to an integer (KB).
 169 config UBOOT_ROMSIZE_KB
 170         int
 171         default 512 if UBOOT_ROMSIZE_KB_512
 172         default 1024 if UBOOT_ROMSIZE_KB_1024
 173         default 2048 if UBOOT_ROMSIZE_KB_2048
 174         default 4096 if UBOOT_ROMSIZE_KB_4096
 175         default 8192 if UBOOT_ROMSIZE_KB_8192
 176         default 16384 if UBOOT_ROMSIZE_KB_16384
 177
 178 # Map the config names to a hex value (bytes).
 179 config ROM_SIZE
 180         hex
 181         default 0x80000 if UBOOT_ROMSIZE_KB_512
 182         default 0x100000 if UBOOT_ROMSIZE_KB_1024
 183         default 0x200000 if UBOOT_ROMSIZE_KB_2048
 184         default 0x400000 if UBOOT_ROMSIZE_KB_4096
 185         default 0x800000 if UBOOT_ROMSIZE_KB_8192
 186         default 0xc00000 if UBOOT_ROMSIZE_KB_12288
 187         default 0x1000000 if UBOOT_ROMSIZE_KB_16384
 188
 189 config HAVE_INTEL_ME
 190         bool "Platform requires Intel Management Engine"
 191         help
 192           Newer higher-end devices have an Intel Management Engine (ME)
 193           which is a very large binary blob (typically 1.5MB) which is
 194           required for the platform to work. This enforces a particular
 195           SPI flash format. You will need to supply the me.bin file in
 196           your board directory.
 197
 198 config X86_RAMTEST
 199         bool "Perform a simple RAM test after SDRAM initialisation"
 200         help
 201           If there is something wrong with SDRAM then the platform will
 202           often crash within U-Boot or the kernel. This option enables a
 203           very simple RAM test that quickly checks whether the SDRAM seems
 204           to work correctly. It is not exhaustive but can save time by
 205           detecting obvious failures.
 206
 207 config HAVE_FSP
 208         bool "Add an Firmware Support Package binary"
 209         depends on !EFI
 210         help
 211           Select this option to add an Firmware Support Package binary to
 212           the resulting U-Boot image. It is a binary blob which U-Boot uses
 213           to set up SDRAM and other chipset specific initialization.
 214
 215           Note: Without this binary U-Boot will not be able to set up its
 216           SDRAM so will not boot.
 217
 218 config FSP_FILE
 219         string "Firmware Support Package binary filename"
 220         depends on HAVE_FSP
 221         default "fsp.bin"
 222         help
 223           The filename of the file to use as Firmware Support Package binary
 224           in the board directory.
 225
 226 config FSP_ADDR
 227         hex "Firmware Support Package binary location"
 228         depends on HAVE_FSP
 229         default 0xfffc0000
 230         help
 231           FSP is not Position Independent Code (PIC) and the whole FSP has to
 232           be rebased if it is placed at a location which is different from the
 233           perferred base address specified during the FSP build. Use Intel's
 234           Binary Configuration Tool (BCT) to do the rebase.
 235
 236           The default base address of 0xfffc0000 indicates that the binary must
 237           be located at offset 0xc0000 from the beginning of a 1MB flash device.
 238
 239 config FSP_TEMP_RAM_ADDR
 240         hex
 241         depends on HAVE_FSP
 242         default 0x2000000
 243         help
 244           Stack top address which is used in fsp_init() after DRAM is ready and
 245           CAR is disabled.
 246
 247 config FSP_SYS_MALLOC_F_LEN
 248         hex
 249         depends on HAVE_FSP
 250         default 0x100000
 251         help
 252           Additional size of malloc() pool before relocation.
 253
 254 config FSP_USE_UPD
 255         bool
 256         depends on HAVE_FSP
 257         default y
 258         help
 259           Most FSPs use UPD data region for some FSP customization. But there
 260           are still some FSPs that might not even have UPD. For such FSPs,
 261           override this to n in their platform Kconfig files.
 262
 263 config FSP_BROKEN_HOB
 264         bool
 265         depends on HAVE_FSP
 266         help
 267           Indicate some buggy FSPs that does not report memory used by FSP
 268           itself as reserved in the resource descriptor HOB. Select this to
 269           tell U-Boot to do some additional work to ensure U-Boot relocation
 270           do not overwrite the important boot service data which is used by
 271           FSP, otherwise the subsequent call to fsp_notify() will fail.
 272
 273 config ENABLE_MRC_CACHE
 274         bool "Enable MRC cache"
 275         depends on !EFI && !SYS_COREBOOT
 276         help
 277           Enable this feature to cause MRC data to be cached in NV storage
 278           to be used for speeding up boot time on future reboots and/or
 279           power cycles.
 280
 281           For platforms that use Intel FSP for the memory initialization,
 282           please check FSP output HOB via U-Boot command 'fsp hob' to see
 283           if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
 284           If such GUID does not exist, MRC cache is not avaiable on such
 285           platform (eg: Intel Queensbay), which means selecting this option
 286           here does not make any difference.
 287
 288 config HAVE_MRC
 289         bool "Add a System Agent binary"
 290         depends on !HAVE_FSP
 291         help
 292           Select this option to add a System Agent binary to
 293           the resulting U-Boot image. MRC stands for Memory Reference Code.
 294           It is a binary blob which U-Boot uses to set up SDRAM.
 295
 296           Note: Without this binary U-Boot will not be able to set up its
 297           SDRAM so will not boot.
 298
 299 config CACHE_MRC_BIN
 300         bool
 301         depends on HAVE_MRC
 302         default n
 303         help
 304           Enable caching for the memory reference code binary. This uses an
 305           MTRR (memory type range register) to turn on caching for the section
 306           of SPI flash that contains the memory reference code. This makes
 307           SDRAM init run faster.
 308
 309 config CACHE_MRC_SIZE_KB
 310         int
 311         depends on HAVE_MRC
 312         default 512
 313         help
 314           Sets the size of the cached area for the memory reference code.
 315           This ends at the end of SPI flash (address 0xffffffff) and is
 316           measured in KB. Typically this is set to 512, providing for 0.5MB
 317           of cached space.
 318
 319 config DCACHE_RAM_BASE
 320         hex
 321         depends on HAVE_MRC
 322         help
 323           Sets the base of the data cache area in memory space. This is the
 324           start address of the cache-as-RAM (CAR) area and the address varies
 325           depending on the CPU. Once CAR is set up, read/write memory becomes
 326           available at this address and can be used temporarily until SDRAM
 327           is working.
 328
 329 config DCACHE_RAM_SIZE
 330         hex
 331         depends on HAVE_MRC
 332         default 0x40000
 333         help
 334           Sets the total size of the data cache area in memory space. This
 335           sets the size of the cache-as-RAM (CAR) area. Note that much of the
 336           CAR space is required by the MRC. The CAR space available to U-Boot
 337           is normally at the start and typically extends to 1/4 or 1/2 of the
 338           available size.
 339
 340 config DCACHE_RAM_MRC_VAR_SIZE
 341         hex
 342         depends on HAVE_MRC
 343         help
 344           This is the amount of CAR (Cache as RAM) reserved for use by the
 345           memory reference code. This depends on the implementation of the
 346           memory reference code and must be set correctly or the board will
 347           not boot.
 348
 349 config HAVE_REFCODE
 350         bool "Add a Reference Code binary"
 351         help
 352           Select this option to add a Reference Code binary to the resulting
 353           U-Boot image. This is an Intel binary blob that handles system
 354           initialisation, in this case the PCH and System Agent.
 355
 356           Note: Without this binary (on platforms that need it such as
 357           broadwell) U-Boot will be missing some critical setup steps.
 358           Various peripherals may fail to work.
 359
 360 config SMP
 361         bool "Enable Symmetric Multiprocessing"
 362         default n
 363         help
 364           Enable use of more than one CPU in U-Boot and the Operating System
 365           when loaded. Each CPU will be started up and information can be
 366           obtained using the 'cpu' command. If this option is disabled, then
 367           only one CPU will be enabled regardless of the number of CPUs
 368           available.
 369
 370 config MAX_CPUS
 371         int "Maximum number of CPUs permitted"
 372         depends on SMP
 373         default 4
 374         help
 375           When using multi-CPU chips it is possible for U-Boot to start up
 376           more than one CPU. The stack memory used by all of these CPUs is
 377           pre-allocated so at present U-Boot wants to know the maximum
 378           number of CPUs that may be present. Set this to at least as high
 379           as the number of CPUs in your system (it uses about 4KB of RAM for
 380           each CPU).
 381
 382 config AP_STACK_SIZE
 383         hex
 384         depends on SMP
 385         default 0x1000
 386         help
 387           Each additional CPU started by U-Boot requires its own stack. This
 388           option sets the stack size used by each CPU and directly affects
 389           the memory used by this initialisation process. Typically 4KB is
 390           enough space.
 391
 392 config HAVE_VGA_BIOS
 393         bool "Add a VGA BIOS image"
 394         help
 395           Select this option if you have a VGA BIOS image that you would
 396           like to add to your ROM.
 397
 398 config VGA_BIOS_FILE
 399         string "VGA BIOS image filename"
 400         depends on HAVE_VGA_BIOS
 401         default "vga.bin"
 402         help
 403           The filename of the VGA BIOS image in the board directory.
 404
 405 config VGA_BIOS_ADDR
 406         hex "VGA BIOS image location"
 407         depends on HAVE_VGA_BIOS
 408         default 0xfff90000
 409         help
 410           The location of VGA BIOS image in the SPI flash. For example, base
 411           address of 0xfff90000 indicates that the image will be put at offset
 412           0x90000 from the beginning of a 1MB flash device.
 413
 414 menu "System tables"
 415         depends on !EFI && !SYS_COREBOOT
 416
 417 config GENERATE_PIRQ_TABLE
 418         bool "Generate a PIRQ table"
 419         default n
 420         help
 421           Generate a PIRQ routing table for this board. The PIRQ routing table
 422           is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
 423           at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
 424           It specifies the interrupt router information as well how all the PCI
 425           devices' interrupt pins are wired to PIRQs.
 426
 427 config GENERATE_SFI_TABLE
 428         bool "Generate a SFI (Simple Firmware Interface) table"
 429         help
 430           The Simple Firmware Interface (SFI) provides a lightweight method
 431           for platform firmware to pass information to the operating system
 432           via static tables in memory.  Kernel SFI support is required to
 433           boot on SFI-only platforms.  If you have ACPI tables then these are
 434           used instead.
 435
 436           U-Boot writes this table in write_sfi_table() just before booting
 437           the OS.
 438
 439           For more information, see http://simplefirmware.org
 440
 441 config GENERATE_MP_TABLE
 442         bool "Generate an MP (Multi-Processor) table"
 443         default n
 444         help
 445           Generate an MP (Multi-Processor) table for this board. The MP table
 446           provides a way for the operating system to support for symmetric
 447           multiprocessing as well as symmetric I/O interrupt handling with
 448           the local APIC and I/O APIC.
 449
 450 config GENERATE_ACPI_TABLE
 451         bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 452         default n
 453         select QFW if QEMU
 454         help
 455           The Advanced Configuration and Power Interface (ACPI) specification
 456           provides an open standard for device configuration and management
 457           by the operating system. It defines platform-independent interfaces
 458           for configuration and power management monitoring.
 459
 460 config GENERATE_SMBIOS_TABLE
 461         bool "Generate an SMBIOS (System Management BIOS) table"
 462         default y
 463         help
 464           The System Management BIOS (SMBIOS) specification addresses how
 465           motherboard and system vendors present management information about
 466           their products in a standard format by extending the BIOS interface
 467           on Intel architecture systems.
 468
 469           Check http://www.dmtf.org/standards/smbios for details.
 470
 471 config SMBIOS_MANUFACTURER
 472         string "SMBIOS Manufacturer"
 473         depends on GENERATE_SMBIOS_TABLE
 474         default SYS_VENDOR
 475         help
 476           The board manufacturer to store in SMBIOS structures.
 477           Change this to override the default one (CONFIG_SYS_VENDOR).
 478
 479 config SMBIOS_PRODUCT_NAME
 480         string "SMBIOS Product Name"
 481         depends on GENERATE_SMBIOS_TABLE
 482         default SYS_BOARD
 483         help
 484           The product name to store in SMBIOS structures.
 485           Change this to override the default one (CONFIG_SYS_BOARD).
 486
 487 endmenu
 488
 489 config MAX_PIRQ_LINKS
 490         int
 491         default 8
 492         help
 493           This variable specifies the number of PIRQ interrupt links which are
 494           routable. On most older chipsets, this is 4, PIRQA through PIRQD.
 495           Some newer chipsets offer more than four links, commonly up to PIRQH.
 496
 497 config IRQ_SLOT_COUNT
 498         int
 499         default 128
 500         help
 501           U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
 502           which in turns forms a table of exact 4KiB. The default value 128
 503           should be enough for most boards. If this does not fit your board,
 504           change it according to your needs.
 505
 506 config PCIE_ECAM_BASE
 507         hex
 508         default 0xe0000000
 509         help
 510           This is the memory-mapped address of PCI configuration space, which
 511           is only available through the Enhanced Configuration Access
 512           Mechanism (ECAM) with PCI Express. It can be set up almost
 513           anywhere. Before it is set up, it is possible to access PCI
 514           configuration space through I/O access, but memory access is more
 515           convenient. Using this, PCI can be scanned and configured. This
 516           should be set to a region that does not conflict with memory
 517           assigned to PCI devices - i.e. the memory and prefetch regions, as
 518           passed to pci_set_region().
 519
 520 config PCIE_ECAM_SIZE
 521         hex
 522         default 0x10000000
 523         help
 524           This is the size of memory-mapped address of PCI configuration space,
 525           which is only available through the Enhanced Configuration Access
 526           Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
 527           so a default 0x10000000 size covers all of the 256 buses which is the
 528           maximum number of PCI buses as defined by the PCI specification.
 529
 530 config I8259_PIC
 531         bool
 532         default y
 533         help
 534           Intel 8259 ISA compatible chipset incorporates two 8259 (master and
 535           slave) interrupt controllers. Include this to have U-Boot set up
 536           the interrupt correctly.
 537
 538 config I8254_TIMER
 539         bool
 540         default y
 541         help
 542           Intel 8254 timer contains three counters which have fixed uses.
 543           Include this to have U-Boot set up the timer correctly.
 544
 545 config I8042_KEYB
 546         default y
 547
 548 config DM_KEYBOARD
 549         default y
 550
 551 config SEABIOS
 552         bool "Support booting SeaBIOS"
 553         help
 554           SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
 555           It can run in an emulator or natively on X86 hardware with the use
 556           of coreboot/U-Boot. By turning on this option, U-Boot prepares
 557           all the configuration tables that are necessary to boot SeaBIOS.
 558
 559           Check http://www.seabios.org/SeaBIOS for details.
 560
 561 config HIGH_TABLE_SIZE
 562         hex "Size of configuration tables which reside in high memory"
 563         default 0x10000
 564         depends on SEABIOS
 565         help
 566           SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
 567           configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
 568           puts a copy of configuration tables in high memory region which
 569           is reserved on the stack before relocation. The region size is
 570           determined by this option.
 571
 572           Increse it if the default size does not fit the board's needs.
 573           This is most likely due to a large ACPI DSDT table is used.
 574
 575 source "arch/x86/lib/efi/Kconfig"
 576
 577 endmenu