arch/x86/cpu/coreboot/coreboot.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008
   4  * Graeme Russ, graeme.russ@gmail.com.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <fdtdec.h>
  11 #include <netdev.h>
  12 #include <asm/io.h>
  13 #include <asm/msr.h>
  14 #include <asm/mtrr.h>
  15 #include <asm/arch/sysinfo.h>
  16 #include <asm/arch/timestamp.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 int arch_cpu_init(void)
  21 {
  22         int ret = get_coreboot_info(&lib_sysinfo);
  23         if (ret != 0) {
  24                 printf("Failed to parse coreboot tables.\n");
  25                 return ret;
  26         }
  27
  28         timestamp_init();
  29
  30         return x86_cpu_init_f();
  31 }
  32
  33 int board_early_init_f(void)
  34 {
  35         return 0;
  36 }
  37
  38 int print_cpuinfo(void)
  39 {
  40         return default_print_cpuinfo();
  41 }
  42
  43 int last_stage_init(void)
  44 {
  45         if (gd->flags & GD_FLG_COLD_BOOT)
  46                 timestamp_add_to_bootstage();
  47
  48         return 0;
  49 }
  50
  51 int board_eth_init(bd_t *bis)
  52 {
  53         return pci_eth_init(bis);
  54 }
  55
  56 void board_final_cleanup(void)
  57 {
  58         /*
  59          * Un-cache the ROM so the kernel has one
  60          * more MTRR available.
  61          *
  62          * Coreboot should have assigned this to the
  63          * top available variable MTRR.
  64          */
  65         u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
  66         u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
  67
  68         /* Make sure this MTRR is the correct Write-Protected type */
  69         if (top_type == MTRR_TYPE_WRPROT) {
  70                 struct mtrr_state state;
  71
  72                 mtrr_open(&state);
  73                 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
  74                 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
  75                 mtrr_close(&state);
  76         }
  77
  78         if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
  79                 /*
  80                  * Issue SMI to coreboot to lock down ME and registers
  81                  * when allowed via device tree
  82                  */
  83                 printf("Finalizing coreboot\n");
  84                 outb(0xcb, 0xb2);
  85         }
  86 }
  87
  88 int misc_init_r(void)
  89 {
  90         return 0;
  91 }