arch/x86/cpu/ivybridge/early_me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
   4  *
   5  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/pci.h>
  12 #include <asm/cpu.h>
  13 #include <asm/processor.h>
  14 #include <asm/arch/me.h>
  15 #include <asm/arch/pch.h>
  16 #include <asm/io.h>
  17
  18 static const char *const me_ack_values[] = {
  19         [ME_HFS_ACK_NO_DID]     = "No DID Ack received",
  20         [ME_HFS_ACK_RESET]      = "Non-power cycle reset",
  21         [ME_HFS_ACK_PWR_CYCLE]  = "Power cycle reset",
  22         [ME_HFS_ACK_S3]         = "Go to S3",
  23         [ME_HFS_ACK_S4]         = "Go to S4",
  24         [ME_HFS_ACK_S5]         = "Go to S5",
  25         [ME_HFS_ACK_GBL_RESET]  = "Global Reset",
  26         [ME_HFS_ACK_CONTINUE]   = "Continue to boot"
  27 };
  28
  29 int intel_early_me_init(struct udevice *me_dev)
  30 {
  31         int count;
  32         struct me_uma uma;
  33         struct me_hfs hfs;
  34
  35         debug("Intel ME early init\n");
  36
  37         /* Wait for ME UMA SIZE VALID bit to be set */
  38         for (count = ME_RETRY; count > 0; --count) {
  39                 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
  40                 if (uma.valid)
  41                         break;
  42                 udelay(ME_DELAY);
  43         }
  44         if (!count) {
  45                 printf("ERROR: ME is not ready!\n");
  46                 return -EBUSY;
  47         }
  48
  49         /* Check for valid firmware */
  50         pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
  51         if (hfs.fpt_bad) {
  52                 printf("WARNING: ME has bad firmware\n");
  53                 return -EBADF;
  54         }
  55
  56         debug("Intel ME firmware is ready\n");
  57
  58         return 0;
  59 }
  60
  61 int intel_early_me_uma_size(struct udevice *me_dev)
  62 {
  63         struct me_uma uma;
  64
  65         pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
  66         if (uma.valid) {
  67                 debug("ME: Requested %uMB UMA\n", uma.size);
  68                 return uma.size;
  69         }
  70
  71         debug("ME: Invalid UMA size\n");
  72         return -EINVAL;
  73 }
  74
  75 static inline void set_global_reset(struct udevice *dev, int enable)
  76 {
  77         u32 etr3;
  78
  79         dm_pci_read_config32(dev, ETR3, &etr3);
  80
  81         /* Clear CF9 Without Resume Well Reset Enable */
  82         etr3 &= ~ETR3_CWORWRE;
  83
  84         /* CF9GR indicates a Global Reset */
  85         if (enable)
  86                 etr3 |= ETR3_CF9GR;
  87         else
  88                 etr3 &= ~ETR3_CF9GR;
  89
  90         dm_pci_write_config32(dev, ETR3, etr3);
  91 }
  92
  93 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
  94                              uint status)
  95 {
  96         int count;
  97         u32 mebase_l, mebase_h;
  98         struct me_hfs hfs;
  99         struct me_did did = {
 100                 .init_done = ME_INIT_DONE,
 101                 .status = status
 102         };
 103
 104         /* MEBASE from MESEG_BASE[35:20] */
 105         dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
 106         dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
 107         mebase_h &= 0xf;
 108         did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
 109
 110         /* Send message to ME */
 111         debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
 112               status, did.uma_base);
 113
 114         pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
 115
 116         /* Must wait for ME acknowledgement */
 117         for (count = ME_RETRY; count > 0; --count) {
 118                 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
 119                 if (hfs.bios_msg_ack)
 120                         break;
 121                 udelay(ME_DELAY);
 122         }
 123         if (!count) {
 124                 printf("ERROR: ME failed to respond\n");
 125                 return -ETIMEDOUT;
 126         }
 127
 128         /* Return the requested BIOS action */
 129         debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
 130
 131         /* Check status after acknowledgement */
 132         intel_me_status(me_dev);
 133
 134         switch (hfs.ack_data) {
 135         case ME_HFS_ACK_CONTINUE:
 136                 /* Continue to boot */
 137                 return 0;
 138         case ME_HFS_ACK_RESET:
 139                 /* Non-power cycle reset */
 140                 set_global_reset(dev, 0);
 141                 reset_cpu(0);
 142                 break;
 143         case ME_HFS_ACK_PWR_CYCLE:
 144                 /* Power cycle reset */
 145                 set_global_reset(dev, 0);
 146                 x86_full_reset();
 147                 break;
 148         case ME_HFS_ACK_GBL_RESET:
 149                 /* Global reset */
 150                 set_global_reset(dev, 1);
 151                 x86_full_reset();
 152                 break;
 153         case ME_HFS_ACK_S3:
 154         case ME_HFS_ACK_S4:
 155         case ME_HFS_ACK_S5:
 156                 break;
 157         }
 158
 159         return -EINVAL;
 160 }
 161
 162 static const struct udevice_id ivybridge_syscon_ids[] = {
 163         { .compatible = "intel,me", .data = X86_SYSCON_ME },
 164         { }
 165 };
 166
 167 U_BOOT_DRIVER(syscon_intel_me) = {
 168         .name = "intel_me_syscon",
 169         .id = UCLASS_SYSCON,
 170         .of_match = ivybridge_syscon_ids,
 171 };