arch/x86/cpu/ivybridge/pci.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008,2009
   4  * Graeme Russ, <graeme.russ@gmail.com>
   5  *
   6  * (C) Copyright 2002
   7  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <pci.h>
  14 #include <asm/pci.h>
  15 #include <asm/arch/bd82x6x.h>
  16 #include <asm/arch/pch.h>
  17
  18 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
  19                               struct pci_config_table *table)
  20 {
  21         u8 secondary;
  22
  23         hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
  24         if (secondary != 0)
  25                 pci_hose_scan_bus(hose, secondary);
  26 }
  27
  28 static struct pci_config_table pci_ivybridge_config_table[] = {
  29         /* vendor, device, class, bus, dev, func */
  30         { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
  31                 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
  32         {}
  33 };
  34
  35 void board_pci_setup_hose(struct pci_controller *hose)
  36 {
  37         hose->config_table = pci_ivybridge_config_table;
  38         hose->first_busno = 0;
  39         hose->last_busno = 0;
  40
  41         /* PCI memory space */
  42         pci_set_region(hose->regions + 0,
  43                        CONFIG_PCI_MEM_BUS,
  44                        CONFIG_PCI_MEM_PHYS,
  45                        CONFIG_PCI_MEM_SIZE,
  46                        PCI_REGION_MEM);
  47
  48         /* PCI IO space */
  49         pci_set_region(hose->regions + 1,
  50                        CONFIG_PCI_IO_BUS,
  51                        CONFIG_PCI_IO_PHYS,
  52                        CONFIG_PCI_IO_SIZE,
  53                        PCI_REGION_IO);
  54
  55         pci_set_region(hose->regions + 2,
  56                        CONFIG_PCI_PREF_BUS,
  57                        CONFIG_PCI_PREF_PHYS,
  58                        CONFIG_PCI_PREF_SIZE,
  59                        PCI_REGION_PREFETCH);
  60
  61         hose->region_count = 3;
  62 }
  63
  64 int board_pci_pre_scan(struct pci_controller *hose)
  65 {
  66         pci_dev_t dev;
  67         u16 reg16;
  68
  69         bd82x6x_init();
  70
  71         reg16 = 0xff;
  72         dev = PCH_DEV;
  73         reg16 = pci_read_config16(dev, PCI_COMMAND);
  74         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  75         pci_write_config16(dev, PCI_COMMAND, reg16);
  76
  77         /*
  78         * Clear non-reserved bits in status register.
  79         */
  80         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  81         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  82         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  83
  84         pci_write_bar32(hose, dev, 0, 0xf0000000);
  85
  86         return 0;
  87 }
  88
  89 int board_pci_post_scan(struct pci_controller *hose)
  90 {
  91         int ret;
  92
  93         ret = bd82x6x_init_pci_devices();
  94         if (ret) {
  95                 printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
  96                 return ret;
  97         }
  98
  99         return 0;
 100 }