arch/x86/cpu/ivybridge/usb_ehci.c

   1 /*
   2  * From Coreboot
   3  * Copyright (C) 2008-2009 coresystems GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/pci.h>
  11 #include <asm/arch/pch.h>
  12
  13 void bd82x6x_usb_ehci_init(pci_dev_t dev)
  14 {
  15         u32 reg32;
  16
  17         /* Disable Wake on Disconnect in RMH */
  18         reg32 = readl(RCB_REG(0x35b0));
  19         reg32 |= 0x22;
  20         writel(reg32, RCB_REG(0x35b0));
  21
  22         debug("EHCI: Setting up controller.. ");
  23         reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
  24         reg32 |= PCI_COMMAND_MASTER;
  25         /* reg32 |= PCI_COMMAND_SERR; */
  26         x86_pci_write_config32(dev, PCI_COMMAND, reg32);
  27
  28         debug("done.\n");
  29 }