arch/x86/cpu/qemu/qemu.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <pci.h>
   9 #include <qfw.h>
  10 #include <asm/irq.h>
  11 #include <asm/post.h>
  12 #include <asm/processor.h>
  13 #include <asm/arch/device.h>
  14 #include <asm/arch/qemu.h>
  15
  16 static bool i440fx;
  17
  18 #ifdef CONFIG_QFW
  19
  20 /* on x86, the qfw registers are all IO ports */
  21 #define FW_CONTROL_PORT 0x510
  22 #define FW_DATA_PORT            0x511
  23 #define FW_DMA_PORT_LOW 0x514
  24 #define FW_DMA_PORT_HIGH        0x518
  25
  26 static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
  27                 uint32_t size, void *address)
  28 {
  29         uint32_t i = 0;
  30         uint8_t *data = address;
  31
  32         /*
  33          * writting FW_CFG_INVALID will cause read operation to resume at
  34          * last offset, otherwise read will start at offset 0
  35          *
  36          * Note: on platform where the control register is IO port, the
  37          * endianness is little endian.
  38          */
  39         if (entry != FW_CFG_INVALID)
  40                 outw(cpu_to_le16(entry), FW_CONTROL_PORT);
  41
  42         /* the endianness of data register is string-preserving */
  43         while (size--)
  44                 data[i++] = inb(FW_DATA_PORT);
  45 }
  46
  47 static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
  48 {
  49         /* the DMA address register is big endian */
  50         outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
  51
  52         while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
  53                 __asm__ __volatile__ ("pause");
  54 }
  55
  56 static struct fw_cfg_arch_ops fwcfg_x86_ops = {
  57         .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
  58         .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
  59 };
  60 #endif
  61
  62 static void enable_pm_piix(void)
  63 {
  64         u8 en;
  65         u16 cmd;
  66
  67         /* Set the PM I/O base */
  68         pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
  69
  70         /* Enable access to the PM I/O space */
  71         pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
  72         cmd |= PCI_COMMAND_IO;
  73         pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
  74
  75         /* PM I/O Space Enable (PMIOSE) */
  76         pci_read_config8(PIIX_PM, PMREGMISC, &en);
  77         en |= PMIOSE;
  78         pci_write_config8(PIIX_PM, PMREGMISC, en);
  79 }
  80
  81 static void enable_pm_ich9(void)
  82 {
  83         /* Set the PM I/O base */
  84         pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
  85 }
  86
  87 static void qemu_chipset_init(void)
  88 {
  89         u16 device, xbcs;
  90         int pam, i;
  91
  92         /*
  93          * i440FX and Q35 chipset have different PAM register offset, but with
  94          * the same bitfield layout. Here we determine the offset based on its
  95          * PCI device ID.
  96          */
  97         pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
  98         i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
  99         pam = i440fx ? I440FX_PAM : Q35_PAM;
 100
 101         /*
 102          * Initialize Programmable Attribute Map (PAM) Registers
 103          *
 104          * Configure legacy segments C/D/E/F to system RAM
 105          */
 106         for (i = 0; i < PAM_NUM; i++)
 107                 pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
 108
 109         if (i440fx) {
 110                 /*
 111                  * Enable legacy IDE I/O ports decode
 112                  *
 113                  * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
 114                  * However Linux ata_piix driver does sanity check on these two
 115                  * registers to see whether legacy ports decode is turned on.
 116                  * This is to make Linux ata_piix driver happy.
 117                  */
 118                 pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
 119                 pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
 120
 121                 /* Enable I/O APIC */
 122                 pci_read_config16(PIIX_ISA, XBCS, &xbcs);
 123                 xbcs |= APIC_EN;
 124                 pci_write_config16(PIIX_ISA, XBCS, xbcs);
 125
 126                 enable_pm_piix();
 127         } else {
 128                 /* Configure PCIe ECAM base address */
 129                 pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
 130                                    CONFIG_PCIE_ECAM_BASE | BAR_EN);
 131
 132                 enable_pm_ich9();
 133         }
 134
 135 #ifdef CONFIG_QFW
 136         qemu_fwcfg_init(&fwcfg_x86_ops);
 137 #endif
 138 }
 139
 140 #if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
 141 int arch_cpu_init(void)
 142 {
 143         post_code(POST_CPU_INIT);
 144
 145         return x86_cpu_init_f();
 146 }
 147 #endif
 148
 149 #if !CONFIG_IS_ENABLED(EFI_STUB) && \
 150         !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
 151
 152 int checkcpu(void)
 153 {
 154         return 0;
 155 }
 156
 157 int print_cpuinfo(void)
 158 {
 159         post_code(POST_CPU_INFO);
 160         return default_print_cpuinfo();
 161 }
 162 #endif
 163
 164 void reset_cpu(ulong addr)
 165 {
 166         /* cold reset */
 167         x86_full_reset();
 168 }
 169
 170 int arch_early_init_r(void)
 171 {
 172         qemu_chipset_init();
 173
 174         return 0;
 175 }
 176
 177 #ifdef CONFIG_GENERATE_MP_TABLE
 178 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
 179 {
 180         u8 irq;
 181
 182         if (i440fx) {
 183                 /*
 184                  * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
 185                  * connected to I/O APIC INTPIN#16-19. Instead they are routed
 186                  * to an irq number controled by the PIRQ routing register.
 187                  */
 188                 pci_read_config8(PCI_BDF(bus, dev, func),
 189                                  PCI_INTERRUPT_LINE, &irq);
 190         } else {
 191                 /*
 192                  * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
 193                  * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
 194                  */
 195                 irq = pirq < 8 ? pirq + 16 : pirq + 12;
 196         }
 197
 198         return irq;
 199 }
 200 #endif