arch/x86/cpu/quark/quark.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <mmc.h>
   9 #include <asm/cache.h>
  10 #include <asm/io.h>
  11 #include <asm/ioapic.h>
  12 #include <asm/irq.h>
  13 #include <asm/mrccache.h>
  14 #include <asm/mtrr.h>
  15 #include <asm/pci.h>
  16 #include <asm/post.h>
  17 #include <asm/arch/device.h>
  18 #include <asm/arch/msg_port.h>
  19 #include <asm/arch/quark.h>
  20
  21 static void quark_setup_mtrr(void)
  22 {
  23         u32 base, mask;
  24         int i;
  25
  26         disable_caches();
  27
  28         /* mark the VGA RAM area as uncacheable */
  29         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
  30                        MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  31         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
  32                        MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  33
  34         /* mark other fixed range areas as cacheable */
  35         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
  36                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  37         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
  38                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  39         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
  40                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  41         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
  42                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  43         for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
  44                 msg_port_write(MSG_PORT_HOST_BRIDGE, i,
  45                                MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  46
  47         /* variable range MTRR#0: ROM area */
  48         mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
  49         base = CONFIG_SYS_TEXT_BASE & mask;
  50         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
  51                        base | MTRR_TYPE_WRBACK);
  52         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
  53                        mask | MTRR_PHYS_MASK_VALID);
  54
  55         /* variable range MTRR#1: eSRAM area */
  56         mask = ~(ESRAM_SIZE - 1);
  57         base = CONFIG_ESRAM_BASE & mask;
  58         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
  59                        base | MTRR_TYPE_WRBACK);
  60         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
  61                        mask | MTRR_PHYS_MASK_VALID);
  62
  63         /* enable both variable and fixed range MTRRs */
  64         msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
  65                        MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
  66
  67         enable_caches();
  68 }
  69
  70 static void quark_setup_bars(void)
  71 {
  72         /* GPIO - D31:F0:R44h */
  73         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  74                                    CONFIG_GPIO_BASE | IO_BAR_EN);
  75
  76         /* ACPI PM1 Block - D31:F0:R48h */
  77         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  78                                    CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  79
  80         /* GPE0 - D31:F0:R4Ch */
  81         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  82                                    CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  83
  84         /* WDT - D31:F0:R84h */
  85         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  86                                    CONFIG_WDT_BASE | IO_BAR_EN);
  87
  88         /* RCBA - D31:F0:RF0h */
  89         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  90                                    CONFIG_RCBA_BASE | MEM_BAR_EN);
  91
  92         /* ACPI P Block - Msg Port 04:R70h */
  93         msg_port_write(MSG_PORT_RMU, PBLK_BA,
  94                        CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  95
  96         /* SPI DMA - Msg Port 04:R7Ah */
  97         msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  98                        CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  99
 100         /* PCIe ECAM */
 101         msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
 102                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
 103         msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
 104                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
 105 }
 106
 107 static void quark_pcie_early_init(void)
 108 {
 109         /*
 110          * Step1: Assert PCIe signal PERST#
 111          *
 112          * The CPU interface to the PERST# signal is platform dependent.
 113          * Call the board-specific codes to perform this task.
 114          */
 115         board_assert_perst();
 116
 117         /* Step2: PHY common lane reset */
 118         msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
 119         /* wait 1 ms for PHY common lane reset */
 120         mdelay(1);
 121
 122         /* Step3: PHY sideband interface reset and controller main reset */
 123         msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
 124                              PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
 125         /* wait 80ms for PLL to lock */
 126         mdelay(80);
 127
 128         /* Step4: Controller sideband interface reset */
 129         msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
 130         /* wait 20ms for controller sideband interface reset */
 131         mdelay(20);
 132
 133         /* Step5: De-assert PERST# */
 134         board_deassert_perst();
 135
 136         /* Step6: Controller primary interface reset */
 137         msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
 138
 139         /* Mixer Load Lane 0 */
 140         msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
 141                             (1 << 6) | (1 << 7));
 142
 143         /* Mixer Load Lane 1 */
 144         msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
 145                             (1 << 6) | (1 << 7));
 146 }
 147
 148 static void quark_usb_early_init(void)
 149 {
 150         /* The sequence below comes from Quark firmware writer guide */
 151
 152         msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
 153                                 1 << 1, (1 << 6) | (1 << 7));
 154
 155         msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
 156                                 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
 157
 158         msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
 159
 160         msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
 161
 162         msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
 163                                 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
 164
 165         msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
 166
 167         msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
 168 }
 169
 170 static void quark_thermal_early_init(void)
 171 {
 172         /* The sequence below comes from Quark firmware writer guide */
 173
 174         /* thermal sensor mode config */
 175         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
 176                                 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
 177         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
 178                                 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
 179                                 (1 << 12), 1 << 9);
 180         msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
 181         msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
 182         msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
 183         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
 184         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
 185         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
 186                                 (1 << 8) | (1 << 9), 1 << 8);
 187         msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
 188         msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
 189                                 0x7ff800, 0xc8 << 11);
 190
 191         /* thermal monitor catastrophic trip set point (105 celsius) */
 192         msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
 193
 194         /* thermal monitor catastrophic trip clear point (0 celsius) */
 195         msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
 196
 197         /* take thermal sensor out of reset */
 198         msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
 199
 200         /* enable thermal monitor */
 201         msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
 202
 203         /* lock all thermal configuration */
 204         msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
 205 }
 206
 207 static void quark_enable_legacy_seg(void)
 208 {
 209         msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
 210                          HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
 211 }
 212
 213 int arch_cpu_init(void)
 214 {
 215         int ret;
 216
 217         post_code(POST_CPU_INIT);
 218
 219         ret = x86_cpu_init_f();
 220         if (ret)
 221                 return ret;
 222
 223         /*
 224          * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
 225          * are accessed indirectly via the message port and not the traditional
 226          * MSR mechanism. Only UC, WT and WB cache types are supported.
 227          */
 228         quark_setup_mtrr();
 229
 230         /*
 231          * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
 232          * which need be initialized with suggested values
 233          */
 234         quark_setup_bars();
 235
 236         /* Initialize USB2 PHY */
 237         quark_usb_early_init();
 238
 239         /* Initialize thermal sensor */
 240         quark_thermal_early_init();
 241
 242         /* Turn on legacy segments (A/B/E/F) decode to system RAM */
 243         quark_enable_legacy_seg();
 244
 245         return 0;
 246 }
 247
 248 int arch_cpu_init_dm(void)
 249 {
 250         /*
 251          * Initialize PCIe controller
 252          *
 253          * Quark SoC holds the PCIe controller in reset following a power on.
 254          * U-Boot needs to release the PCIe controller from reset. The PCIe
 255          * controller (D23:F0/F1) will not be visible in PCI configuration
 256          * space and any access to its PCI configuration registers will cause
 257          * system hang while it is held in reset.
 258          */
 259         quark_pcie_early_init();
 260
 261         return 0;
 262 }
 263
 264 int checkcpu(void)
 265 {
 266         return 0;
 267 }
 268
 269 int print_cpuinfo(void)
 270 {
 271         post_code(POST_CPU_INFO);
 272         return default_print_cpuinfo();
 273 }
 274
 275 static void quark_pcie_init(void)
 276 {
 277         u32 val;
 278
 279         /* PCIe upstream non-posted & posted request size */
 280         qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
 281                                    CCFG_UPRS | CCFG_UNRS);
 282         qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
 283                                    CCFG_UPRS | CCFG_UNRS);
 284
 285         /* PCIe packet fast transmit mode (IPF) */
 286         qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
 287         qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
 288
 289         /* PCIe message bus idle counter (SBIC) */
 290         qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
 291         val |= MBC_SBIC;
 292         qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
 293         qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
 294         val |= MBC_SBIC;
 295         qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
 296 }
 297
 298 static void quark_usb_init(void)
 299 {
 300         u32 bar;
 301
 302         /* Change USB EHCI packet buffer OUT/IN threshold */
 303         qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
 304         writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
 305
 306         /* Disable USB device interrupts */
 307         qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
 308         writel(0x7f, bar + USBD_INT_MASK);
 309         writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
 310         writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
 311 }
 312
 313 static void quark_irq_init(void)
 314 {
 315         struct quark_rcba *rcba;
 316         u32 base;
 317
 318         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
 319         base &= ~MEM_BAR_EN;
 320         rcba = (struct quark_rcba *)base;
 321
 322         /*
 323          * Route Quark PCI device interrupt pin to PIRQ
 324          *
 325          * Route device#23's INTA/B/C/D to PIRQA/B/C/D
 326          * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
 327          */
 328         writew(PIRQC, &rcba->rmu_ir);
 329         writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
 330                &rcba->d23_ir);
 331         writew(PIRQD, &rcba->core_ir);
 332         writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
 333                &rcba->d20d21_ir);
 334 }
 335
 336 int arch_early_init_r(void)
 337 {
 338         quark_pcie_init();
 339
 340         quark_usb_init();
 341
 342         quark_irq_init();
 343
 344         return 0;
 345 }
 346
 347 int arch_misc_init(void)
 348 {
 349 #ifdef CONFIG_ENABLE_MRC_CACHE
 350         /*
 351          * We intend not to check any return value here, as even MRC cache
 352          * is not saved successfully, it is not a severe error that will
 353          * prevent system from continuing to boot.
 354          */
 355         mrccache_save();
 356 #endif
 357
 358         /* Assign a unique I/O APIC ID */
 359         io_apic_set_id(1);
 360
 361         return 0;
 362 }
 363
 364 void board_final_cleanup(void)
 365 {
 366         struct quark_rcba *rcba;
 367         u32 base, val;
 368
 369         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
 370         base &= ~MEM_BAR_EN;
 371         rcba = (struct quark_rcba *)base;
 372
 373         /* Initialize 'Component ID' to zero */
 374         val = readl(&rcba->esd);
 375         val &= ~0xff0000;
 376         writel(val, &rcba->esd);
 377
 378         /* Lock HMBOUND for security */
 379         msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
 380
 381         return;
 382 }