arch/x86/cpu/quark/quark.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <mmc.h>
   9 #include <netdev.h>
  10 #include <phy.h>
  11 #include <asm/io.h>
  12 #include <asm/irq.h>
  13 #include <asm/pci.h>
  14 #include <asm/post.h>
  15 #include <asm/processor.h>
  16 #include <asm/arch/device.h>
  17 #include <asm/arch/msg_port.h>
  18 #include <asm/arch/quark.h>
  19
  20 static struct pci_device_id mmc_supported[] = {
  21         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
  22 };
  23
  24 /*
  25  * TODO:
  26  *
  27  * This whole routine should be removed until we fully convert the ICH SPI
  28  * driver to DM and make use of DT to pass the bios control register offset
  29  */
  30 static void unprotect_spi_flash(void)
  31 {
  32         u32 bc;
  33
  34         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
  35         bc |= 0x1;      /* unprotect the flash */
  36         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
  37 }
  38
  39 static void quark_setup_bars(void)
  40 {
  41         /* GPIO - D31:F0:R44h */
  42         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  43                                    CONFIG_GPIO_BASE | IO_BAR_EN);
  44
  45         /* ACPI PM1 Block - D31:F0:R48h */
  46         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  47                                    CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  48
  49         /* GPE0 - D31:F0:R4Ch */
  50         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  51                                    CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  52
  53         /* WDT - D31:F0:R84h */
  54         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  55                                    CONFIG_WDT_BASE | IO_BAR_EN);
  56
  57         /* RCBA - D31:F0:RF0h */
  58         qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  59                                    CONFIG_RCBA_BASE | MEM_BAR_EN);
  60
  61         /* ACPI P Block - Msg Port 04:R70h */
  62         msg_port_write(MSG_PORT_RMU, PBLK_BA,
  63                        CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  64
  65         /* SPI DMA - Msg Port 04:R7Ah */
  66         msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  67                        CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  68
  69         /* PCIe ECAM */
  70         msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
  71                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  72         msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
  73                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  74 }
  75
  76 static void quark_pcie_early_init(void)
  77 {
  78         u32 pcie_cfg;
  79
  80         /*
  81          * Step1: Assert PCIe signal PERST#
  82          *
  83          * The CPU interface to the PERST# signal is platform dependent.
  84          * Call the board-specific codes to perform this task.
  85          */
  86         board_assert_perst();
  87
  88         /* Step2: PHY common lane reset */
  89         pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
  90         pcie_cfg |= PCIE_PHY_LANE_RST;
  91         msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
  92         /* wait 1 ms for PHY common lane reset */
  93         mdelay(1);
  94
  95         /* Step3: PHY sideband interface reset and controller main reset */
  96         pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
  97         pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
  98         msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
  99         /* wait 80ms for PLL to lock */
 100         mdelay(80);
 101
 102         /* Step4: Controller sideband interface reset */
 103         pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
 104         pcie_cfg |= PCIE_CTLR_SB_RST;
 105         msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
 106         /* wait 20ms for controller sideband interface reset */
 107         mdelay(20);
 108
 109         /* Step5: De-assert PERST# */
 110         board_deassert_perst();
 111
 112         /* Step6: Controller primary interface reset */
 113         pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
 114         pcie_cfg |= PCIE_CTLR_PRI_RST;
 115         msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
 116
 117         /* Mixer Load Lane 0 */
 118         pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0);
 119         pcie_cfg &= ~((1 << 6) | (1 << 7));
 120         msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg);
 121
 122         /* Mixer Load Lane 1 */
 123         pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1);
 124         pcie_cfg &= ~((1 << 6) | (1 << 7));
 125         msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg);
 126 }
 127
 128 static void quark_usb_early_init(void)
 129 {
 130         u32 usb;
 131
 132         /* The sequence below comes from Quark firmware writer guide */
 133
 134         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT);
 135         usb &= ~(1 << 1);
 136         usb |= ((1 << 6) | (1 << 7));
 137         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, usb);
 138
 139         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_COMPBG);
 140         usb &= ~((1 << 8) | (1 << 9));
 141         usb |= ((1 << 7) | (1 << 10));
 142         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_COMPBG, usb);
 143
 144         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
 145         usb |= (1 << 29);
 146         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
 147
 148         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
 149         usb |= (1 << 1);
 150         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
 151
 152         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
 153         usb &= ~((1 << 3) | (1 << 4) | (1 << 5));
 154         usb |= (1 << 6);
 155         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
 156
 157         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
 158         usb &= ~(1 << 29);
 159         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
 160
 161         usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
 162         usb |= (1 << 24);
 163         msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
 164 }
 165
 166 static void quark_enable_legacy_seg(void)
 167 {
 168         u32 hmisc2;
 169
 170         hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
 171         hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
 172         msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
 173 }
 174
 175 int arch_cpu_init(void)
 176 {
 177         int ret;
 178
 179         post_code(POST_CPU_INIT);
 180 #ifdef CONFIG_SYS_X86_TSC_TIMER
 181         timer_set_base(rdtsc());
 182 #endif
 183
 184         ret = x86_cpu_init_f();
 185         if (ret)
 186                 return ret;
 187
 188         /*
 189          * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
 190          * which need be initialized with suggested values
 191          */
 192         quark_setup_bars();
 193
 194         /*
 195          * Initialize PCIe controller
 196          *
 197          * Quark SoC holds the PCIe controller in reset following a power on.
 198          * U-Boot needs to release the PCIe controller from reset. The PCIe
 199          * controller (D23:F0/F1) will not be visible in PCI configuration
 200          * space and any access to its PCI configuration registers will cause
 201          * system hang while it is held in reset.
 202          */
 203         quark_pcie_early_init();
 204
 205         /* Initialize USB2 PHY */
 206         quark_usb_early_init();
 207
 208         /* Turn on legacy segments (A/B/E/F) decode to system RAM */
 209         quark_enable_legacy_seg();
 210
 211         unprotect_spi_flash();
 212
 213         return 0;
 214 }
 215
 216 int print_cpuinfo(void)
 217 {
 218         post_code(POST_CPU_INFO);
 219         return default_print_cpuinfo();
 220 }
 221
 222 void reset_cpu(ulong addr)
 223 {
 224         /* cold reset */
 225         x86_full_reset();
 226 }
 227
 228 int cpu_mmc_init(bd_t *bis)
 229 {
 230         return pci_mmc_init("Quark SDHCI", mmc_supported,
 231                             ARRAY_SIZE(mmc_supported));
 232 }
 233
 234 int cpu_eth_init(bd_t *bis)
 235 {
 236         u32 base;
 237         int ret0, ret1;
 238
 239         qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
 240         ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
 241
 242         qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
 243         ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
 244
 245         if (ret0 < 0 && ret1 < 0)
 246                 return -1;
 247         else
 248                 return 0;
 249 }
 250
 251 void cpu_irq_init(void)
 252 {
 253         struct quark_rcba *rcba;
 254         u32 base;
 255
 256         qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
 257         base &= ~MEM_BAR_EN;
 258         rcba = (struct quark_rcba *)base;
 259
 260         /*
 261          * Route Quark PCI device interrupt pin to PIRQ
 262          *
 263          * Route device#23's INTA/B/C/D to PIRQA/B/C/D
 264          * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
 265          */
 266         writew(PIRQC, &rcba->rmu_ir);
 267         writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
 268                &rcba->d23_ir);
 269         writew(PIRQD, &rcba->core_ir);
 270         writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
 271                &rcba->d20d21_ir);
 272 }
 273
 274 int arch_misc_init(void)
 275 {
 276         return pirq_init();
 277 }