2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
15 #include <asm/arch/device.h>
16 #include <asm/arch/msg_port.h>
17 #include <asm/arch/quark.h>
19 static struct pci_device_id mmc_supported
[] = {
20 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_QRK_SDIO
},
26 * This whole routine should be removed until we fully convert the ICH SPI
27 * driver to DM and make use of DT to pass the bios control register offset
29 static void unprotect_spi_flash(void)
33 bc
= x86_pci_read_config32(QUARK_LEGACY_BRIDGE
, 0xd8);
34 bc
|= 0x1; /* unprotect the flash */
35 x86_pci_write_config32(QUARK_LEGACY_BRIDGE
, 0xd8, bc
);
38 static void quark_setup_bars(void)
40 /* GPIO - D31:F0:R44h */
41 pci_write_config_dword(QUARK_LEGACY_BRIDGE
, LB_GBA
,
42 CONFIG_GPIO_BASE
| IO_BAR_EN
);
44 /* ACPI PM1 Block - D31:F0:R48h */
45 pci_write_config_dword(QUARK_LEGACY_BRIDGE
, LB_PM1BLK
,
46 CONFIG_ACPI_PM1_BASE
| IO_BAR_EN
);
48 /* GPE0 - D31:F0:R4Ch */
49 pci_write_config_dword(QUARK_LEGACY_BRIDGE
, LB_GPE0BLK
,
50 CONFIG_ACPI_GPE0_BASE
| IO_BAR_EN
);
52 /* WDT - D31:F0:R84h */
53 pci_write_config_dword(QUARK_LEGACY_BRIDGE
, LB_WDTBA
,
54 CONFIG_WDT_BASE
| IO_BAR_EN
);
56 /* RCBA - D31:F0:RF0h */
57 pci_write_config_dword(QUARK_LEGACY_BRIDGE
, LB_RCBA
,
58 CONFIG_RCBA_BASE
| MEM_BAR_EN
);
60 /* ACPI P Block - Msg Port 04:R70h */
61 msg_port_write(MSG_PORT_RMU
, PBLK_BA
,
62 CONFIG_ACPI_PBLK_BASE
| IO_BAR_EN
);
64 /* SPI DMA - Msg Port 04:R7Ah */
65 msg_port_write(MSG_PORT_RMU
, SPI_DMA_BA
,
66 CONFIG_SPI_DMA_BASE
| IO_BAR_EN
);
69 msg_port_write(MSG_PORT_MEM_ARBITER
, AEC_CTRL
,
70 CONFIG_PCIE_ECAM_BASE
| MEM_BAR_EN
);
71 msg_port_write(MSG_PORT_HOST_BRIDGE
, HEC_REG
,
72 CONFIG_PCIE_ECAM_BASE
| MEM_BAR_EN
);
75 static void quark_enable_legacy_seg(void)
79 hmisc2
= msg_port_read(MSG_PORT_HOST_BRIDGE
, HMISC2
);
80 hmisc2
|= (HMISC2_SEGE
| HMISC2_SEGF
| HMISC2_SEGAB
);
81 msg_port_write(MSG_PORT_HOST_BRIDGE
, HMISC2
, hmisc2
);
84 int arch_cpu_init(void)
86 struct pci_controller
*hose
;
89 post_code(POST_CPU_INIT
);
90 #ifdef CONFIG_SYS_X86_TSC_TIMER
91 timer_set_base(rdtsc());
94 ret
= x86_cpu_init_f();
98 ret
= pci_early_init_hose(&hose
);
103 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
104 * which need be initialized with suggested values
108 /* Turn on legacy segments (A/B/E/F) decode to system RAM */
109 quark_enable_legacy_seg();
111 unprotect_spi_flash();
116 int print_cpuinfo(void)
118 post_code(POST_CPU_INFO
);
119 return default_print_cpuinfo();
122 void reset_cpu(ulong addr
)
128 int cpu_mmc_init(bd_t
*bis
)
130 return pci_mmc_init("Quark SDHCI", mmc_supported
,
131 ARRAY_SIZE(mmc_supported
));
134 int cpu_eth_init(bd_t
*bis
)
139 pci_read_config_dword(QUARK_EMAC0
, PCI_BASE_ADDRESS_0
, &base
);
140 ret0
= designware_initialize(base
, PHY_INTERFACE_MODE_RMII
);
142 pci_read_config_dword(QUARK_EMAC1
, PCI_BASE_ADDRESS_0
, &base
);
143 ret1
= designware_initialize(base
, PHY_INTERFACE_MODE_RMII
);
145 if (ret0
< 0 && ret1
< 0)