2 * (C) Copyright 2010,2011
3 * Graeme Russ, <graeme.russ@gmail.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor-flags.h>
27 #include <asm/ic/sc520.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 struct sc520_sdram_info
{
38 static void sc520_sizemem(void);
39 static void sc520_set_dram_timing(void);
40 static void sc520_set_dram_refresh_rate(void);
41 static void sc520_enable_dram_refresh(void);
42 static void sc520_enable_sdram(void);
43 #if CONFIG_SYS_SDRAM_ECC_ENABLE
44 static void sc520_enable_ecc(void)
50 sc520_set_dram_timing();
51 sc520_set_dram_refresh_rate();
52 sc520_enable_dram_refresh();
54 #if CONFIG_SYS_SDRAM_ECC_ENABLE
61 static inline void sc520_dummy_write(void)
63 writew(0x0000, CACHELINESZ
);
65 static inline void sc520_issue_sdram_op_mode_select(u8 command
)
67 writeb(command
, &sc520_mmcr
->drcctl
);
71 static inline int check_long(u32 test_long
)
74 u8 tmp_byte
= (u8
)(test_long
& 0x000000ff);
76 for (i
= 1; i
< 4; i
++) {
77 if ((u8
)((test_long
>> (i
* 8)) & 0x000000ff) != tmp_byte
)
84 static inline int write_and_test(u32 data
, u32 address
)
86 writel(data
, address
);
87 if (readl(address
) == data
)
93 static void sc520_enable_sdram(void)
97 /* Enable Writes, Caching and Code Execution to SDRAM */
98 par_config
= readl(&sc520_mmcr
->par
[3]);
99 par_config
&= ~(SC520_PAR_EXEC_DIS
|
100 SC520_PAR_CACHE_DIS
|
101 SC520_PAR_WRITE_DIS
);
102 writel(par_config
, &sc520_mmcr
->par
[3]);
104 par_config
= readl(&sc520_mmcr
->par
[4]);
105 par_config
&= ~(SC520_PAR_EXEC_DIS
|
106 SC520_PAR_CACHE_DIS
|
107 SC520_PAR_WRITE_DIS
);
108 writel(par_config
, &sc520_mmcr
->par
[4]);
111 static void sc520_set_dram_timing(void)
115 #if defined CONFIG_SYS_SDRAM_DRCTMCTL
116 /* just have your hardware designer _GIVE_ you what you need here! */
117 drctmctl
= CONFIG_SYS_SDRAM_DRCTMCTL
;
119 switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY
) {
131 switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY
) {
147 switch (CONFIG_SYS_SDRAM_CAS_LATENCY
) {
156 writeb(drctmctl
, &sc520_mmcr
->drctmctl
);
158 /* Issue load mode register command */
159 sc520_issue_sdram_op_mode_select(0x03);
162 static void sc520_set_dram_refresh_rate(void)
166 drctl
= readb(&sc520_mmcr
->drcctl
);
169 switch (CONFIG_SYS_SDRAM_REFRESH_RATE
) {
184 writeb(drctl
, &sc520_mmcr
->drcctl
);
187 static void sc520_enable_dram_refresh(void)
191 drctl
= readb(&sc520_mmcr
->drcctl
);
192 drctl
&= 0x30; /* keep refresh rate */
193 drctl
|= 0x08; /* enable refresh, normal mode */
195 writeb(drctl
, &sc520_mmcr
->drcctl
);
198 static void sc520_get_bank_info(int bank
, struct sc520_sdram_info
*bank_info
)
210 bank_info
->banks
= 0x00;
211 bank_info
->columns
= 0x00;
212 bank_info
->rows
= 0x00;
213 bank_info
->size
= 0x00;
215 if ((bank
< 0) || (bank
> 3)) {
216 printf("Bad Bank ID\n");
220 /* Save configuration */
221 drcbendadr
= readl(&sc520_mmcr
->drcbendadr
);
222 drccfg
= readw(&sc520_mmcr
->drccfg
);
224 /* Setup SDRAM Bank to largest possible size */
225 writew(0x000b << (bank
* 4), &sc520_mmcr
->drccfg
);
227 /* Set ending address for this bank */
228 writel(0x000000ff << (bank
* 8), &sc520_mmcr
->drcbendadr
);
230 /* write col 11 wrap adr */
231 if (write_and_test(COL11_DATA
, COL11_ADR
) != 0)
232 goto restore_and_exit
;
234 /* write col 10 wrap adr */
235 if (write_and_test(COL10_DATA
, COL10_ADR
) != 0)
236 goto restore_and_exit
;
238 /* write col 9 wrap adr */
239 if (write_and_test(COL09_DATA
, COL09_ADR
) != 0)
240 goto restore_and_exit
;
242 /* write col 8 wrap adr */
243 if (write_and_test(COL08_DATA
, COL08_ADR
) != 0)
244 goto restore_and_exit
;
246 col_data
= readl(COL11_ADR
);
248 /* All four bytes in the read long must be the same */
249 if (check_long(col_data
) < 0)
250 goto restore_and_exit
;
252 if ((col_data
>= COL08_DATA
) && (col_data
<= COL11_DATA
))
253 columns
= (u8
)(col_data
& 0x000000ff);
255 goto restore_and_exit
;
257 /* write row 14 wrap adr */
258 if (write_and_test(ROW14_DATA
, ROW14_ADR
) != 0)
259 goto restore_and_exit
;
261 /* write row 13 wrap adr */
262 if (write_and_test(ROW13_DATA
, ROW13_ADR
) != 0)
263 goto restore_and_exit
;
265 /* write row 12 wrap adr */
266 if (write_and_test(ROW12_DATA
, ROW12_ADR
) != 0)
267 goto restore_and_exit
;
269 /* write row 11 wrap adr */
270 if (write_and_test(ROW11_DATA
, ROW11_ADR
) != 0)
271 goto restore_and_exit
;
273 if (write_and_test(ROW10_DATA
, ROW10_ADR
) != 0)
274 goto restore_and_exit
;
277 * read data @ row 12 wrap adr to determine number of banks,
278 * and read data @ row 14 wrap adr to determine number of rows.
279 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
280 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
281 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
283 row_data
= readl(ROW12_ADR
);
285 /* All four bytes in the read long must be the same */
286 if (check_long(row_data
) != 0)
287 goto restore_and_exit
;
300 goto restore_and_exit
;
303 row_data
= readl(ROW14_ADR
);
305 /* All four bytes in the read long must be the same */
306 if (check_long(row_data
) != 0)
307 goto restore_and_exit
;
314 rows
= (u8
)(row_data
& 0x000000ff);
318 goto restore_and_exit
;
321 bank_info
->banks
= banks
;
322 bank_info
->columns
= columns
;
323 bank_info
->rows
= rows
;
325 if ((bank_info
->banks
!= 0) &&
326 (bank_info
->columns
!= 0) &&
327 (bank_info
->rows
!= 0)) {
328 bank_info
->size
= bank_info
->rows
;
329 bank_info
->size
>>= (11 - bank_info
->columns
);
334 /* Restore configuration */
335 writel(drcbendadr
, &sc520_mmcr
->drcbendadr
);
336 writew(drccfg
, &sc520_mmcr
->drccfg
);
339 static void sc520_setup_sizemem(void)
343 /* Disable write buffer */
344 writeb(0x00, &sc520_mmcr
->dbctl
);
347 writeb(0x00, &sc520_mmcr
->eccctl
);
349 /* Set slowest SDRAM timing */
350 writeb(0x1e, &sc520_mmcr
->drctmctl
);
352 /* Issue a NOP to all SDRAM banks */
353 sc520_issue_sdram_op_mode_select(0x01);
355 /* Delay for 100 microseconds */
358 /* Issue 'All Banks Precharge' command */
359 sc520_issue_sdram_op_mode_select(0x02);
361 /* Issue 2 'Auto Refresh Enable' command */
362 sc520_issue_sdram_op_mode_select(0x04);
365 /* Issue 'Load Mode Register' command */
366 sc520_issue_sdram_op_mode_select(0x03);
368 /* Issue 8 more 'Auto Refresh Enable' commands */
369 sc520_issue_sdram_op_mode_select(0x04);
370 for (i
= 0; i
< 7; i
++)
373 /* Set control register to 'Normal Mode' */
374 writeb(0x00, &sc520_mmcr
->drcctl
);
377 static void sc520_sizemem(void)
379 struct sc520_sdram_info sdram_info
[4];
380 u8 bank_config
= 0x00;
383 u32 drcbendadr
= 0x00000000;
386 /* Use PARs to disable caching of maximum allowable 256MB SDRAM */
387 writel(SC520_SDRAM1_PAR
| SC520_PAR_CACHE_DIS
, &sc520_mmcr
->par
[3]);
388 writel(SC520_SDRAM2_PAR
| SC520_PAR_CACHE_DIS
, &sc520_mmcr
->par
[4]);
390 sc520_setup_sizemem();
394 /* Size each SDRAM bank */
395 for (i
= 0; i
<= 3; i
++) {
396 sc520_get_bank_info(i
, &sdram_info
[i
]);
398 if (sdram_info
[i
].banks
!= 0) {
399 /* Update Configuration register */
400 bank_config
= sdram_info
[i
].columns
- 8;
402 if (sdram_info
[i
].banks
== 4)
405 drccfg
|= bank_config
<< (i
* 4);
407 /* Update End Address register */
408 end_addr
+= sdram_info
[i
].size
;
409 drcbendadr
|= (end_addr
| 0x80) << (i
* 8);
411 gd
->ram_size
+= sdram_info
[i
].size
<< 22;
414 /* Issue 'All Banks Precharge' command */
415 sc520_issue_sdram_op_mode_select(0x02);
417 /* Set control register to 'Normal Mode' */
418 writeb(0x00, &sc520_mmcr
->drcctl
);
421 writel(drcbendadr
, &sc520_mmcr
->drcbendadr
);
422 writew(drccfg
, &sc520_mmcr
->drccfg
);
424 /* Clear PARs preventing caching of SDRAM */
425 writel(0x00000000, &sc520_mmcr
->par
[3]);
426 writel(0x00000000, &sc520_mmcr
->par
[4]);
429 #if CONFIG_SYS_SDRAM_ECC_ENABLE
430 static void sc520_enable_ecc(void)
432 /* A nominal memory test: just a byte at each address line */
447 /* clear all ram with a memset */
456 /* enable read, write buffers */
461 /* enable NMI mapping for ECC */
479 ulong dram_present
= 0x00000000;
482 * We read-back the configuration of the dram
483 * controller that the assembly code wrote
485 dram_ctrl
= readl(&sc520_mmcr
->drcbendadr
);
487 gd
->bd
->bi_dram
[0].start
= 0;
488 if (dram_ctrl
& 0x80) {
490 gd
->bd
->bi_dram
[1].start
= (dram_ctrl
& 0x7f) << 22;
491 dram_present
= gd
->bd
->bi_dram
[1].start
;
492 gd
->bd
->bi_dram
[0].size
= gd
->bd
->bi_dram
[1].start
;
494 gd
->bd
->bi_dram
[0].size
= 0;
495 gd
->bd
->bi_dram
[1].start
= gd
->bd
->bi_dram
[0].start
;
498 if (dram_ctrl
& 0x8000) {
500 gd
->bd
->bi_dram
[2].start
= (dram_ctrl
& 0x7f00) << 14;
501 dram_present
= gd
->bd
->bi_dram
[2].start
;
502 gd
->bd
->bi_dram
[1].size
= gd
->bd
->bi_dram
[2].start
-
503 gd
->bd
->bi_dram
[1].start
;
505 gd
->bd
->bi_dram
[1].size
= 0;
506 gd
->bd
->bi_dram
[2].start
= gd
->bd
->bi_dram
[1].start
;
509 if (dram_ctrl
& 0x800000) {
511 gd
->bd
->bi_dram
[3].start
= (dram_ctrl
& 0x7f0000) << 6;
512 dram_present
= gd
->bd
->bi_dram
[3].start
;
513 gd
->bd
->bi_dram
[2].size
= gd
->bd
->bi_dram
[3].start
-
514 gd
->bd
->bi_dram
[2].start
;
516 gd
->bd
->bi_dram
[2].size
= 0;
517 gd
->bd
->bi_dram
[3].start
= gd
->bd
->bi_dram
[2].start
;
520 if (dram_ctrl
& 0x80000000) {
522 dram_present
= (dram_ctrl
& 0x7f000000) >> 2;
523 gd
->bd
->bi_dram
[3].size
= dram_present
-
524 gd
->bd
->bi_dram
[3].start
;
526 gd
->bd
->bi_dram
[3].size
= 0;
529 gd
->ram_size
= dram_present
;