]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/x86/dts/chromebook_link.dts
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[people/ms/u-boot.git] / arch / x86 / dts / chromebook_link.dts
1 /dts-v1/;
2
3 /include/ "skeleton.dtsi"
4 /include/ "serial.dtsi"
5 /include/ "rtc.dtsi"
6
7 / {
8 model = "Google Link";
9 compatible = "google,link", "intel,celeron-ivybridge";
10
11 aliases {
12 spi0 = "/pci/pch/spi";
13 };
14
15 config {
16 silent_console = <0>;
17 };
18
19 gpioa {
20 compatible = "intel,ich6-gpio";
21 u-boot,dm-pre-reloc;
22 reg = <0 0x10>;
23 bank-name = "A";
24 };
25
26 gpiob {
27 compatible = "intel,ich6-gpio";
28 u-boot,dm-pre-reloc;
29 reg = <0x30 0x10>;
30 bank-name = "B";
31 };
32
33 gpioc {
34 compatible = "intel,ich6-gpio";
35 u-boot,dm-pre-reloc;
36 reg = <0x40 0x10>;
37 bank-name = "C";
38 };
39
40 chosen {
41 stdout-path = "/serial";
42 };
43
44 spd {
45 compatible = "memory-spd";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 elpida_4Gb_1600_x16 {
49 reg = <0>;
50 data = [92 10 0b 03 04 19 02 02
51 03 52 01 08 0a 00 fe 00
52 69 78 69 3c 69 11 18 81
53 20 08 3c 3c 01 40 83 81
54 00 00 00 00 00 00 00 00
55 00 00 00 00 00 00 00 00
56 00 00 00 00 00 00 00 00
57 00 00 00 00 0f 11 42 00
58 00 00 00 00 00 00 00 00
59 00 00 00 00 00 00 00 00
60 00 00 00 00 00 00 00 00
61 00 00 00 00 00 00 00 00
62 00 00 00 00 00 00 00 00
63 00 00 00 00 00 00 00 00
64 00 00 00 00 00 02 fe 00
65 11 52 00 00 00 07 7f 37
66 45 42 4a 32 30 55 47 36
67 45 42 55 30 2d 47 4e 2d
68 46 20 30 20 02 fe 00 00
69 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00
71 00 00 00 00 00 00 00 00
72 00 00 00 00 00 00 00 00
73 00 00 00 00 00 00 00 00
74 00 00 00 00 00 00 00 00
75 00 00 00 00 00 00 00 00
76 00 00 00 00 00 00 00 00
77 00 00 00 00 00 00 00 00
78 00 00 00 00 00 00 00 00
79 00 00 00 00 00 00 00 00
80 00 00 00 00 00 00 00 00
81 00 00 00 00 00 00 00 00];
82 };
83 samsung_4Gb_1600_1.35v_x16 {
84 reg = <1>;
85 data = [92 11 0b 03 04 19 02 02
86 03 11 01 08 0a 00 fe 00
87 69 78 69 3c 69 11 18 81
88 f0 0a 3c 3c 01 40 83 01
89 00 80 00 00 00 00 00 00
90 00 00 00 00 00 00 00 00
91 00 00 00 00 00 00 00 00
92 00 00 00 00 0f 11 02 00
93 00 00 00 00 00 00 00 00
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 00 00 00 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 80 ce 01
100 00 00 00 00 00 00 6a 04
101 4d 34 37 31 42 35 36 37
102 34 42 48 30 2d 59 4b 30
103 20 20 00 00 80 ce 00 00
104 00 00 00 00 00 00 00 00
105 00 00 00 00 00 00 00 00
106 00 00 00 00 00 00 00 00
107 00 00 00 00 00 00 00 00
108 00 00 00 00 00 00 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00];
117 };
118 micron_4Gb_1600_1.35v_x16 {
119 reg = <2>;
120 data = [92 11 0b 03 04 19 02 02
121 03 11 01 08 0a 00 fe 00
122 69 78 69 3c 69 11 18 81
123 20 08 3c 3c 01 40 83 05
124 00 00 00 00 00 00 00 00
125 00 00 00 00 00 00 00 00
126 00 00 00 00 00 00 00 00
127 00 00 00 00 0f 01 02 00
128 00 00 00 00 00 00 00 00
129 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 00 00 00 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 80 2c 00
135 00 00 00 00 00 00 ad 75
136 34 4b 54 46 32 35 36 36
137 34 48 5a 2d 31 47 36 45
138 31 20 45 31 80 2c 00 00
139 00 00 00 00 00 00 00 00
140 00 00 00 00 00 00 00 00
141 00 00 00 00 00 00 00 00
142 ff ff ff ff ff ff ff ff
143 ff ff ff ff ff ff ff ff
144 ff ff ff ff ff ff ff ff
145 ff ff ff ff ff ff ff ff
146 ff ff ff ff ff ff ff ff
147 ff ff ff ff ff ff ff ff
148 ff ff ff ff ff ff ff ff
149 ff ff ff ff ff ff ff ff
150 ff ff ff ff ff ff ff ff
151 ff ff ff ff ff ff ff ff];
152 };
153 };
154
155 pci {
156 compatible = "intel,pci-ivybridge", "pci-x86";
157 #address-cells = <3>;
158 #size-cells = <2>;
159 u-boot,dm-pre-reloc;
160 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
161 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
162 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
163 sata {
164 compatible = "intel,pantherpoint-ahci";
165 intel,sata-mode = "ahci";
166 intel,sata-port-map = <1>;
167 intel,sata-port0-gen3-tx = <0x00880a7f>;
168 };
169
170 gma {
171 compatible = "intel,gma";
172 intel,dp_hotplug = <0 0 0x06>;
173 intel,panel-port-select = <1>;
174 intel,panel-power-cycle-delay = <6>;
175 intel,panel-power-up-delay = <2000>;
176 intel,panel-power-down-delay = <500>;
177 intel,panel-power-backlight-on-delay = <2000>;
178 intel,panel-power-backlight-off-delay = <2000>;
179 intel,cpu-backlight = <0x00000200>;
180 intel,pch-backlight = <0x04000000>;
181 };
182
183 pch {
184 reg = <0x0000f800 0 0 0 0>;
185 compatible = "intel,bd82x6x", "intel,pch";
186 u-boot,dm-pre-reloc;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 gen-dec = <0x800 0xfc 0x900 0xfc>;
190 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
191 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
192 0x80 0x80 0x80 0x80>;
193 intel,gpi-routing = <0 0 0 0 0 0 0 2
194 1 0 0 0 0 0 0 0>;
195 /* Enable EC SMI source */
196 intel,alt-gp-smi-enable = <0x0100>;
197 spi {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 compatible = "intel,ich-spi";
201 spi-flash@0 {
202 #size-cells = <1>;
203 #address-cells = <1>;
204 reg = <0>;
205 compatible = "winbond,w25q64",
206 "spi-flash";
207 memory-map = <0xff800000 0x00800000>;
208 rw-mrc-cache {
209 label = "rw-mrc-cache";
210 reg = <0x003e0000 0x00010000>;
211 type = "wiped";
212 wipe-value = [ff];
213 };
214 };
215 };
216
217 lpc {
218 compatible = "intel,bd82x6x-lpc";
219 #address-cells = <1>;
220 #size-cells = <0>;
221 cros-ec@200 {
222 compatible = "google,cros-ec";
223 reg = <0x204 1 0x200 1 0x880 0x80>;
224
225 /*
226 * Describes the flash memory within
227 * the EC
228 */
229 #address-cells = <1>;
230 #size-cells = <1>;
231 flash@8000000 {
232 reg = <0x08000000 0x20000>;
233 erase-value = <0xff>;
234 };
235 };
236 };
237 };
238 };
239
240 microcode {
241 update@0 {
242 #include "microcode/m12306a9_0000001b.dtsi"
243 };
244 };
245
246 };