arch/x86/dts/minnowmax.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "serial.dtsi"
  14 /include/ "rtc.dtsi"
  15 /include/ "tsc_timer.dtsi"
  16
  17 / {
  18         model = "Intel Minnowboard Max";
  19         compatible = "intel,minnowmax", "intel,baytrail";
  20
  21         aliases {
  22                 serial0 = &serial;
  23                 spi0 = &spi;
  24         };
  25
  26         config {
  27                 silent_console = <0>;
  28         };
  29
  30         pch_pinctrl {
  31                 compatible = "intel,x86-pinctrl";
  32                 io-base = <0x4c>;
  33
  34                 /* GPIO E0 */
  35                 soc_gpio_s5_0@0 {
  36                         gpio-offset = <0x80 0>;
  37                         pad-offset = <0x1d0>;
  38                         mode-gpio;
  39                         output-value = <0>;
  40                         direction = <PIN_OUTPUT>;
  41                 };
  42
  43                 /* GPIO E1 */
  44                 soc_gpio_s5_1@0 {
  45                         gpio-offset = <0x80 1>;
  46                         pad-offset = <0x210>;
  47                         mode-gpio;
  48                         output-value = <0>;
  49                         direction = <PIN_OUTPUT>;
  50                 };
  51
  52                 /* GPIO E2 */
  53                 soc_gpio_s5_2@0 {
  54                         gpio-offset = <0x80 2>;
  55                         pad-offset = <0x1e0>;
  56                         mode-gpio;
  57                         output-value = <0>;
  58                         direction = <PIN_OUTPUT>;
  59                 };
  60
  61                 pin_usb_host_en0@0 {
  62                         gpio-offset = <0x80 8>;
  63                         pad-offset = <0x260>;
  64                         mode-gpio;
  65                         output-value = <1>;
  66                         direction = <PIN_OUTPUT>;
  67                 };
  68
  69                 pin_usb_host_en1@0 {
  70                         gpio-offset = <0x80 9>;
  71                         pad-offset = <0x250>;
  72                         mode-gpio;
  73                         output-value = <1>;
  74                         direction = <PIN_OUTPUT>;
  75                 };
  76         };
  77
  78         gpioa {
  79                 compatible = "intel,ich6-gpio";
  80                 u-boot,dm-pre-reloc;
  81                 reg = <0 0x20>;
  82                 bank-name = "A";
  83         };
  84
  85         gpiob {
  86                 compatible = "intel,ich6-gpio";
  87                 u-boot,dm-pre-reloc;
  88                 reg = <0x20 0x20>;
  89                 bank-name = "B";
  90         };
  91
  92         gpioc {
  93                 compatible = "intel,ich6-gpio";
  94                 u-boot,dm-pre-reloc;
  95                 reg = <0x40 0x20>;
  96                 bank-name = "C";
  97         };
  98
  99         gpiod {
 100                 compatible = "intel,ich6-gpio";
 101                 u-boot,dm-pre-reloc;
 102                 reg = <0x60 0x20>;
 103                 bank-name = "D";
 104         };
 105
 106         gpioe {
 107                 compatible = "intel,ich6-gpio";
 108                 u-boot,dm-pre-reloc;
 109                 reg = <0x80 0x20>;
 110                 bank-name = "E";
 111         };
 112
 113         gpiof {
 114                 compatible = "intel,ich6-gpio";
 115                 u-boot,dm-pre-reloc;
 116                 reg = <0xA0 0x20>;
 117                 bank-name = "F";
 118         };
 119
 120         chosen {
 121                 stdout-path = "/serial";
 122         };
 123
 124         cpus {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127
 128                 cpu@0 {
 129                         device_type = "cpu";
 130                         compatible = "intel,baytrail-cpu";
 131                         reg = <0>;
 132                         intel,apic-id = <0>;
 133                 };
 134
 135                 cpu@1 {
 136                         device_type = "cpu";
 137                         compatible = "intel,baytrail-cpu";
 138                         reg = <1>;
 139                         intel,apic-id = <4>;
 140                 };
 141
 142         };
 143
 144         pci {
 145                 compatible = "intel,pci-baytrail", "pci-x86";
 146                 #address-cells = <3>;
 147                 #size-cells = <2>;
 148                 u-boot,dm-pre-reloc;
 149                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 150                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 151                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 152
 153                 pch@1f,0 {
 154                         reg = <0x0000f800 0 0 0 0>;
 155                         compatible = "pci8086,0f1c", "intel,pch9";
 156
 157                         irq-router {
 158                                 compatible = "intel,irq-router";
 159                                 intel,pirq-config = "ibase";
 160                                 intel,ibase-offset = <0x50>;
 161                                 intel,pirq-link = <8 8>;
 162                                 intel,pirq-mask = <0xdee0>;
 163                                 intel,pirq-routing = <
 164                                         /* BayTrail PCI devices */
 165                                         PCI_BDF(0, 2, 0) INTA PIRQA
 166                                         PCI_BDF(0, 3, 0) INTA PIRQA
 167                                         PCI_BDF(0, 16, 0) INTA PIRQA
 168                                         PCI_BDF(0, 17, 0) INTA PIRQA
 169                                         PCI_BDF(0, 18, 0) INTA PIRQA
 170                                         PCI_BDF(0, 19, 0) INTA PIRQA
 171                                         PCI_BDF(0, 20, 0) INTA PIRQA
 172                                         PCI_BDF(0, 21, 0) INTA PIRQA
 173                                         PCI_BDF(0, 22, 0) INTA PIRQA
 174                                         PCI_BDF(0, 23, 0) INTA PIRQA
 175                                         PCI_BDF(0, 24, 0) INTA PIRQA
 176                                         PCI_BDF(0, 24, 1) INTC PIRQC
 177                                         PCI_BDF(0, 24, 2) INTD PIRQD
 178                                         PCI_BDF(0, 24, 3) INTB PIRQB
 179                                         PCI_BDF(0, 24, 4) INTA PIRQA
 180                                         PCI_BDF(0, 24, 5) INTC PIRQC
 181                                         PCI_BDF(0, 24, 6) INTD PIRQD
 182                                         PCI_BDF(0, 24, 7) INTB PIRQB
 183                                         PCI_BDF(0, 26, 0) INTA PIRQA
 184                                         PCI_BDF(0, 27, 0) INTA PIRQA
 185                                         PCI_BDF(0, 28, 0) INTA PIRQA
 186                                         PCI_BDF(0, 28, 1) INTB PIRQB
 187                                         PCI_BDF(0, 28, 2) INTC PIRQC
 188                                         PCI_BDF(0, 28, 3) INTD PIRQD
 189                                         PCI_BDF(0, 29, 0) INTA PIRQA
 190                                         PCI_BDF(0, 30, 0) INTA PIRQA
 191                                         PCI_BDF(0, 30, 1) INTD PIRQD
 192                                         PCI_BDF(0, 30, 2) INTB PIRQB
 193                                         PCI_BDF(0, 30, 3) INTC PIRQC
 194                                         PCI_BDF(0, 30, 4) INTD PIRQD
 195                                         PCI_BDF(0, 30, 5) INTB PIRQB
 196                                         PCI_BDF(0, 31, 3) INTB PIRQB
 197
 198                                         /*
 199                                          * PCIe root ports downstream
 200                                          * interrupts
 201                                          */
 202                                         PCI_BDF(1, 0, 0) INTA PIRQA
 203                                         PCI_BDF(1, 0, 0) INTB PIRQB
 204                                         PCI_BDF(1, 0, 0) INTC PIRQC
 205                                         PCI_BDF(1, 0, 0) INTD PIRQD
 206                                         PCI_BDF(2, 0, 0) INTA PIRQB
 207                                         PCI_BDF(2, 0, 0) INTB PIRQC
 208                                         PCI_BDF(2, 0, 0) INTC PIRQD
 209                                         PCI_BDF(2, 0, 0) INTD PIRQA
 210                                         PCI_BDF(3, 0, 0) INTA PIRQC
 211                                         PCI_BDF(3, 0, 0) INTB PIRQD
 212                                         PCI_BDF(3, 0, 0) INTC PIRQA
 213                                         PCI_BDF(3, 0, 0) INTD PIRQB
 214                                         PCI_BDF(4, 0, 0) INTA PIRQD
 215                                         PCI_BDF(4, 0, 0) INTB PIRQA
 216                                         PCI_BDF(4, 0, 0) INTC PIRQB
 217                                         PCI_BDF(4, 0, 0) INTD PIRQC
 218                                 >;
 219                         };
 220
 221                         spi: spi {
 222                                 #address-cells = <1>;
 223                                 #size-cells = <0>;
 224                                 compatible = "intel,ich-spi";
 225                                 spi-flash@0 {
 226                                         #address-cells = <1>;
 227                                         #size-cells = <1>;
 228                                         reg = <0>;
 229                                         compatible = "stmicro,n25q064a",
 230                                                 "spi-flash";
 231                                         memory-map = <0xff800000 0x00800000>;
 232                                         rw-mrc-cache {
 233                                                 label = "rw-mrc-cache";
 234                                                 reg = <0x006f0000 0x00010000>;
 235                                         };
 236                                 };
 237                         };
 238                 };
 239         };
 240
 241         fsp {
 242                 compatible = "intel,baytrail-fsp";
 243                 fsp,mrc-init-tseg-size = <0>;
 244                 fsp,mrc-init-mmio-size = <0x800>;
 245                 fsp,mrc-init-spd-addr1 = <0xa0>;
 246                 fsp,mrc-init-spd-addr2 = <0xa2>;
 247                 fsp,emmc-boot-mode = <2>;
 248                 fsp,enable-sdio;
 249                 fsp,enable-sdcard;
 250                 fsp,enable-hsuart1;
 251                 fsp,enable-spi;
 252                 fsp,enable-sata;
 253                 fsp,sata-mode = <1>;
 254                 fsp,enable-lpe;
 255                 fsp,lpss-sio-enable-pci-mode;
 256                 fsp,enable-dma0;
 257                 fsp,enable-dma1;
 258                 fsp,enable-i2c0;
 259                 fsp,enable-i2c1;
 260                 fsp,enable-i2c2;
 261                 fsp,enable-i2c3;
 262                 fsp,enable-i2c4;
 263                 fsp,enable-i2c5;
 264                 fsp,enable-i2c6;
 265                 fsp,enable-pwm0;
 266                 fsp,enable-pwm1;
 267                 fsp,igd-dvmt50-pre-alloc = <2>;
 268                 fsp,aperture-size = <2>;
 269                 fsp,gtt-size = <2>;
 270                 fsp,serial-debug-port-address = <0x3f8>;
 271                 fsp,serial-debug-port-type = <1>;
 272                 fsp,scc-enable-pci-mode;
 273                 fsp,os-selection = <4>;
 274                 fsp,emmc45-ddr50-enabled;
 275                 fsp,emmc45-retune-timer-value = <8>;
 276                 fsp,enable-igd;
 277                 fsp,enable-memory-down;
 278                 fsp,memory-down-params {
 279                         compatible = "intel,baytrail-fsp-mdp";
 280                         fsp,dram-speed = <1>;
 281                         fsp,dram-type = <1>;
 282                         fsp,dimm-0-enable;
 283                         fsp,dimm-width = <1>;
 284                         fsp,dimm-density = <2>;
 285                         fsp,dimm-bus-width = <3>;
 286                         fsp,dimm-sides = <0>;
 287                         fsp,dimm-tcl = <0xb>;
 288                         fsp,dimm-trpt-rcd = <0xb>;
 289                         fsp,dimm-twr = <0xc>;
 290                         fsp,dimm-twtr = <6>;
 291                         fsp,dimm-trrd = <6>;
 292                         fsp,dimm-trtp = <6>;
 293                         fsp,dimm-tfaw = <0x14>;
 294                 };
 295         };
 296
 297         microcode {
 298                 update@0 {
 299 #include "microcode/m0130673322.dtsi"
 300                 };
 301                 update@1 {
 302 #include "microcode/m0130679901.dtsi"
 303                 };
 304         };
 305
 306 };