2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
33 #include <asm/stacktrace.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
42 #include <asm/unwind.h>
44 #include "perf_event.h"
46 struct x86_pmu x86_pmu __read_mostly
;
48 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key
);
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX
]
60 [PERF_COUNT_HW_CACHE_OP_MAX
]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
68 u64
x86_perf_event_update(struct perf_event
*event
)
70 struct hw_perf_event
*hwc
= &event
->hw
;
71 int shift
= 64 - x86_pmu
.cntval_bits
;
72 u64 prev_raw_count
, new_raw_count
;
76 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
80 * Careful: an NMI might modify the previous event value.
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
87 prev_raw_count
= local64_read(&hwc
->prev_count
);
88 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
90 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
91 new_raw_count
) != prev_raw_count
)
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
99 * Careful, not all hw sign-extends above the physical width
102 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
105 local64_add(delta
, &event
->count
);
106 local64_sub(delta
, &hwc
->period_left
);
108 return new_raw_count
;
112 * Find and validate any extra registers to set up.
114 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
116 struct hw_perf_event_extra
*reg
;
117 struct extra_reg
*er
;
119 reg
= &event
->hw
.extra_reg
;
121 if (!x86_pmu
.extra_regs
)
124 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
125 if (er
->event
!= (config
& er
->config_mask
))
127 if (event
->attr
.config1
& ~er
->valid_mask
)
129 /* Check if the extra msrs can be safely accessed*/
130 if (!er
->extra_msr_access
)
134 reg
->config
= event
->attr
.config1
;
141 static atomic_t active_events
;
142 static atomic_t pmc_refcount
;
143 static DEFINE_MUTEX(pmc_reserve_mutex
);
145 #ifdef CONFIG_X86_LOCAL_APIC
147 static bool reserve_pmc_hardware(void)
151 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
156 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
164 for (i
--; i
>= 0; i
--)
165 release_evntsel_nmi(x86_pmu_config_addr(i
));
167 i
= x86_pmu
.num_counters
;
170 for (i
--; i
>= 0; i
--)
171 release_perfctr_nmi(x86_pmu_event_addr(i
));
176 static void release_pmc_hardware(void)
180 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i
));
182 release_evntsel_nmi(x86_pmu_config_addr(i
));
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
193 static bool check_hw_exists(void)
195 u64 val
, val_fail
= -1, val_new
= ~0;
196 int i
, reg
, reg_fail
= -1, ret
= 0;
201 * Check to see if the BIOS enabled any of the counters, if so
204 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
205 reg
= x86_pmu_config_addr(i
);
206 ret
= rdmsrl_safe(reg
, &val
);
209 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
218 if (x86_pmu
.num_counters_fixed
) {
219 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
220 ret
= rdmsrl_safe(reg
, &val
);
223 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
224 if (val
& (0x03 << i
*4)) {
233 * If all the counters are enabled, the below test will always
234 * fail. The tools will also become useless in this scenario.
235 * Just fail and disable the hardware counters.
238 if (reg_safe
== -1) {
244 * Read the current value, change it and read it back to see if it
245 * matches, this is needed to detect certain hardware emulators
246 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
248 reg
= x86_pmu_event_addr(reg_safe
);
249 if (rdmsrl_safe(reg
, &val
))
252 ret
= wrmsrl_safe(reg
, val
);
253 ret
|= rdmsrl_safe(reg
, &val_new
);
254 if (ret
|| val
!= val_new
)
258 * We still allow the PMU driver to operate:
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
280 static void hw_perf_event_destroy(struct perf_event
*event
)
282 x86_release_hardware();
283 atomic_dec(&active_events
);
286 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
288 hw_perf_event_destroy(event
);
290 /* undo the lbr/bts event accounting */
291 x86_del_exclusive(x86_lbr_exclusive_lbr
);
294 static inline int x86_pmu_initialized(void)
296 return x86_pmu
.handle_irq
!= NULL
;
300 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
302 struct perf_event_attr
*attr
= &event
->attr
;
303 unsigned int cache_type
, cache_op
, cache_result
;
306 config
= attr
->config
;
308 cache_type
= (config
>> 0) & 0xff;
309 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
311 cache_type
= array_index_nospec(cache_type
, PERF_COUNT_HW_CACHE_MAX
);
313 cache_op
= (config
>> 8) & 0xff;
314 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
316 cache_op
= array_index_nospec(cache_op
, PERF_COUNT_HW_CACHE_OP_MAX
);
318 cache_result
= (config
>> 16) & 0xff;
319 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
321 cache_result
= array_index_nospec(cache_result
, PERF_COUNT_HW_CACHE_RESULT_MAX
);
323 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
332 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
333 return x86_pmu_extra_regs(val
, event
);
336 int x86_reserve_hardware(void)
340 if (!atomic_inc_not_zero(&pmc_refcount
)) {
341 mutex_lock(&pmc_reserve_mutex
);
342 if (atomic_read(&pmc_refcount
) == 0) {
343 if (!reserve_pmc_hardware())
346 reserve_ds_buffers();
349 atomic_inc(&pmc_refcount
);
350 mutex_unlock(&pmc_reserve_mutex
);
356 void x86_release_hardware(void)
358 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex
);
366 * Check if we can create event of a certain type (that no conflicting events
369 int x86_add_exclusive(unsigned int what
)
374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
375 * LBR and BTS are still mutually exclusive.
377 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
380 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
381 mutex_lock(&pmc_reserve_mutex
);
382 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
383 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
386 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
387 mutex_unlock(&pmc_reserve_mutex
);
390 atomic_inc(&active_events
);
394 mutex_unlock(&pmc_reserve_mutex
);
398 void x86_del_exclusive(unsigned int what
)
400 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
403 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
404 atomic_dec(&active_events
);
407 int x86_setup_perfctr(struct perf_event
*event
)
409 struct perf_event_attr
*attr
= &event
->attr
;
410 struct hw_perf_event
*hwc
= &event
->hw
;
413 if (!is_sampling_event(event
)) {
414 hwc
->sample_period
= x86_pmu
.max_period
;
415 hwc
->last_period
= hwc
->sample_period
;
416 local64_set(&hwc
->period_left
, hwc
->sample_period
);
419 if (attr
->type
== PERF_TYPE_RAW
)
420 return x86_pmu_extra_regs(event
->attr
.config
, event
);
422 if (attr
->type
== PERF_TYPE_HW_CACHE
)
423 return set_ext_hw_attr(hwc
, event
);
425 if (attr
->config
>= x86_pmu
.max_events
)
428 attr
->config
= array_index_nospec((unsigned long)attr
->config
, x86_pmu
.max_events
);
433 config
= x86_pmu
.event_map(attr
->config
);
444 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
445 !attr
->freq
&& hwc
->sample_period
== 1) {
446 /* BTS is not supported by this architecture. */
447 if (!x86_pmu
.bts_active
)
450 /* BTS is currently only allowed for user-mode. */
451 if (!attr
->exclude_kernel
)
454 /* disallow bts if conflicting events are present */
455 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
458 event
->destroy
= hw_perf_lbr_event_destroy
;
461 hwc
->config
|= config
;
467 * check that branch_sample_type is compatible with
468 * settings needed for precise_ip > 1 which implies
469 * using the LBR to capture ALL taken branches at the
470 * priv levels of the measurement
472 static inline int precise_br_compat(struct perf_event
*event
)
474 u64 m
= event
->attr
.branch_sample_type
;
477 /* must capture all branches */
478 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
481 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
483 if (!event
->attr
.exclude_user
)
484 b
|= PERF_SAMPLE_BRANCH_USER
;
486 if (!event
->attr
.exclude_kernel
)
487 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
490 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
496 int x86_pmu_max_precise(void)
500 /* Support for constant skid */
501 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
504 /* Support for IP fixup */
505 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
508 if (x86_pmu
.pebs_prec_dist
)
514 int x86_pmu_hw_config(struct perf_event
*event
)
516 if (event
->attr
.precise_ip
) {
517 int precise
= x86_pmu_max_precise();
519 if (event
->attr
.precise_ip
> precise
)
522 /* There's no sense in having PEBS for non sampling events: */
523 if (!is_sampling_event(event
))
527 * check that PEBS LBR correction does not conflict with
528 * whatever the user is asking with attr->branch_sample_type
530 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
531 u64
*br_type
= &event
->attr
.branch_sample_type
;
533 if (has_branch_stack(event
)) {
534 if (!precise_br_compat(event
))
537 /* branch_sample_type is compatible */
541 * user did not specify branch_sample_type
543 * For PEBS fixups, we capture all
544 * the branches at the priv level of the
547 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
549 if (!event
->attr
.exclude_user
)
550 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
552 if (!event
->attr
.exclude_kernel
)
553 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
557 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
558 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
562 * (keep 'enabled' bit clear for now)
564 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
567 * Count user and OS events unless requested not to
569 if (!event
->attr
.exclude_user
)
570 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
571 if (!event
->attr
.exclude_kernel
)
572 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
574 if (event
->attr
.type
== PERF_TYPE_RAW
)
575 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
577 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
578 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
579 event
->attr
.sample_period
)
583 return x86_setup_perfctr(event
);
587 * Setup the hardware configuration for a given attr_type
589 static int __x86_pmu_event_init(struct perf_event
*event
)
593 if (!x86_pmu_initialized())
596 err
= x86_reserve_hardware();
600 atomic_inc(&active_events
);
601 event
->destroy
= hw_perf_event_destroy
;
604 event
->hw
.last_cpu
= -1;
605 event
->hw
.last_tag
= ~0ULL;
608 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
609 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
611 return x86_pmu
.hw_config(event
);
614 void x86_pmu_disable_all(void)
616 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
619 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
622 if (!test_bit(idx
, cpuc
->active_mask
))
624 rdmsrl(x86_pmu_config_addr(idx
), val
);
625 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
627 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
628 wrmsrl(x86_pmu_config_addr(idx
), val
);
633 * There may be PMI landing after enabled=0. The PMI hitting could be before or
636 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
637 * It will not be re-enabled in the NMI handler again, because enabled=0. After
638 * handling the NMI, disable_all will be called, which will not change the
639 * state either. If PMI hits after disable_all, the PMU is already disabled
640 * before entering NMI handler. The NMI handler will not change the state
643 * So either situation is harmless.
645 static void x86_pmu_disable(struct pmu
*pmu
)
647 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
649 if (!x86_pmu_initialized())
659 x86_pmu
.disable_all();
662 void x86_pmu_enable_all(int added
)
664 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
667 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
668 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
670 if (!test_bit(idx
, cpuc
->active_mask
))
673 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
677 static struct pmu pmu
;
679 static inline int is_x86_event(struct perf_event
*event
)
681 return event
->pmu
== &pmu
;
685 * Event scheduler state:
687 * Assign events iterating over all events and counters, beginning
688 * with events with least weights first. Keep the current iterator
689 * state in struct sched_state.
693 int event
; /* event index */
694 int counter
; /* counter index */
695 int unassigned
; /* number of events to be assigned left */
696 int nr_gp
; /* number of GP counters used */
697 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
700 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
701 #define SCHED_STATES_MAX 2
708 struct event_constraint
**constraints
;
709 struct sched_state state
;
710 struct sched_state saved
[SCHED_STATES_MAX
];
714 * Initialize interator that runs through all events and counters.
716 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
717 int num
, int wmin
, int wmax
, int gpmax
)
721 memset(sched
, 0, sizeof(*sched
));
722 sched
->max_events
= num
;
723 sched
->max_weight
= wmax
;
724 sched
->max_gp
= gpmax
;
725 sched
->constraints
= constraints
;
727 for (idx
= 0; idx
< num
; idx
++) {
728 if (constraints
[idx
]->weight
== wmin
)
732 sched
->state
.event
= idx
; /* start with min weight */
733 sched
->state
.weight
= wmin
;
734 sched
->state
.unassigned
= num
;
737 static void perf_sched_save_state(struct perf_sched
*sched
)
739 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
742 sched
->saved
[sched
->saved_states
] = sched
->state
;
743 sched
->saved_states
++;
746 static bool perf_sched_restore_state(struct perf_sched
*sched
)
748 if (!sched
->saved_states
)
751 sched
->saved_states
--;
752 sched
->state
= sched
->saved
[sched
->saved_states
];
754 /* continue with next counter: */
755 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
761 * Select a counter for the current event to schedule. Return true on
764 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
766 struct event_constraint
*c
;
769 if (!sched
->state
.unassigned
)
772 if (sched
->state
.event
>= sched
->max_events
)
775 c
= sched
->constraints
[sched
->state
.event
];
776 /* Prefer fixed purpose counters */
777 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
778 idx
= INTEL_PMC_IDX_FIXED
;
779 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
780 if (!__test_and_set_bit(idx
, sched
->state
.used
))
785 /* Grab the first unused counter starting with idx */
786 idx
= sched
->state
.counter
;
787 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
788 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
789 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
799 sched
->state
.counter
= idx
;
802 perf_sched_save_state(sched
);
807 static bool perf_sched_find_counter(struct perf_sched
*sched
)
809 while (!__perf_sched_find_counter(sched
)) {
810 if (!perf_sched_restore_state(sched
))
818 * Go through all unassigned events and find the next one to schedule.
819 * Take events with the least weight first. Return true on success.
821 static bool perf_sched_next_event(struct perf_sched
*sched
)
823 struct event_constraint
*c
;
825 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
830 sched
->state
.event
++;
831 if (sched
->state
.event
>= sched
->max_events
) {
833 sched
->state
.event
= 0;
834 sched
->state
.weight
++;
835 if (sched
->state
.weight
> sched
->max_weight
)
838 c
= sched
->constraints
[sched
->state
.event
];
839 } while (c
->weight
!= sched
->state
.weight
);
841 sched
->state
.counter
= 0; /* start with first counter */
847 * Assign a counter for each event.
849 int perf_assign_events(struct event_constraint
**constraints
, int n
,
850 int wmin
, int wmax
, int gpmax
, int *assign
)
852 struct perf_sched sched
;
854 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
857 if (!perf_sched_find_counter(&sched
))
860 assign
[sched
.state
.event
] = sched
.state
.counter
;
861 } while (perf_sched_next_event(&sched
));
863 return sched
.state
.unassigned
;
865 EXPORT_SYMBOL_GPL(perf_assign_events
);
867 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
869 struct event_constraint
*c
;
870 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
871 struct perf_event
*e
;
872 int i
, wmin
, wmax
, unsched
= 0;
873 struct hw_perf_event
*hwc
;
875 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
877 if (x86_pmu
.start_scheduling
)
878 x86_pmu
.start_scheduling(cpuc
);
880 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
881 cpuc
->event_constraint
[i
] = NULL
;
882 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
883 cpuc
->event_constraint
[i
] = c
;
885 wmin
= min(wmin
, c
->weight
);
886 wmax
= max(wmax
, c
->weight
);
890 * fastpath, try to reuse previous register
892 for (i
= 0; i
< n
; i
++) {
893 hwc
= &cpuc
->event_list
[i
]->hw
;
894 c
= cpuc
->event_constraint
[i
];
900 /* constraint still honored */
901 if (!test_bit(hwc
->idx
, c
->idxmsk
))
904 /* not already used */
905 if (test_bit(hwc
->idx
, used_mask
))
908 __set_bit(hwc
->idx
, used_mask
);
910 assign
[i
] = hwc
->idx
;
915 int gpmax
= x86_pmu
.num_counters
;
918 * Do not allow scheduling of more than half the available
921 * This helps avoid counter starvation of sibling thread by
922 * ensuring at most half the counters cannot be in exclusive
923 * mode. There is no designated counters for the limits. Any
924 * N/2 counters can be used. This helps with events with
925 * specific counter constraints.
927 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
928 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
931 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
932 wmax
, gpmax
, assign
);
936 * In case of success (unsched = 0), mark events as committed,
937 * so we do not put_constraint() in case new events are added
938 * and fail to be scheduled
940 * We invoke the lower level commit callback to lock the resource
942 * We do not need to do all of this in case we are called to
943 * validate an event group (assign == NULL)
945 if (!unsched
&& assign
) {
946 for (i
= 0; i
< n
; i
++) {
947 e
= cpuc
->event_list
[i
];
948 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
949 if (x86_pmu
.commit_scheduling
)
950 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
953 for (i
= 0; i
< n
; i
++) {
954 e
= cpuc
->event_list
[i
];
956 * do not put_constraint() on comitted events,
957 * because they are good to go
959 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
963 * release events that failed scheduling
965 if (x86_pmu
.put_event_constraints
)
966 x86_pmu
.put_event_constraints(cpuc
, e
);
970 if (x86_pmu
.stop_scheduling
)
971 x86_pmu
.stop_scheduling(cpuc
);
973 return unsched
? -EINVAL
: 0;
977 * dogrp: true if must collect siblings events (group)
978 * returns total number of events and error code
980 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
982 struct perf_event
*event
;
985 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
987 /* current number of events already accepted */
990 if (is_x86_event(leader
)) {
993 cpuc
->event_list
[n
] = leader
;
999 for_each_sibling_event(event
, leader
) {
1000 if (!is_x86_event(event
) ||
1001 event
->state
<= PERF_EVENT_STATE_OFF
)
1007 cpuc
->event_list
[n
] = event
;
1013 static inline void x86_assign_hw_event(struct perf_event
*event
,
1014 struct cpu_hw_events
*cpuc
, int i
)
1016 struct hw_perf_event
*hwc
= &event
->hw
;
1018 hwc
->idx
= cpuc
->assign
[i
];
1019 hwc
->last_cpu
= smp_processor_id();
1020 hwc
->last_tag
= ++cpuc
->tags
[i
];
1022 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1023 hwc
->config_base
= 0;
1024 hwc
->event_base
= 0;
1025 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1026 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1027 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1028 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1030 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1031 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1032 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1037 * x86_perf_rdpmc_index - Return PMC counter used for event
1038 * @event: the perf_event to which the PMC counter was assigned
1040 * The counter assigned to this performance event may change if interrupts
1041 * are enabled. This counter should thus never be used while interrupts are
1042 * enabled. Before this function is used to obtain the assigned counter the
1043 * event should be checked for validity using, for example,
1044 * perf_event_read_local(), within the same interrupt disabled section in
1045 * which this counter is planned to be used.
1047 * Return: The index of the performance monitoring counter assigned to
1050 int x86_perf_rdpmc_index(struct perf_event
*event
)
1052 lockdep_assert_irqs_disabled();
1054 return event
->hw
.event_base_rdpmc
;
1057 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1058 struct cpu_hw_events
*cpuc
,
1061 return hwc
->idx
== cpuc
->assign
[i
] &&
1062 hwc
->last_cpu
== smp_processor_id() &&
1063 hwc
->last_tag
== cpuc
->tags
[i
];
1066 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1068 static void x86_pmu_enable(struct pmu
*pmu
)
1070 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1071 struct perf_event
*event
;
1072 struct hw_perf_event
*hwc
;
1073 int i
, added
= cpuc
->n_added
;
1075 if (!x86_pmu_initialized())
1081 if (cpuc
->n_added
) {
1082 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1084 * apply assignment obtained either from
1085 * hw_perf_group_sched_in() or x86_pmu_enable()
1087 * step1: save events moving to new counters
1089 for (i
= 0; i
< n_running
; i
++) {
1090 event
= cpuc
->event_list
[i
];
1094 * we can avoid reprogramming counter if:
1095 * - assigned same counter as last time
1096 * - running on same CPU as last time
1097 * - no other event has used the counter since
1099 if (hwc
->idx
== -1 ||
1100 match_prev_assignment(hwc
, cpuc
, i
))
1104 * Ensure we don't accidentally enable a stopped
1105 * counter simply because we rescheduled.
1107 if (hwc
->state
& PERF_HES_STOPPED
)
1108 hwc
->state
|= PERF_HES_ARCH
;
1110 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1114 * step2: reprogram moved events into new counters
1116 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1117 event
= cpuc
->event_list
[i
];
1120 if (!match_prev_assignment(hwc
, cpuc
, i
))
1121 x86_assign_hw_event(event
, cpuc
, i
);
1122 else if (i
< n_running
)
1125 if (hwc
->state
& PERF_HES_ARCH
)
1128 x86_pmu_start(event
, PERF_EF_RELOAD
);
1131 perf_events_lapic_init();
1137 x86_pmu
.enable_all(added
);
1140 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1143 * Set the next IRQ period, based on the hwc->period_left value.
1144 * To be called with the event disabled in hw:
1146 int x86_perf_event_set_period(struct perf_event
*event
)
1148 struct hw_perf_event
*hwc
= &event
->hw
;
1149 s64 left
= local64_read(&hwc
->period_left
);
1150 s64 period
= hwc
->sample_period
;
1151 int ret
= 0, idx
= hwc
->idx
;
1153 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1157 * If we are way outside a reasonable range then just skip forward:
1159 if (unlikely(left
<= -period
)) {
1161 local64_set(&hwc
->period_left
, left
);
1162 hwc
->last_period
= period
;
1166 if (unlikely(left
<= 0)) {
1168 local64_set(&hwc
->period_left
, left
);
1169 hwc
->last_period
= period
;
1173 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1175 if (unlikely(left
< 2))
1178 if (left
> x86_pmu
.max_period
)
1179 left
= x86_pmu
.max_period
;
1181 if (x86_pmu
.limit_period
)
1182 left
= x86_pmu
.limit_period(event
, left
);
1184 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1187 * The hw event starts counting from this event offset,
1188 * mark it to be able to extra future deltas:
1190 local64_set(&hwc
->prev_count
, (u64
)-left
);
1192 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1195 * Due to erratum on certan cpu we need
1196 * a second write to be sure the register
1197 * is updated properly
1199 if (x86_pmu
.perfctr_second_write
) {
1200 wrmsrl(hwc
->event_base
,
1201 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1204 perf_event_update_userpage(event
);
1209 void x86_pmu_enable_event(struct perf_event
*event
)
1211 if (__this_cpu_read(cpu_hw_events
.enabled
))
1212 __x86_pmu_enable_event(&event
->hw
,
1213 ARCH_PERFMON_EVENTSEL_ENABLE
);
1217 * Add a single event to the PMU.
1219 * The event is added to the group of enabled events
1220 * but only if it can be scehduled with existing events.
1222 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1224 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1225 struct hw_perf_event
*hwc
;
1226 int assign
[X86_PMC_IDX_MAX
];
1231 n0
= cpuc
->n_events
;
1232 ret
= n
= collect_events(cpuc
, event
, false);
1236 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1237 if (!(flags
& PERF_EF_START
))
1238 hwc
->state
|= PERF_HES_ARCH
;
1241 * If group events scheduling transaction was started,
1242 * skip the schedulability test here, it will be performed
1243 * at commit time (->commit_txn) as a whole.
1245 * If commit fails, we'll call ->del() on all events
1246 * for which ->add() was called.
1248 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1251 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1255 * copy new assignment, now we know it is possible
1256 * will be used by hw_perf_enable()
1258 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1262 * Commit the collect_events() state. See x86_pmu_del() and
1266 cpuc
->n_added
+= n
- n0
;
1267 cpuc
->n_txn
+= n
- n0
;
1271 * This is before x86_pmu_enable() will call x86_pmu_start(),
1272 * so we enable LBRs before an event needs them etc..
1282 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1284 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1285 int idx
= event
->hw
.idx
;
1287 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1290 if (WARN_ON_ONCE(idx
== -1))
1293 if (flags
& PERF_EF_RELOAD
) {
1294 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1295 x86_perf_event_set_period(event
);
1298 event
->hw
.state
= 0;
1300 cpuc
->events
[idx
] = event
;
1301 __set_bit(idx
, cpuc
->active_mask
);
1302 __set_bit(idx
, cpuc
->running
);
1303 x86_pmu
.enable(event
);
1304 perf_event_update_userpage(event
);
1307 void perf_event_print_debug(void)
1309 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1311 struct cpu_hw_events
*cpuc
;
1312 unsigned long flags
;
1315 if (!x86_pmu
.num_counters
)
1318 local_irq_save(flags
);
1320 cpu
= smp_processor_id();
1321 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1323 if (x86_pmu
.version
>= 2) {
1324 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1325 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1326 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1327 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1330 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1331 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1332 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1333 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1334 if (x86_pmu
.pebs_constraints
) {
1335 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1336 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1338 if (x86_pmu
.lbr_nr
) {
1339 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1340 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1343 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1345 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1346 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1347 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1349 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1351 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1352 cpu
, idx
, pmc_ctrl
);
1353 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1354 cpu
, idx
, pmc_count
);
1355 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1356 cpu
, idx
, prev_left
);
1358 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1359 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1361 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1362 cpu
, idx
, pmc_count
);
1364 local_irq_restore(flags
);
1367 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1369 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1370 struct hw_perf_event
*hwc
= &event
->hw
;
1372 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1373 x86_pmu
.disable(event
);
1374 cpuc
->events
[hwc
->idx
] = NULL
;
1375 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1376 hwc
->state
|= PERF_HES_STOPPED
;
1379 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1381 * Drain the remaining delta count out of a event
1382 * that we are disabling:
1384 x86_perf_event_update(event
);
1385 hwc
->state
|= PERF_HES_UPTODATE
;
1389 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1391 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1395 * event is descheduled
1397 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1400 * If we're called during a txn, we only need to undo x86_pmu.add.
1401 * The events never got scheduled and ->cancel_txn will truncate
1404 * XXX assumes any ->del() called during a TXN will only be on
1405 * an event added during that same TXN.
1407 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1411 * Not a TXN, therefore cleanup properly.
1413 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1415 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1416 if (event
== cpuc
->event_list
[i
])
1420 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1423 /* If we have a newly added event; make sure to decrease n_added. */
1424 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1427 if (x86_pmu
.put_event_constraints
)
1428 x86_pmu
.put_event_constraints(cpuc
, event
);
1430 /* Delete the array entry. */
1431 while (++i
< cpuc
->n_events
) {
1432 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1433 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1437 perf_event_update_userpage(event
);
1442 * This is after x86_pmu_stop(); so we disable LBRs after any
1443 * event can need them etc..
1449 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1451 struct perf_sample_data data
;
1452 struct cpu_hw_events
*cpuc
;
1453 struct perf_event
*event
;
1454 int idx
, handled
= 0;
1457 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1460 * Some chipsets need to unmask the LVTPC in a particular spot
1461 * inside the nmi handler. As a result, the unmasking was pushed
1462 * into all the nmi handlers.
1464 * This generic handler doesn't seem to have any issues where the
1465 * unmasking occurs so it was left at the top.
1467 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1469 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1470 if (!test_bit(idx
, cpuc
->active_mask
)) {
1472 * Though we deactivated the counter some cpus
1473 * might still deliver spurious interrupts still
1474 * in flight. Catch them:
1476 if (__test_and_clear_bit(idx
, cpuc
->running
))
1481 event
= cpuc
->events
[idx
];
1483 val
= x86_perf_event_update(event
);
1484 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1491 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1493 if (!x86_perf_event_set_period(event
))
1496 if (perf_event_overflow(event
, &data
, regs
))
1497 x86_pmu_stop(event
, 0);
1501 inc_irq_stat(apic_perf_irqs
);
1506 void perf_events_lapic_init(void)
1508 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1512 * Always use NMI for PMU
1514 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1518 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1525 * All PMUs/events that share this PMI handler should make sure to
1526 * increment active_events for their events.
1528 if (!atomic_read(&active_events
))
1531 start_clock
= sched_clock();
1532 ret
= x86_pmu
.handle_irq(regs
);
1533 finish_clock
= sched_clock();
1535 perf_sample_event_took(finish_clock
- start_clock
);
1539 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1541 struct event_constraint emptyconstraint
;
1542 struct event_constraint unconstrained
;
1544 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1546 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1549 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1550 cpuc
->kfree_on_online
[i
] = NULL
;
1551 if (x86_pmu
.cpu_prepare
)
1552 return x86_pmu
.cpu_prepare(cpu
);
1556 static int x86_pmu_dead_cpu(unsigned int cpu
)
1558 if (x86_pmu
.cpu_dead
)
1559 x86_pmu
.cpu_dead(cpu
);
1563 static int x86_pmu_online_cpu(unsigned int cpu
)
1565 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1568 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1569 kfree(cpuc
->kfree_on_online
[i
]);
1570 cpuc
->kfree_on_online
[i
] = NULL
;
1575 static int x86_pmu_starting_cpu(unsigned int cpu
)
1577 if (x86_pmu
.cpu_starting
)
1578 x86_pmu
.cpu_starting(cpu
);
1582 static int x86_pmu_dying_cpu(unsigned int cpu
)
1584 if (x86_pmu
.cpu_dying
)
1585 x86_pmu
.cpu_dying(cpu
);
1589 static void __init
pmu_check_apic(void)
1591 if (boot_cpu_has(X86_FEATURE_APIC
))
1595 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1596 pr_info("no hardware sampling interrupt available.\n");
1599 * If we have a PMU initialized but no APIC
1600 * interrupts, we cannot sample hardware
1601 * events (user-space has to fall back and
1602 * sample via a hrtimer based software event):
1604 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1608 static struct attribute_group x86_pmu_format_group __ro_after_init
= {
1614 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1615 * out of events_attr attributes.
1617 static void __init
filter_events(struct attribute
**attrs
)
1619 struct device_attribute
*d
;
1620 struct perf_pmu_events_attr
*pmu_attr
;
1624 for (i
= 0; attrs
[i
]; i
++) {
1625 d
= (struct device_attribute
*)attrs
[i
];
1626 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1628 if (pmu_attr
->event_str
)
1630 if (x86_pmu
.event_map(i
+ offset
))
1633 for (j
= i
; attrs
[j
]; j
++)
1634 attrs
[j
] = attrs
[j
+ 1];
1636 /* Check the shifted attr. */
1640 * event_map() is index based, the attrs array is organized
1641 * by increasing event index. If we shift the events, then
1642 * we need to compensate for the event_map(), otherwise
1643 * we are looking up the wrong event in the map
1649 /* Merge two pointer arrays */
1650 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1652 struct attribute
**new;
1655 for (j
= 0; a
&& a
[j
]; j
++)
1657 for (i
= 0; b
&& b
[i
]; i
++)
1661 new = kmalloc_array(j
, sizeof(struct attribute
*), GFP_KERNEL
);
1666 for (i
= 0; a
&& a
[i
]; i
++)
1668 for (i
= 0; b
&& b
[i
]; i
++)
1675 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1677 struct perf_pmu_events_attr
*pmu_attr
= \
1678 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1679 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1681 /* string trumps id */
1682 if (pmu_attr
->event_str
)
1683 return sprintf(page
, "%s", pmu_attr
->event_str
);
1685 return x86_pmu
.events_sysfs_show(page
, config
);
1687 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1689 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1692 struct perf_pmu_events_ht_attr
*pmu_attr
=
1693 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1696 * Report conditional events depending on Hyper-Threading.
1698 * This is overly conservative as usually the HT special
1699 * handling is not needed if the other CPU thread is idle.
1701 * Note this does not (and cannot) handle the case when thread
1702 * siblings are invisible, for example with virtualization
1703 * if they are owned by some other guest. The user tool
1704 * has to re-read when a thread sibling gets onlined later.
1706 return sprintf(page
, "%s",
1707 topology_max_smt_threads() > 1 ?
1708 pmu_attr
->event_str_ht
:
1709 pmu_attr
->event_str_noht
);
1712 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1713 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1714 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1715 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1716 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1717 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1718 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1719 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1720 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1721 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1723 static struct attribute
*empty_attrs
;
1725 static struct attribute
*events_attr
[] = {
1726 EVENT_PTR(CPU_CYCLES
),
1727 EVENT_PTR(INSTRUCTIONS
),
1728 EVENT_PTR(CACHE_REFERENCES
),
1729 EVENT_PTR(CACHE_MISSES
),
1730 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1731 EVENT_PTR(BRANCH_MISSES
),
1732 EVENT_PTR(BUS_CYCLES
),
1733 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1734 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1735 EVENT_PTR(REF_CPU_CYCLES
),
1739 static struct attribute_group x86_pmu_events_group __ro_after_init
= {
1741 .attrs
= events_attr
,
1744 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1746 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1747 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1748 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1749 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1750 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1751 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1755 * We have whole page size to spend and just little data
1756 * to write, so we can safely use sprintf.
1758 ret
= sprintf(page
, "event=0x%02llx", event
);
1761 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1764 ret
+= sprintf(page
+ ret
, ",edge");
1767 ret
+= sprintf(page
+ ret
, ",pc");
1770 ret
+= sprintf(page
+ ret
, ",any");
1773 ret
+= sprintf(page
+ ret
, ",inv");
1776 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1778 ret
+= sprintf(page
+ ret
, "\n");
1783 static struct attribute_group x86_pmu_attr_group
;
1784 static struct attribute_group x86_pmu_caps_group
;
1786 static int __init
init_hw_perf_events(void)
1788 struct x86_pmu_quirk
*quirk
;
1791 pr_info("Performance Events: ");
1793 switch (boot_cpu_data
.x86_vendor
) {
1794 case X86_VENDOR_INTEL
:
1795 err
= intel_pmu_init();
1797 case X86_VENDOR_AMD
:
1798 err
= amd_pmu_init();
1800 case X86_VENDOR_HYGON
:
1801 err
= amd_pmu_init();
1802 x86_pmu
.name
= "HYGON";
1808 pr_cont("no PMU driver, software events only.\n");
1814 /* sanity check that the hardware exists or is emulated */
1815 if (!check_hw_exists())
1818 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1820 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1822 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1825 if (!x86_pmu
.intel_ctrl
)
1826 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1828 perf_events_lapic_init();
1829 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1831 unconstrained
= (struct event_constraint
)
1832 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1833 0, x86_pmu
.num_counters
, 0, 0);
1835 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1837 if (x86_pmu
.caps_attrs
) {
1838 struct attribute
**tmp
;
1840 tmp
= merge_attr(x86_pmu_caps_group
.attrs
, x86_pmu
.caps_attrs
);
1842 x86_pmu_caps_group
.attrs
= tmp
;
1845 if (x86_pmu
.event_attrs
)
1846 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1848 if (!x86_pmu
.events_sysfs_show
)
1849 x86_pmu_events_group
.attrs
= &empty_attrs
;
1851 filter_events(x86_pmu_events_group
.attrs
);
1853 if (x86_pmu
.cpu_events
) {
1854 struct attribute
**tmp
;
1856 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1858 x86_pmu_events_group
.attrs
= tmp
;
1861 if (x86_pmu
.attrs
) {
1862 struct attribute
**tmp
;
1864 tmp
= merge_attr(x86_pmu_attr_group
.attrs
, x86_pmu
.attrs
);
1866 x86_pmu_attr_group
.attrs
= tmp
;
1869 pr_info("... version: %d\n", x86_pmu
.version
);
1870 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1871 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1872 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1873 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1874 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1875 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1878 * Install callbacks. Core will call them for each online
1881 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "perf/x86:prepare",
1882 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1886 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1887 "perf/x86:starting", x86_pmu_starting_cpu
,
1892 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "perf/x86:online",
1893 x86_pmu_online_cpu
, NULL
);
1897 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1904 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1906 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1908 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1911 early_initcall(init_hw_perf_events
);
1913 static inline void x86_pmu_read(struct perf_event
*event
)
1916 return x86_pmu
.read(event
);
1917 x86_perf_event_update(event
);
1921 * Start group events scheduling transaction
1922 * Set the flag to make pmu::enable() not perform the
1923 * schedulability test, it will be performed at commit time
1925 * We only support PERF_PMU_TXN_ADD transactions. Save the
1926 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1929 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1931 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1933 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1935 cpuc
->txn_flags
= txn_flags
;
1936 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1939 perf_pmu_disable(pmu
);
1940 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1944 * Stop group events scheduling transaction
1945 * Clear the flag and pmu::enable() will perform the
1946 * schedulability test.
1948 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1950 unsigned int txn_flags
;
1951 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1953 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1955 txn_flags
= cpuc
->txn_flags
;
1956 cpuc
->txn_flags
= 0;
1957 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1961 * Truncate collected array by the number of events added in this
1962 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1964 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1965 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1966 perf_pmu_enable(pmu
);
1970 * Commit group events scheduling transaction
1971 * Perform the group schedulability test as a whole
1972 * Return 0 if success
1974 * Does not cancel the transaction on failure; expects the caller to do this.
1976 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1978 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1979 int assign
[X86_PMC_IDX_MAX
];
1982 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1984 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1985 cpuc
->txn_flags
= 0;
1991 if (!x86_pmu_initialized())
1994 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1999 * copy new assignment, now we know it is possible
2000 * will be used by hw_perf_enable()
2002 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
2004 cpuc
->txn_flags
= 0;
2005 perf_pmu_enable(pmu
);
2009 * a fake_cpuc is used to validate event groups. Due to
2010 * the extra reg logic, we need to also allocate a fake
2011 * per_core and per_cpu structure. Otherwise, group events
2012 * using extra reg may conflict without the kernel being
2013 * able to catch this when the last event gets added to
2016 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
2018 kfree(cpuc
->shared_regs
);
2022 static struct cpu_hw_events
*allocate_fake_cpuc(void)
2024 struct cpu_hw_events
*cpuc
;
2025 int cpu
= raw_smp_processor_id();
2027 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
2029 return ERR_PTR(-ENOMEM
);
2031 /* only needed, if we have extra_regs */
2032 if (x86_pmu
.extra_regs
) {
2033 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
2034 if (!cpuc
->shared_regs
)
2040 free_fake_cpuc(cpuc
);
2041 return ERR_PTR(-ENOMEM
);
2045 * validate that we can schedule this event
2047 static int validate_event(struct perf_event
*event
)
2049 struct cpu_hw_events
*fake_cpuc
;
2050 struct event_constraint
*c
;
2053 fake_cpuc
= allocate_fake_cpuc();
2054 if (IS_ERR(fake_cpuc
))
2055 return PTR_ERR(fake_cpuc
);
2057 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
2059 if (!c
|| !c
->weight
)
2062 if (x86_pmu
.put_event_constraints
)
2063 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
2065 free_fake_cpuc(fake_cpuc
);
2071 * validate a single event group
2073 * validation include:
2074 * - check events are compatible which each other
2075 * - events do not compete for the same counter
2076 * - number of events <= number of counters
2078 * validation ensures the group can be loaded onto the
2079 * PMU if it was the only group available.
2081 static int validate_group(struct perf_event
*event
)
2083 struct perf_event
*leader
= event
->group_leader
;
2084 struct cpu_hw_events
*fake_cpuc
;
2085 int ret
= -EINVAL
, n
;
2087 fake_cpuc
= allocate_fake_cpuc();
2088 if (IS_ERR(fake_cpuc
))
2089 return PTR_ERR(fake_cpuc
);
2091 * the event is not yet connected with its
2092 * siblings therefore we must first collect
2093 * existing siblings, then add the new event
2094 * before we can simulate the scheduling
2096 n
= collect_events(fake_cpuc
, leader
, true);
2100 fake_cpuc
->n_events
= n
;
2101 n
= collect_events(fake_cpuc
, event
, false);
2105 fake_cpuc
->n_events
= n
;
2107 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2110 free_fake_cpuc(fake_cpuc
);
2114 static int x86_pmu_event_init(struct perf_event
*event
)
2119 switch (event
->attr
.type
) {
2121 case PERF_TYPE_HARDWARE
:
2122 case PERF_TYPE_HW_CACHE
:
2129 err
= __x86_pmu_event_init(event
);
2132 * we temporarily connect event to its pmu
2133 * such that validate_group() can classify
2134 * it as an x86 event using is_x86_event()
2139 if (event
->group_leader
!= event
)
2140 err
= validate_group(event
);
2142 err
= validate_event(event
);
2148 event
->destroy(event
);
2151 if (READ_ONCE(x86_pmu
.attr_rdpmc
) &&
2152 !(event
->hw
.flags
& PERF_X86_EVENT_LARGE_PEBS
))
2153 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2158 static void refresh_pce(void *ignored
)
2160 load_mm_cr4(this_cpu_read(cpu_tlbstate
.loaded_mm
));
2163 static void x86_pmu_event_mapped(struct perf_event
*event
, struct mm_struct
*mm
)
2165 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2169 * This function relies on not being called concurrently in two
2170 * tasks in the same mm. Otherwise one task could observe
2171 * perf_rdpmc_allowed > 1 and return all the way back to
2172 * userspace with CR4.PCE clear while another task is still
2173 * doing on_each_cpu_mask() to propagate CR4.PCE.
2175 * For now, this can't happen because all callers hold mmap_sem
2176 * for write. If this changes, we'll need a different solution.
2178 lockdep_assert_held_exclusive(&mm
->mmap_sem
);
2180 if (atomic_inc_return(&mm
->context
.perf_rdpmc_allowed
) == 1)
2181 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2184 static void x86_pmu_event_unmapped(struct perf_event
*event
, struct mm_struct
*mm
)
2187 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2190 if (atomic_dec_and_test(&mm
->context
.perf_rdpmc_allowed
))
2191 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2194 static int x86_pmu_event_idx(struct perf_event
*event
)
2196 int idx
= event
->hw
.idx
;
2198 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2201 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2202 idx
-= INTEL_PMC_IDX_FIXED
;
2209 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2210 struct device_attribute
*attr
,
2213 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2216 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2217 struct device_attribute
*attr
,
2218 const char *buf
, size_t count
)
2223 ret
= kstrtoul(buf
, 0, &val
);
2230 if (x86_pmu
.attr_rdpmc_broken
)
2233 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2235 * Changing into or out of always available, aka
2236 * perf-event-bypassing mode. This path is extremely slow,
2237 * but only root can trigger it, so it's okay.
2240 static_branch_inc(&rdpmc_always_available_key
);
2242 static_branch_dec(&rdpmc_always_available_key
);
2243 on_each_cpu(refresh_pce
, NULL
, 1);
2246 x86_pmu
.attr_rdpmc
= val
;
2251 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2253 static struct attribute
*x86_pmu_attrs
[] = {
2254 &dev_attr_rdpmc
.attr
,
2258 static struct attribute_group x86_pmu_attr_group __ro_after_init
= {
2259 .attrs
= x86_pmu_attrs
,
2262 static ssize_t
max_precise_show(struct device
*cdev
,
2263 struct device_attribute
*attr
,
2266 return snprintf(buf
, PAGE_SIZE
, "%d\n", x86_pmu_max_precise());
2269 static DEVICE_ATTR_RO(max_precise
);
2271 static struct attribute
*x86_pmu_caps_attrs
[] = {
2272 &dev_attr_max_precise
.attr
,
2276 static struct attribute_group x86_pmu_caps_group __ro_after_init
= {
2278 .attrs
= x86_pmu_caps_attrs
,
2281 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2282 &x86_pmu_attr_group
,
2283 &x86_pmu_format_group
,
2284 &x86_pmu_events_group
,
2285 &x86_pmu_caps_group
,
2289 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2291 if (x86_pmu
.sched_task
)
2292 x86_pmu
.sched_task(ctx
, sched_in
);
2295 void perf_check_microcode(void)
2297 if (x86_pmu
.check_microcode
)
2298 x86_pmu
.check_microcode();
2301 static struct pmu pmu
= {
2302 .pmu_enable
= x86_pmu_enable
,
2303 .pmu_disable
= x86_pmu_disable
,
2305 .attr_groups
= x86_pmu_attr_groups
,
2307 .event_init
= x86_pmu_event_init
,
2309 .event_mapped
= x86_pmu_event_mapped
,
2310 .event_unmapped
= x86_pmu_event_unmapped
,
2314 .start
= x86_pmu_start
,
2315 .stop
= x86_pmu_stop
,
2316 .read
= x86_pmu_read
,
2318 .start_txn
= x86_pmu_start_txn
,
2319 .cancel_txn
= x86_pmu_cancel_txn
,
2320 .commit_txn
= x86_pmu_commit_txn
,
2322 .event_idx
= x86_pmu_event_idx
,
2323 .sched_task
= x86_pmu_sched_task
,
2324 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2327 void arch_perf_update_userpage(struct perf_event
*event
,
2328 struct perf_event_mmap_page
*userpg
, u64 now
)
2330 struct cyc2ns_data data
;
2333 userpg
->cap_user_time
= 0;
2334 userpg
->cap_user_time_zero
= 0;
2335 userpg
->cap_user_rdpmc
=
2336 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2337 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2339 if (!using_native_sched_clock() || !sched_clock_stable())
2342 cyc2ns_read_begin(&data
);
2344 offset
= data
.cyc2ns_offset
+ __sched_clock_offset
;
2347 * Internal timekeeping for enabled/running/stopped times
2348 * is always in the local_clock domain.
2350 userpg
->cap_user_time
= 1;
2351 userpg
->time_mult
= data
.cyc2ns_mul
;
2352 userpg
->time_shift
= data
.cyc2ns_shift
;
2353 userpg
->time_offset
= offset
- now
;
2356 * cap_user_time_zero doesn't make sense when we're using a different
2357 * time base for the records.
2359 if (!event
->attr
.use_clockid
) {
2360 userpg
->cap_user_time_zero
= 1;
2361 userpg
->time_zero
= offset
;
2368 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2370 struct unwind_state state
;
2373 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2374 /* TODO: We don't support guest os callchain now */
2378 if (perf_callchain_store(entry
, regs
->ip
))
2381 for (unwind_start(&state
, current
, regs
, NULL
); !unwind_done(&state
);
2382 unwind_next_frame(&state
)) {
2383 addr
= unwind_get_return_address(&state
);
2384 if (!addr
|| perf_callchain_store(entry
, addr
))
2390 valid_user_frame(const void __user
*fp
, unsigned long size
)
2392 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2395 static unsigned long get_segment_base(unsigned int segment
)
2397 struct desc_struct
*desc
;
2398 unsigned int idx
= segment
>> 3;
2400 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2401 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2402 struct ldt_struct
*ldt
;
2404 /* IRQs are off, so this synchronizes with smp_store_release */
2405 ldt
= READ_ONCE(current
->active_mm
->context
.ldt
);
2406 if (!ldt
|| idx
>= ldt
->nr_entries
)
2409 desc
= &ldt
->entries
[idx
];
2414 if (idx
>= GDT_ENTRIES
)
2417 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2420 return get_desc_base(desc
);
2423 #ifdef CONFIG_IA32_EMULATION
2425 #include <linux/compat.h>
2428 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2430 /* 32-bit process in 64-bit kernel. */
2431 unsigned long ss_base
, cs_base
;
2432 struct stack_frame_ia32 frame
;
2433 const void __user
*fp
;
2435 if (!test_thread_flag(TIF_IA32
))
2438 cs_base
= get_segment_base(regs
->cs
);
2439 ss_base
= get_segment_base(regs
->ss
);
2441 fp
= compat_ptr(ss_base
+ regs
->bp
);
2442 pagefault_disable();
2443 while (entry
->nr
< entry
->max_stack
) {
2444 unsigned long bytes
;
2445 frame
.next_frame
= 0;
2446 frame
.return_address
= 0;
2448 if (!valid_user_frame(fp
, sizeof(frame
)))
2451 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2454 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2458 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2459 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2466 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2473 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2475 struct stack_frame frame
;
2476 const unsigned long __user
*fp
;
2478 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2479 /* TODO: We don't support guest os callchain now */
2484 * We don't know what to do with VM86 stacks.. ignore them for now.
2486 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2489 fp
= (unsigned long __user
*)regs
->bp
;
2491 perf_callchain_store(entry
, regs
->ip
);
2493 if (!nmi_uaccess_okay())
2496 if (perf_callchain_user32(regs
, entry
))
2499 pagefault_disable();
2500 while (entry
->nr
< entry
->max_stack
) {
2501 unsigned long bytes
;
2503 frame
.next_frame
= NULL
;
2504 frame
.return_address
= 0;
2506 if (!valid_user_frame(fp
, sizeof(frame
)))
2509 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2512 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2516 perf_callchain_store(entry
, frame
.return_address
);
2517 fp
= (void __user
*)frame
.next_frame
;
2523 * Deal with code segment offsets for the various execution modes:
2525 * VM86 - the good olde 16 bit days, where the linear address is
2526 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2528 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2529 * to figure out what the 32bit base address is.
2531 * X32 - has TIF_X32 set, but is running in x86_64
2533 * X86_64 - CS,DS,SS,ES are all zero based.
2535 static unsigned long code_segment_base(struct pt_regs
*regs
)
2538 * For IA32 we look at the GDT/LDT segment base to convert the
2539 * effective IP to a linear address.
2542 #ifdef CONFIG_X86_32
2544 * If we are in VM86 mode, add the segment offset to convert to a
2547 if (regs
->flags
& X86_VM_MASK
)
2548 return 0x10 * regs
->cs
;
2550 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2551 return get_segment_base(regs
->cs
);
2553 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2554 regs
->cs
!= __USER32_CS
)
2555 return get_segment_base(regs
->cs
);
2560 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2562 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2563 return perf_guest_cbs
->get_guest_ip();
2565 return regs
->ip
+ code_segment_base(regs
);
2568 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2572 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2573 if (perf_guest_cbs
->is_user_mode())
2574 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2576 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2578 if (user_mode(regs
))
2579 misc
|= PERF_RECORD_MISC_USER
;
2581 misc
|= PERF_RECORD_MISC_KERNEL
;
2584 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2585 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2590 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2592 cap
->version
= x86_pmu
.version
;
2593 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2594 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2595 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2596 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2597 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2598 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2600 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);