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x86/fpu/xstate: Restore supervisor states for signal return
[thirdparty/linux.git] / arch / x86 / events / intel / core.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
22 #include <asm/apic.h>
23 #include <asm/cpu_device_id.h>
24
25 #include "../perf_event.h"
26
27 /*
28 * Intel PerfMon, used on Core and later.
29 */
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
31 {
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
40 };
41
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
43 {
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
50 EVENT_CONSTRAINT_END
51 };
52
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
54 {
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
68 EVENT_CONSTRAINT_END
69 };
70
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
72 {
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
84 EVENT_CONSTRAINT_END
85 };
86
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
88 {
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
92 EVENT_EXTRA_END
93 };
94
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
96 {
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
104 EVENT_CONSTRAINT_END
105 };
106
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
108 {
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
121
122 /*
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
125 */
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
130
131 EVENT_CONSTRAINT_END
132 };
133
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
135 {
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
149
150 /*
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
153 */
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
158
159 EVENT_CONSTRAINT_END
160 };
161
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
163 {
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
168 EVENT_EXTRA_END
169 };
170
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
172 {
173 EVENT_CONSTRAINT_END
174 };
175
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
177 {
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
181 EVENT_CONSTRAINT_END
182 };
183
184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
185 {
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
189 EVENT_CONSTRAINT_END
190 };
191
192 static struct event_constraint intel_skl_event_constraints[] = {
193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
197
198 /*
199 * when HT is off, these can only run on the bottom 4 counters
200 */
201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
206
207 EVENT_CONSTRAINT_END
208 };
209
210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
213 EVENT_EXTRA_END
214 };
215
216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
221 EVENT_EXTRA_END
222 };
223
224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
229 EVENT_EXTRA_END
230 };
231
232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
236 /*
237 * Note the low 8 bits eventsel code is not a continuous field, containing
238 * some #GPing bits. These are masked out.
239 */
240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
241 EVENT_EXTRA_END
242 };
243
244 static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 INTEL_UEVENT_CONSTRAINT(0x1c0, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
250 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
251 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
252 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
253 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
254 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
255 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
256 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
257 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
258 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
259 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
260 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
261 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
262 EVENT_CONSTRAINT_END
263 };
264
265 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
266 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
267 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
268 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
269 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
270 EVENT_EXTRA_END
271 };
272
273 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
274 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
275 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
276
277 static struct attribute *nhm_mem_events_attrs[] = {
278 EVENT_PTR(mem_ld_nhm),
279 NULL,
280 };
281
282 /*
283 * topdown events for Intel Core CPUs.
284 *
285 * The events are all in slots, which is a free slot in a 4 wide
286 * pipeline. Some events are already reported in slots, for cycle
287 * events we multiply by the pipeline width (4).
288 *
289 * With Hyper Threading on, topdown metrics are either summed or averaged
290 * between the threads of a core: (count_t0 + count_t1).
291 *
292 * For the average case the metric is always scaled to pipeline width,
293 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
294 */
295
296 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
297 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
298 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
299 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
300 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
301 "event=0xe,umask=0x1"); /* uops_issued.any */
302 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
303 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
304 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
305 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
306 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
307 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
308 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
309 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
310 "4", "2");
311
312 static struct attribute *snb_events_attrs[] = {
313 EVENT_PTR(td_slots_issued),
314 EVENT_PTR(td_slots_retired),
315 EVENT_PTR(td_fetch_bubbles),
316 EVENT_PTR(td_total_slots),
317 EVENT_PTR(td_total_slots_scale),
318 EVENT_PTR(td_recovery_bubbles),
319 EVENT_PTR(td_recovery_bubbles_scale),
320 NULL,
321 };
322
323 static struct attribute *snb_mem_events_attrs[] = {
324 EVENT_PTR(mem_ld_snb),
325 EVENT_PTR(mem_st_snb),
326 NULL,
327 };
328
329 static struct event_constraint intel_hsw_event_constraints[] = {
330 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
331 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
332 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
333 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
334 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
335 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
336 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
337 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
338 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
339 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
340 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
341 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
342
343 /*
344 * When HT is off these events can only run on the bottom 4 counters
345 * When HT is on, they are impacted by the HT bug and require EXCL access
346 */
347 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
348 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
349 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
350 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
351
352 EVENT_CONSTRAINT_END
353 };
354
355 static struct event_constraint intel_bdw_event_constraints[] = {
356 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
357 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
358 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
359 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
360 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
361 /*
362 * when HT is off, these can only run on the bottom 4 counters
363 */
364 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
365 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
366 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
367 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
368 EVENT_CONSTRAINT_END
369 };
370
371 static u64 intel_pmu_event_map(int hw_event)
372 {
373 return intel_perfmon_event_map[hw_event];
374 }
375
376 /*
377 * Notes on the events:
378 * - data reads do not include code reads (comparable to earlier tables)
379 * - data counts include speculative execution (except L1 write, dtlb, bpu)
380 * - remote node access includes remote memory, remote cache, remote mmio.
381 * - prefetches are not included in the counts.
382 * - icache miss does not include decoded icache
383 */
384
385 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
386 #define SKL_DEMAND_RFO BIT_ULL(1)
387 #define SKL_ANY_RESPONSE BIT_ULL(16)
388 #define SKL_SUPPLIER_NONE BIT_ULL(17)
389 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
390 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
391 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
392 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
393 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
394 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
395 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
396 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
397 #define SKL_SPL_HIT BIT_ULL(30)
398 #define SKL_SNOOP_NONE BIT_ULL(31)
399 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
400 #define SKL_SNOOP_MISS BIT_ULL(33)
401 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
402 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
403 #define SKL_SNOOP_HITM BIT_ULL(36)
404 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
405 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
406 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
407 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
408 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
409 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
410 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
411 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
412 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
413 SKL_SNOOP_HITM|SKL_SPL_HIT)
414 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
415 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
416 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
417 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
418 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
419
420 static __initconst const u64 skl_hw_cache_event_ids
421 [PERF_COUNT_HW_CACHE_MAX]
422 [PERF_COUNT_HW_CACHE_OP_MAX]
423 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
424 {
425 [ C(L1D ) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
428 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
429 },
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
432 [ C(RESULT_MISS) ] = 0x0,
433 },
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = 0x0,
436 [ C(RESULT_MISS) ] = 0x0,
437 },
438 },
439 [ C(L1I ) ] = {
440 [ C(OP_READ) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = -1,
446 [ C(RESULT_MISS) ] = -1,
447 },
448 [ C(OP_PREFETCH) ] = {
449 [ C(RESULT_ACCESS) ] = 0x0,
450 [ C(RESULT_MISS) ] = 0x0,
451 },
452 },
453 [ C(LL ) ] = {
454 [ C(OP_READ) ] = {
455 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
456 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
457 },
458 [ C(OP_WRITE) ] = {
459 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
460 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0,
464 [ C(RESULT_MISS) ] = 0x0,
465 },
466 },
467 [ C(DTLB) ] = {
468 [ C(OP_READ) ] = {
469 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
470 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
471 },
472 [ C(OP_WRITE) ] = {
473 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
474 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
475 },
476 [ C(OP_PREFETCH) ] = {
477 [ C(RESULT_ACCESS) ] = 0x0,
478 [ C(RESULT_MISS) ] = 0x0,
479 },
480 },
481 [ C(ITLB) ] = {
482 [ C(OP_READ) ] = {
483 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
484 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
485 },
486 [ C(OP_WRITE) ] = {
487 [ C(RESULT_ACCESS) ] = -1,
488 [ C(RESULT_MISS) ] = -1,
489 },
490 [ C(OP_PREFETCH) ] = {
491 [ C(RESULT_ACCESS) ] = -1,
492 [ C(RESULT_MISS) ] = -1,
493 },
494 },
495 [ C(BPU ) ] = {
496 [ C(OP_READ) ] = {
497 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
498 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
499 },
500 [ C(OP_WRITE) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
503 },
504 [ C(OP_PREFETCH) ] = {
505 [ C(RESULT_ACCESS) ] = -1,
506 [ C(RESULT_MISS) ] = -1,
507 },
508 },
509 [ C(NODE) ] = {
510 [ C(OP_READ) ] = {
511 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
512 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
513 },
514 [ C(OP_WRITE) ] = {
515 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
516 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 },
518 [ C(OP_PREFETCH) ] = {
519 [ C(RESULT_ACCESS) ] = 0x0,
520 [ C(RESULT_MISS) ] = 0x0,
521 },
522 },
523 };
524
525 static __initconst const u64 skl_hw_cache_extra_regs
526 [PERF_COUNT_HW_CACHE_MAX]
527 [PERF_COUNT_HW_CACHE_OP_MAX]
528 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
529 {
530 [ C(LL ) ] = {
531 [ C(OP_READ) ] = {
532 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
533 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
534 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
535 SKL_L3_MISS|SKL_ANY_SNOOP|
536 SKL_SUPPLIER_NONE,
537 },
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
540 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
541 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
542 SKL_L3_MISS|SKL_ANY_SNOOP|
543 SKL_SUPPLIER_NONE,
544 },
545 [ C(OP_PREFETCH) ] = {
546 [ C(RESULT_ACCESS) ] = 0x0,
547 [ C(RESULT_MISS) ] = 0x0,
548 },
549 },
550 [ C(NODE) ] = {
551 [ C(OP_READ) ] = {
552 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
553 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
554 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
555 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
556 },
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
559 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
560 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
561 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
562 },
563 [ C(OP_PREFETCH) ] = {
564 [ C(RESULT_ACCESS) ] = 0x0,
565 [ C(RESULT_MISS) ] = 0x0,
566 },
567 },
568 };
569
570 #define SNB_DMND_DATA_RD (1ULL << 0)
571 #define SNB_DMND_RFO (1ULL << 1)
572 #define SNB_DMND_IFETCH (1ULL << 2)
573 #define SNB_DMND_WB (1ULL << 3)
574 #define SNB_PF_DATA_RD (1ULL << 4)
575 #define SNB_PF_RFO (1ULL << 5)
576 #define SNB_PF_IFETCH (1ULL << 6)
577 #define SNB_LLC_DATA_RD (1ULL << 7)
578 #define SNB_LLC_RFO (1ULL << 8)
579 #define SNB_LLC_IFETCH (1ULL << 9)
580 #define SNB_BUS_LOCKS (1ULL << 10)
581 #define SNB_STRM_ST (1ULL << 11)
582 #define SNB_OTHER (1ULL << 15)
583 #define SNB_RESP_ANY (1ULL << 16)
584 #define SNB_NO_SUPP (1ULL << 17)
585 #define SNB_LLC_HITM (1ULL << 18)
586 #define SNB_LLC_HITE (1ULL << 19)
587 #define SNB_LLC_HITS (1ULL << 20)
588 #define SNB_LLC_HITF (1ULL << 21)
589 #define SNB_LOCAL (1ULL << 22)
590 #define SNB_REMOTE (0xffULL << 23)
591 #define SNB_SNP_NONE (1ULL << 31)
592 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
593 #define SNB_SNP_MISS (1ULL << 33)
594 #define SNB_NO_FWD (1ULL << 34)
595 #define SNB_SNP_FWD (1ULL << 35)
596 #define SNB_HITM (1ULL << 36)
597 #define SNB_NON_DRAM (1ULL << 37)
598
599 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
600 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
601 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
602
603 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
604 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
605 SNB_HITM)
606
607 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
608 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
609
610 #define SNB_L3_ACCESS SNB_RESP_ANY
611 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
612
613 static __initconst const u64 snb_hw_cache_extra_regs
614 [PERF_COUNT_HW_CACHE_MAX]
615 [PERF_COUNT_HW_CACHE_OP_MAX]
616 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
617 {
618 [ C(LL ) ] = {
619 [ C(OP_READ) ] = {
620 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
621 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
622 },
623 [ C(OP_WRITE) ] = {
624 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
625 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
626 },
627 [ C(OP_PREFETCH) ] = {
628 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
629 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
630 },
631 },
632 [ C(NODE) ] = {
633 [ C(OP_READ) ] = {
634 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
635 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
636 },
637 [ C(OP_WRITE) ] = {
638 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
639 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
640 },
641 [ C(OP_PREFETCH) ] = {
642 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
643 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
644 },
645 },
646 };
647
648 static __initconst const u64 snb_hw_cache_event_ids
649 [PERF_COUNT_HW_CACHE_MAX]
650 [PERF_COUNT_HW_CACHE_OP_MAX]
651 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
652 {
653 [ C(L1D) ] = {
654 [ C(OP_READ) ] = {
655 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
656 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
657 },
658 [ C(OP_WRITE) ] = {
659 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
660 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
661 },
662 [ C(OP_PREFETCH) ] = {
663 [ C(RESULT_ACCESS) ] = 0x0,
664 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
665 },
666 },
667 [ C(L1I ) ] = {
668 [ C(OP_READ) ] = {
669 [ C(RESULT_ACCESS) ] = 0x0,
670 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
671 },
672 [ C(OP_WRITE) ] = {
673 [ C(RESULT_ACCESS) ] = -1,
674 [ C(RESULT_MISS) ] = -1,
675 },
676 [ C(OP_PREFETCH) ] = {
677 [ C(RESULT_ACCESS) ] = 0x0,
678 [ C(RESULT_MISS) ] = 0x0,
679 },
680 },
681 [ C(LL ) ] = {
682 [ C(OP_READ) ] = {
683 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
684 [ C(RESULT_ACCESS) ] = 0x01b7,
685 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
686 [ C(RESULT_MISS) ] = 0x01b7,
687 },
688 [ C(OP_WRITE) ] = {
689 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
690 [ C(RESULT_ACCESS) ] = 0x01b7,
691 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
692 [ C(RESULT_MISS) ] = 0x01b7,
693 },
694 [ C(OP_PREFETCH) ] = {
695 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
696 [ C(RESULT_ACCESS) ] = 0x01b7,
697 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
701 [ C(DTLB) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
704 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
708 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
713 },
714 },
715 [ C(ITLB) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
718 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = -1,
726 [ C(RESULT_MISS) ] = -1,
727 },
728 },
729 [ C(BPU ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
732 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = -1,
740 [ C(RESULT_MISS) ] = -1,
741 },
742 },
743 [ C(NODE) ] = {
744 [ C(OP_READ) ] = {
745 [ C(RESULT_ACCESS) ] = 0x01b7,
746 [ C(RESULT_MISS) ] = 0x01b7,
747 },
748 [ C(OP_WRITE) ] = {
749 [ C(RESULT_ACCESS) ] = 0x01b7,
750 [ C(RESULT_MISS) ] = 0x01b7,
751 },
752 [ C(OP_PREFETCH) ] = {
753 [ C(RESULT_ACCESS) ] = 0x01b7,
754 [ C(RESULT_MISS) ] = 0x01b7,
755 },
756 },
757
758 };
759
760 /*
761 * Notes on the events:
762 * - data reads do not include code reads (comparable to earlier tables)
763 * - data counts include speculative execution (except L1 write, dtlb, bpu)
764 * - remote node access includes remote memory, remote cache, remote mmio.
765 * - prefetches are not included in the counts because they are not
766 * reliably counted.
767 */
768
769 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
770 #define HSW_DEMAND_RFO BIT_ULL(1)
771 #define HSW_ANY_RESPONSE BIT_ULL(16)
772 #define HSW_SUPPLIER_NONE BIT_ULL(17)
773 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
774 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
775 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
776 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
777 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
778 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
779 HSW_L3_MISS_REMOTE_HOP2P)
780 #define HSW_SNOOP_NONE BIT_ULL(31)
781 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
782 #define HSW_SNOOP_MISS BIT_ULL(33)
783 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
784 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
785 #define HSW_SNOOP_HITM BIT_ULL(36)
786 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
787 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
788 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
789 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
790 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
791 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
792 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
793 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
794 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
795 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
796 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
797
798 #define BDW_L3_MISS_LOCAL BIT(26)
799 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
800 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
801 HSW_L3_MISS_REMOTE_HOP2P)
802
803
804 static __initconst const u64 hsw_hw_cache_event_ids
805 [PERF_COUNT_HW_CACHE_MAX]
806 [PERF_COUNT_HW_CACHE_OP_MAX]
807 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
808 {
809 [ C(L1D ) ] = {
810 [ C(OP_READ) ] = {
811 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
812 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
816 [ C(RESULT_MISS) ] = 0x0,
817 },
818 [ C(OP_PREFETCH) ] = {
819 [ C(RESULT_ACCESS) ] = 0x0,
820 [ C(RESULT_MISS) ] = 0x0,
821 },
822 },
823 [ C(L1I ) ] = {
824 [ C(OP_READ) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
827 },
828 [ C(OP_WRITE) ] = {
829 [ C(RESULT_ACCESS) ] = -1,
830 [ C(RESULT_MISS) ] = -1,
831 },
832 [ C(OP_PREFETCH) ] = {
833 [ C(RESULT_ACCESS) ] = 0x0,
834 [ C(RESULT_MISS) ] = 0x0,
835 },
836 },
837 [ C(LL ) ] = {
838 [ C(OP_READ) ] = {
839 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
840 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
841 },
842 [ C(OP_WRITE) ] = {
843 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
844 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
845 },
846 [ C(OP_PREFETCH) ] = {
847 [ C(RESULT_ACCESS) ] = 0x0,
848 [ C(RESULT_MISS) ] = 0x0,
849 },
850 },
851 [ C(DTLB) ] = {
852 [ C(OP_READ) ] = {
853 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
854 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
855 },
856 [ C(OP_WRITE) ] = {
857 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
858 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
859 },
860 [ C(OP_PREFETCH) ] = {
861 [ C(RESULT_ACCESS) ] = 0x0,
862 [ C(RESULT_MISS) ] = 0x0,
863 },
864 },
865 [ C(ITLB) ] = {
866 [ C(OP_READ) ] = {
867 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
868 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
869 },
870 [ C(OP_WRITE) ] = {
871 [ C(RESULT_ACCESS) ] = -1,
872 [ C(RESULT_MISS) ] = -1,
873 },
874 [ C(OP_PREFETCH) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 },
879 [ C(BPU ) ] = {
880 [ C(OP_READ) ] = {
881 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
882 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
883 },
884 [ C(OP_WRITE) ] = {
885 [ C(RESULT_ACCESS) ] = -1,
886 [ C(RESULT_MISS) ] = -1,
887 },
888 [ C(OP_PREFETCH) ] = {
889 [ C(RESULT_ACCESS) ] = -1,
890 [ C(RESULT_MISS) ] = -1,
891 },
892 },
893 [ C(NODE) ] = {
894 [ C(OP_READ) ] = {
895 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
896 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
897 },
898 [ C(OP_WRITE) ] = {
899 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
900 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
901 },
902 [ C(OP_PREFETCH) ] = {
903 [ C(RESULT_ACCESS) ] = 0x0,
904 [ C(RESULT_MISS) ] = 0x0,
905 },
906 },
907 };
908
909 static __initconst const u64 hsw_hw_cache_extra_regs
910 [PERF_COUNT_HW_CACHE_MAX]
911 [PERF_COUNT_HW_CACHE_OP_MAX]
912 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
913 {
914 [ C(LL ) ] = {
915 [ C(OP_READ) ] = {
916 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
917 HSW_LLC_ACCESS,
918 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
919 HSW_L3_MISS|HSW_ANY_SNOOP,
920 },
921 [ C(OP_WRITE) ] = {
922 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
923 HSW_LLC_ACCESS,
924 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
925 HSW_L3_MISS|HSW_ANY_SNOOP,
926 },
927 [ C(OP_PREFETCH) ] = {
928 [ C(RESULT_ACCESS) ] = 0x0,
929 [ C(RESULT_MISS) ] = 0x0,
930 },
931 },
932 [ C(NODE) ] = {
933 [ C(OP_READ) ] = {
934 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
935 HSW_L3_MISS_LOCAL_DRAM|
936 HSW_SNOOP_DRAM,
937 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
938 HSW_L3_MISS_REMOTE|
939 HSW_SNOOP_DRAM,
940 },
941 [ C(OP_WRITE) ] = {
942 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
943 HSW_L3_MISS_LOCAL_DRAM|
944 HSW_SNOOP_DRAM,
945 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
946 HSW_L3_MISS_REMOTE|
947 HSW_SNOOP_DRAM,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = 0x0,
951 [ C(RESULT_MISS) ] = 0x0,
952 },
953 },
954 };
955
956 static __initconst const u64 westmere_hw_cache_event_ids
957 [PERF_COUNT_HW_CACHE_MAX]
958 [PERF_COUNT_HW_CACHE_OP_MAX]
959 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
960 {
961 [ C(L1D) ] = {
962 [ C(OP_READ) ] = {
963 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
964 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
965 },
966 [ C(OP_WRITE) ] = {
967 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
968 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
969 },
970 [ C(OP_PREFETCH) ] = {
971 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
972 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
973 },
974 },
975 [ C(L1I ) ] = {
976 [ C(OP_READ) ] = {
977 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
978 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
979 },
980 [ C(OP_WRITE) ] = {
981 [ C(RESULT_ACCESS) ] = -1,
982 [ C(RESULT_MISS) ] = -1,
983 },
984 [ C(OP_PREFETCH) ] = {
985 [ C(RESULT_ACCESS) ] = 0x0,
986 [ C(RESULT_MISS) ] = 0x0,
987 },
988 },
989 [ C(LL ) ] = {
990 [ C(OP_READ) ] = {
991 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
992 [ C(RESULT_ACCESS) ] = 0x01b7,
993 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
994 [ C(RESULT_MISS) ] = 0x01b7,
995 },
996 /*
997 * Use RFO, not WRITEBACK, because a write miss would typically occur
998 * on RFO.
999 */
1000 [ C(OP_WRITE) ] = {
1001 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1002 [ C(RESULT_ACCESS) ] = 0x01b7,
1003 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1004 [ C(RESULT_MISS) ] = 0x01b7,
1005 },
1006 [ C(OP_PREFETCH) ] = {
1007 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1008 [ C(RESULT_ACCESS) ] = 0x01b7,
1009 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1010 [ C(RESULT_MISS) ] = 0x01b7,
1011 },
1012 },
1013 [ C(DTLB) ] = {
1014 [ C(OP_READ) ] = {
1015 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1016 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1017 },
1018 [ C(OP_WRITE) ] = {
1019 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1020 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1021 },
1022 [ C(OP_PREFETCH) ] = {
1023 [ C(RESULT_ACCESS) ] = 0x0,
1024 [ C(RESULT_MISS) ] = 0x0,
1025 },
1026 },
1027 [ C(ITLB) ] = {
1028 [ C(OP_READ) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1030 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1031 },
1032 [ C(OP_WRITE) ] = {
1033 [ C(RESULT_ACCESS) ] = -1,
1034 [ C(RESULT_MISS) ] = -1,
1035 },
1036 [ C(OP_PREFETCH) ] = {
1037 [ C(RESULT_ACCESS) ] = -1,
1038 [ C(RESULT_MISS) ] = -1,
1039 },
1040 },
1041 [ C(BPU ) ] = {
1042 [ C(OP_READ) ] = {
1043 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1044 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1045 },
1046 [ C(OP_WRITE) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1049 },
1050 [ C(OP_PREFETCH) ] = {
1051 [ C(RESULT_ACCESS) ] = -1,
1052 [ C(RESULT_MISS) ] = -1,
1053 },
1054 },
1055 [ C(NODE) ] = {
1056 [ C(OP_READ) ] = {
1057 [ C(RESULT_ACCESS) ] = 0x01b7,
1058 [ C(RESULT_MISS) ] = 0x01b7,
1059 },
1060 [ C(OP_WRITE) ] = {
1061 [ C(RESULT_ACCESS) ] = 0x01b7,
1062 [ C(RESULT_MISS) ] = 0x01b7,
1063 },
1064 [ C(OP_PREFETCH) ] = {
1065 [ C(RESULT_ACCESS) ] = 0x01b7,
1066 [ C(RESULT_MISS) ] = 0x01b7,
1067 },
1068 },
1069 };
1070
1071 /*
1072 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1073 * See IA32 SDM Vol 3B 30.6.1.3
1074 */
1075
1076 #define NHM_DMND_DATA_RD (1 << 0)
1077 #define NHM_DMND_RFO (1 << 1)
1078 #define NHM_DMND_IFETCH (1 << 2)
1079 #define NHM_DMND_WB (1 << 3)
1080 #define NHM_PF_DATA_RD (1 << 4)
1081 #define NHM_PF_DATA_RFO (1 << 5)
1082 #define NHM_PF_IFETCH (1 << 6)
1083 #define NHM_OFFCORE_OTHER (1 << 7)
1084 #define NHM_UNCORE_HIT (1 << 8)
1085 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1086 #define NHM_OTHER_CORE_HITM (1 << 10)
1087 /* reserved */
1088 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1089 #define NHM_REMOTE_DRAM (1 << 13)
1090 #define NHM_LOCAL_DRAM (1 << 14)
1091 #define NHM_NON_DRAM (1 << 15)
1092
1093 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1094 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1095
1096 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1097 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1098 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1099
1100 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1101 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1102 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1103
1104 static __initconst const u64 nehalem_hw_cache_extra_regs
1105 [PERF_COUNT_HW_CACHE_MAX]
1106 [PERF_COUNT_HW_CACHE_OP_MAX]
1107 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1108 {
1109 [ C(LL ) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1112 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1113 },
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1116 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1117 },
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1120 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1121 },
1122 },
1123 [ C(NODE) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1126 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1127 },
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1130 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1131 },
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1134 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1135 },
1136 },
1137 };
1138
1139 static __initconst const u64 nehalem_hw_cache_event_ids
1140 [PERF_COUNT_HW_CACHE_MAX]
1141 [PERF_COUNT_HW_CACHE_OP_MAX]
1142 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1143 {
1144 [ C(L1D) ] = {
1145 [ C(OP_READ) ] = {
1146 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1147 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1148 },
1149 [ C(OP_WRITE) ] = {
1150 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1151 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1152 },
1153 [ C(OP_PREFETCH) ] = {
1154 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1155 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1156 },
1157 },
1158 [ C(L1I ) ] = {
1159 [ C(OP_READ) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1161 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1162 },
1163 [ C(OP_WRITE) ] = {
1164 [ C(RESULT_ACCESS) ] = -1,
1165 [ C(RESULT_MISS) ] = -1,
1166 },
1167 [ C(OP_PREFETCH) ] = {
1168 [ C(RESULT_ACCESS) ] = 0x0,
1169 [ C(RESULT_MISS) ] = 0x0,
1170 },
1171 },
1172 [ C(LL ) ] = {
1173 [ C(OP_READ) ] = {
1174 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1175 [ C(RESULT_ACCESS) ] = 0x01b7,
1176 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1177 [ C(RESULT_MISS) ] = 0x01b7,
1178 },
1179 /*
1180 * Use RFO, not WRITEBACK, because a write miss would typically occur
1181 * on RFO.
1182 */
1183 [ C(OP_WRITE) ] = {
1184 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1186 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1187 [ C(RESULT_MISS) ] = 0x01b7,
1188 },
1189 [ C(OP_PREFETCH) ] = {
1190 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1191 [ C(RESULT_ACCESS) ] = 0x01b7,
1192 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1193 [ C(RESULT_MISS) ] = 0x01b7,
1194 },
1195 },
1196 [ C(DTLB) ] = {
1197 [ C(OP_READ) ] = {
1198 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1199 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1200 },
1201 [ C(OP_WRITE) ] = {
1202 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1203 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1204 },
1205 [ C(OP_PREFETCH) ] = {
1206 [ C(RESULT_ACCESS) ] = 0x0,
1207 [ C(RESULT_MISS) ] = 0x0,
1208 },
1209 },
1210 [ C(ITLB) ] = {
1211 [ C(OP_READ) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1213 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1214 },
1215 [ C(OP_WRITE) ] = {
1216 [ C(RESULT_ACCESS) ] = -1,
1217 [ C(RESULT_MISS) ] = -1,
1218 },
1219 [ C(OP_PREFETCH) ] = {
1220 [ C(RESULT_ACCESS) ] = -1,
1221 [ C(RESULT_MISS) ] = -1,
1222 },
1223 },
1224 [ C(BPU ) ] = {
1225 [ C(OP_READ) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1227 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1228 },
1229 [ C(OP_WRITE) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1232 },
1233 [ C(OP_PREFETCH) ] = {
1234 [ C(RESULT_ACCESS) ] = -1,
1235 [ C(RESULT_MISS) ] = -1,
1236 },
1237 },
1238 [ C(NODE) ] = {
1239 [ C(OP_READ) ] = {
1240 [ C(RESULT_ACCESS) ] = 0x01b7,
1241 [ C(RESULT_MISS) ] = 0x01b7,
1242 },
1243 [ C(OP_WRITE) ] = {
1244 [ C(RESULT_ACCESS) ] = 0x01b7,
1245 [ C(RESULT_MISS) ] = 0x01b7,
1246 },
1247 [ C(OP_PREFETCH) ] = {
1248 [ C(RESULT_ACCESS) ] = 0x01b7,
1249 [ C(RESULT_MISS) ] = 0x01b7,
1250 },
1251 },
1252 };
1253
1254 static __initconst const u64 core2_hw_cache_event_ids
1255 [PERF_COUNT_HW_CACHE_MAX]
1256 [PERF_COUNT_HW_CACHE_OP_MAX]
1257 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1258 {
1259 [ C(L1D) ] = {
1260 [ C(OP_READ) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1262 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1263 },
1264 [ C(OP_WRITE) ] = {
1265 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1266 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1267 },
1268 [ C(OP_PREFETCH) ] = {
1269 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1270 [ C(RESULT_MISS) ] = 0,
1271 },
1272 },
1273 [ C(L1I ) ] = {
1274 [ C(OP_READ) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1276 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1277 },
1278 [ C(OP_WRITE) ] = {
1279 [ C(RESULT_ACCESS) ] = -1,
1280 [ C(RESULT_MISS) ] = -1,
1281 },
1282 [ C(OP_PREFETCH) ] = {
1283 [ C(RESULT_ACCESS) ] = 0,
1284 [ C(RESULT_MISS) ] = 0,
1285 },
1286 },
1287 [ C(LL ) ] = {
1288 [ C(OP_READ) ] = {
1289 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1290 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1291 },
1292 [ C(OP_WRITE) ] = {
1293 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1294 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1295 },
1296 [ C(OP_PREFETCH) ] = {
1297 [ C(RESULT_ACCESS) ] = 0,
1298 [ C(RESULT_MISS) ] = 0,
1299 },
1300 },
1301 [ C(DTLB) ] = {
1302 [ C(OP_READ) ] = {
1303 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1304 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1305 },
1306 [ C(OP_WRITE) ] = {
1307 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1308 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1309 },
1310 [ C(OP_PREFETCH) ] = {
1311 [ C(RESULT_ACCESS) ] = 0,
1312 [ C(RESULT_MISS) ] = 0,
1313 },
1314 },
1315 [ C(ITLB) ] = {
1316 [ C(OP_READ) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1318 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1319 },
1320 [ C(OP_WRITE) ] = {
1321 [ C(RESULT_ACCESS) ] = -1,
1322 [ C(RESULT_MISS) ] = -1,
1323 },
1324 [ C(OP_PREFETCH) ] = {
1325 [ C(RESULT_ACCESS) ] = -1,
1326 [ C(RESULT_MISS) ] = -1,
1327 },
1328 },
1329 [ C(BPU ) ] = {
1330 [ C(OP_READ) ] = {
1331 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1332 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1333 },
1334 [ C(OP_WRITE) ] = {
1335 [ C(RESULT_ACCESS) ] = -1,
1336 [ C(RESULT_MISS) ] = -1,
1337 },
1338 [ C(OP_PREFETCH) ] = {
1339 [ C(RESULT_ACCESS) ] = -1,
1340 [ C(RESULT_MISS) ] = -1,
1341 },
1342 },
1343 };
1344
1345 static __initconst const u64 atom_hw_cache_event_ids
1346 [PERF_COUNT_HW_CACHE_MAX]
1347 [PERF_COUNT_HW_CACHE_OP_MAX]
1348 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1349 {
1350 [ C(L1D) ] = {
1351 [ C(OP_READ) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 [ C(OP_WRITE) ] = {
1356 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1357 [ C(RESULT_MISS) ] = 0,
1358 },
1359 [ C(OP_PREFETCH) ] = {
1360 [ C(RESULT_ACCESS) ] = 0x0,
1361 [ C(RESULT_MISS) ] = 0,
1362 },
1363 },
1364 [ C(L1I ) ] = {
1365 [ C(OP_READ) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1367 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1368 },
1369 [ C(OP_WRITE) ] = {
1370 [ C(RESULT_ACCESS) ] = -1,
1371 [ C(RESULT_MISS) ] = -1,
1372 },
1373 [ C(OP_PREFETCH) ] = {
1374 [ C(RESULT_ACCESS) ] = 0,
1375 [ C(RESULT_MISS) ] = 0,
1376 },
1377 },
1378 [ C(LL ) ] = {
1379 [ C(OP_READ) ] = {
1380 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1381 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1382 },
1383 [ C(OP_WRITE) ] = {
1384 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1385 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1386 },
1387 [ C(OP_PREFETCH) ] = {
1388 [ C(RESULT_ACCESS) ] = 0,
1389 [ C(RESULT_MISS) ] = 0,
1390 },
1391 },
1392 [ C(DTLB) ] = {
1393 [ C(OP_READ) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1395 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1396 },
1397 [ C(OP_WRITE) ] = {
1398 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1399 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1400 },
1401 [ C(OP_PREFETCH) ] = {
1402 [ C(RESULT_ACCESS) ] = 0,
1403 [ C(RESULT_MISS) ] = 0,
1404 },
1405 },
1406 [ C(ITLB) ] = {
1407 [ C(OP_READ) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1409 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1410 },
1411 [ C(OP_WRITE) ] = {
1412 [ C(RESULT_ACCESS) ] = -1,
1413 [ C(RESULT_MISS) ] = -1,
1414 },
1415 [ C(OP_PREFETCH) ] = {
1416 [ C(RESULT_ACCESS) ] = -1,
1417 [ C(RESULT_MISS) ] = -1,
1418 },
1419 },
1420 [ C(BPU ) ] = {
1421 [ C(OP_READ) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1423 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1424 },
1425 [ C(OP_WRITE) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1428 },
1429 [ C(OP_PREFETCH) ] = {
1430 [ C(RESULT_ACCESS) ] = -1,
1431 [ C(RESULT_MISS) ] = -1,
1432 },
1433 },
1434 };
1435
1436 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1437 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1438 /* no_alloc_cycles.not_delivered */
1439 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1440 "event=0xca,umask=0x50");
1441 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1442 /* uops_retired.all */
1443 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1444 "event=0xc2,umask=0x10");
1445 /* uops_retired.all */
1446 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1447 "event=0xc2,umask=0x10");
1448
1449 static struct attribute *slm_events_attrs[] = {
1450 EVENT_PTR(td_total_slots_slm),
1451 EVENT_PTR(td_total_slots_scale_slm),
1452 EVENT_PTR(td_fetch_bubbles_slm),
1453 EVENT_PTR(td_fetch_bubbles_scale_slm),
1454 EVENT_PTR(td_slots_issued_slm),
1455 EVENT_PTR(td_slots_retired_slm),
1456 NULL
1457 };
1458
1459 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1460 {
1461 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1462 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1463 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1464 EVENT_EXTRA_END
1465 };
1466
1467 #define SLM_DMND_READ SNB_DMND_DATA_RD
1468 #define SLM_DMND_WRITE SNB_DMND_RFO
1469 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1470
1471 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1472 #define SLM_LLC_ACCESS SNB_RESP_ANY
1473 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1474
1475 static __initconst const u64 slm_hw_cache_extra_regs
1476 [PERF_COUNT_HW_CACHE_MAX]
1477 [PERF_COUNT_HW_CACHE_OP_MAX]
1478 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1479 {
1480 [ C(LL ) ] = {
1481 [ C(OP_READ) ] = {
1482 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1483 [ C(RESULT_MISS) ] = 0,
1484 },
1485 [ C(OP_WRITE) ] = {
1486 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1487 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1488 },
1489 [ C(OP_PREFETCH) ] = {
1490 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1491 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1492 },
1493 },
1494 };
1495
1496 static __initconst const u64 slm_hw_cache_event_ids
1497 [PERF_COUNT_HW_CACHE_MAX]
1498 [PERF_COUNT_HW_CACHE_OP_MAX]
1499 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1500 {
1501 [ C(L1D) ] = {
1502 [ C(OP_READ) ] = {
1503 [ C(RESULT_ACCESS) ] = 0,
1504 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1505 },
1506 [ C(OP_WRITE) ] = {
1507 [ C(RESULT_ACCESS) ] = 0,
1508 [ C(RESULT_MISS) ] = 0,
1509 },
1510 [ C(OP_PREFETCH) ] = {
1511 [ C(RESULT_ACCESS) ] = 0,
1512 [ C(RESULT_MISS) ] = 0,
1513 },
1514 },
1515 [ C(L1I ) ] = {
1516 [ C(OP_READ) ] = {
1517 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1518 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1519 },
1520 [ C(OP_WRITE) ] = {
1521 [ C(RESULT_ACCESS) ] = -1,
1522 [ C(RESULT_MISS) ] = -1,
1523 },
1524 [ C(OP_PREFETCH) ] = {
1525 [ C(RESULT_ACCESS) ] = 0,
1526 [ C(RESULT_MISS) ] = 0,
1527 },
1528 },
1529 [ C(LL ) ] = {
1530 [ C(OP_READ) ] = {
1531 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1532 [ C(RESULT_ACCESS) ] = 0x01b7,
1533 [ C(RESULT_MISS) ] = 0,
1534 },
1535 [ C(OP_WRITE) ] = {
1536 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1537 [ C(RESULT_ACCESS) ] = 0x01b7,
1538 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1539 [ C(RESULT_MISS) ] = 0x01b7,
1540 },
1541 [ C(OP_PREFETCH) ] = {
1542 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1543 [ C(RESULT_ACCESS) ] = 0x01b7,
1544 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1545 [ C(RESULT_MISS) ] = 0x01b7,
1546 },
1547 },
1548 [ C(DTLB) ] = {
1549 [ C(OP_READ) ] = {
1550 [ C(RESULT_ACCESS) ] = 0,
1551 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1552 },
1553 [ C(OP_WRITE) ] = {
1554 [ C(RESULT_ACCESS) ] = 0,
1555 [ C(RESULT_MISS) ] = 0,
1556 },
1557 [ C(OP_PREFETCH) ] = {
1558 [ C(RESULT_ACCESS) ] = 0,
1559 [ C(RESULT_MISS) ] = 0,
1560 },
1561 },
1562 [ C(ITLB) ] = {
1563 [ C(OP_READ) ] = {
1564 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1565 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1566 },
1567 [ C(OP_WRITE) ] = {
1568 [ C(RESULT_ACCESS) ] = -1,
1569 [ C(RESULT_MISS) ] = -1,
1570 },
1571 [ C(OP_PREFETCH) ] = {
1572 [ C(RESULT_ACCESS) ] = -1,
1573 [ C(RESULT_MISS) ] = -1,
1574 },
1575 },
1576 [ C(BPU ) ] = {
1577 [ C(OP_READ) ] = {
1578 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1579 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1580 },
1581 [ C(OP_WRITE) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1584 },
1585 [ C(OP_PREFETCH) ] = {
1586 [ C(RESULT_ACCESS) ] = -1,
1587 [ C(RESULT_MISS) ] = -1,
1588 },
1589 },
1590 };
1591
1592 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1593 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1594 /* UOPS_NOT_DELIVERED.ANY */
1595 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1596 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1597 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1598 /* UOPS_RETIRED.ANY */
1599 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1600 /* UOPS_ISSUED.ANY */
1601 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1602
1603 static struct attribute *glm_events_attrs[] = {
1604 EVENT_PTR(td_total_slots_glm),
1605 EVENT_PTR(td_total_slots_scale_glm),
1606 EVENT_PTR(td_fetch_bubbles_glm),
1607 EVENT_PTR(td_recovery_bubbles_glm),
1608 EVENT_PTR(td_slots_issued_glm),
1609 EVENT_PTR(td_slots_retired_glm),
1610 NULL
1611 };
1612
1613 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1614 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1615 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1616 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1617 EVENT_EXTRA_END
1618 };
1619
1620 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1621 #define GLM_DEMAND_RFO BIT_ULL(1)
1622 #define GLM_ANY_RESPONSE BIT_ULL(16)
1623 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1624 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1625 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1626 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1627 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1628 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1629 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1630
1631 static __initconst const u64 glm_hw_cache_event_ids
1632 [PERF_COUNT_HW_CACHE_MAX]
1633 [PERF_COUNT_HW_CACHE_OP_MAX]
1634 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1635 [C(L1D)] = {
1636 [C(OP_READ)] = {
1637 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1638 [C(RESULT_MISS)] = 0x0,
1639 },
1640 [C(OP_WRITE)] = {
1641 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1642 [C(RESULT_MISS)] = 0x0,
1643 },
1644 [C(OP_PREFETCH)] = {
1645 [C(RESULT_ACCESS)] = 0x0,
1646 [C(RESULT_MISS)] = 0x0,
1647 },
1648 },
1649 [C(L1I)] = {
1650 [C(OP_READ)] = {
1651 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1652 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1653 },
1654 [C(OP_WRITE)] = {
1655 [C(RESULT_ACCESS)] = -1,
1656 [C(RESULT_MISS)] = -1,
1657 },
1658 [C(OP_PREFETCH)] = {
1659 [C(RESULT_ACCESS)] = 0x0,
1660 [C(RESULT_MISS)] = 0x0,
1661 },
1662 },
1663 [C(LL)] = {
1664 [C(OP_READ)] = {
1665 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1666 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1667 },
1668 [C(OP_WRITE)] = {
1669 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1670 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1671 },
1672 [C(OP_PREFETCH)] = {
1673 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1674 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1675 },
1676 },
1677 [C(DTLB)] = {
1678 [C(OP_READ)] = {
1679 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1680 [C(RESULT_MISS)] = 0x0,
1681 },
1682 [C(OP_WRITE)] = {
1683 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1684 [C(RESULT_MISS)] = 0x0,
1685 },
1686 [C(OP_PREFETCH)] = {
1687 [C(RESULT_ACCESS)] = 0x0,
1688 [C(RESULT_MISS)] = 0x0,
1689 },
1690 },
1691 [C(ITLB)] = {
1692 [C(OP_READ)] = {
1693 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1694 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1695 },
1696 [C(OP_WRITE)] = {
1697 [C(RESULT_ACCESS)] = -1,
1698 [C(RESULT_MISS)] = -1,
1699 },
1700 [C(OP_PREFETCH)] = {
1701 [C(RESULT_ACCESS)] = -1,
1702 [C(RESULT_MISS)] = -1,
1703 },
1704 },
1705 [C(BPU)] = {
1706 [C(OP_READ)] = {
1707 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1708 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1709 },
1710 [C(OP_WRITE)] = {
1711 [C(RESULT_ACCESS)] = -1,
1712 [C(RESULT_MISS)] = -1,
1713 },
1714 [C(OP_PREFETCH)] = {
1715 [C(RESULT_ACCESS)] = -1,
1716 [C(RESULT_MISS)] = -1,
1717 },
1718 },
1719 };
1720
1721 static __initconst const u64 glm_hw_cache_extra_regs
1722 [PERF_COUNT_HW_CACHE_MAX]
1723 [PERF_COUNT_HW_CACHE_OP_MAX]
1724 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1725 [C(LL)] = {
1726 [C(OP_READ)] = {
1727 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1728 GLM_LLC_ACCESS,
1729 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1730 GLM_LLC_MISS,
1731 },
1732 [C(OP_WRITE)] = {
1733 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1734 GLM_LLC_ACCESS,
1735 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1736 GLM_LLC_MISS,
1737 },
1738 [C(OP_PREFETCH)] = {
1739 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1740 GLM_LLC_ACCESS,
1741 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1742 GLM_LLC_MISS,
1743 },
1744 },
1745 };
1746
1747 static __initconst const u64 glp_hw_cache_event_ids
1748 [PERF_COUNT_HW_CACHE_MAX]
1749 [PERF_COUNT_HW_CACHE_OP_MAX]
1750 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1751 [C(L1D)] = {
1752 [C(OP_READ)] = {
1753 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1754 [C(RESULT_MISS)] = 0x0,
1755 },
1756 [C(OP_WRITE)] = {
1757 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1758 [C(RESULT_MISS)] = 0x0,
1759 },
1760 [C(OP_PREFETCH)] = {
1761 [C(RESULT_ACCESS)] = 0x0,
1762 [C(RESULT_MISS)] = 0x0,
1763 },
1764 },
1765 [C(L1I)] = {
1766 [C(OP_READ)] = {
1767 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1768 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1769 },
1770 [C(OP_WRITE)] = {
1771 [C(RESULT_ACCESS)] = -1,
1772 [C(RESULT_MISS)] = -1,
1773 },
1774 [C(OP_PREFETCH)] = {
1775 [C(RESULT_ACCESS)] = 0x0,
1776 [C(RESULT_MISS)] = 0x0,
1777 },
1778 },
1779 [C(LL)] = {
1780 [C(OP_READ)] = {
1781 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1782 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1783 },
1784 [C(OP_WRITE)] = {
1785 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1786 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1787 },
1788 [C(OP_PREFETCH)] = {
1789 [C(RESULT_ACCESS)] = 0x0,
1790 [C(RESULT_MISS)] = 0x0,
1791 },
1792 },
1793 [C(DTLB)] = {
1794 [C(OP_READ)] = {
1795 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1796 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1797 },
1798 [C(OP_WRITE)] = {
1799 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1800 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1801 },
1802 [C(OP_PREFETCH)] = {
1803 [C(RESULT_ACCESS)] = 0x0,
1804 [C(RESULT_MISS)] = 0x0,
1805 },
1806 },
1807 [C(ITLB)] = {
1808 [C(OP_READ)] = {
1809 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1810 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1811 },
1812 [C(OP_WRITE)] = {
1813 [C(RESULT_ACCESS)] = -1,
1814 [C(RESULT_MISS)] = -1,
1815 },
1816 [C(OP_PREFETCH)] = {
1817 [C(RESULT_ACCESS)] = -1,
1818 [C(RESULT_MISS)] = -1,
1819 },
1820 },
1821 [C(BPU)] = {
1822 [C(OP_READ)] = {
1823 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1824 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1825 },
1826 [C(OP_WRITE)] = {
1827 [C(RESULT_ACCESS)] = -1,
1828 [C(RESULT_MISS)] = -1,
1829 },
1830 [C(OP_PREFETCH)] = {
1831 [C(RESULT_ACCESS)] = -1,
1832 [C(RESULT_MISS)] = -1,
1833 },
1834 },
1835 };
1836
1837 static __initconst const u64 glp_hw_cache_extra_regs
1838 [PERF_COUNT_HW_CACHE_MAX]
1839 [PERF_COUNT_HW_CACHE_OP_MAX]
1840 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1841 [C(LL)] = {
1842 [C(OP_READ)] = {
1843 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1844 GLM_LLC_ACCESS,
1845 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1846 GLM_LLC_MISS,
1847 },
1848 [C(OP_WRITE)] = {
1849 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1850 GLM_LLC_ACCESS,
1851 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1852 GLM_LLC_MISS,
1853 },
1854 [C(OP_PREFETCH)] = {
1855 [C(RESULT_ACCESS)] = 0x0,
1856 [C(RESULT_MISS)] = 0x0,
1857 },
1858 },
1859 };
1860
1861 #define TNT_LOCAL_DRAM BIT_ULL(26)
1862 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
1863 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
1864 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
1865 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
1866 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
1867 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
1868
1869 static __initconst const u64 tnt_hw_cache_extra_regs
1870 [PERF_COUNT_HW_CACHE_MAX]
1871 [PERF_COUNT_HW_CACHE_OP_MAX]
1872 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1873 [C(LL)] = {
1874 [C(OP_READ)] = {
1875 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1876 TNT_LLC_ACCESS,
1877 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1878 TNT_LLC_MISS,
1879 },
1880 [C(OP_WRITE)] = {
1881 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1882 TNT_LLC_ACCESS,
1883 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1884 TNT_LLC_MISS,
1885 },
1886 [C(OP_PREFETCH)] = {
1887 [C(RESULT_ACCESS)] = 0x0,
1888 [C(RESULT_MISS)] = 0x0,
1889 },
1890 },
1891 };
1892
1893 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
1894 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1895 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
1896 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
1897 EVENT_EXTRA_END
1898 };
1899
1900 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1901 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1902 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1903 #define KNL_MCDRAM_FAR BIT_ULL(22)
1904 #define KNL_DDR_LOCAL BIT_ULL(23)
1905 #define KNL_DDR_FAR BIT_ULL(24)
1906 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1907 KNL_DDR_LOCAL | KNL_DDR_FAR)
1908 #define KNL_L2_READ SLM_DMND_READ
1909 #define KNL_L2_WRITE SLM_DMND_WRITE
1910 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1911 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1912 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1913 KNL_DRAM_ANY | SNB_SNP_ANY | \
1914 SNB_NON_DRAM)
1915
1916 static __initconst const u64 knl_hw_cache_extra_regs
1917 [PERF_COUNT_HW_CACHE_MAX]
1918 [PERF_COUNT_HW_CACHE_OP_MAX]
1919 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1920 [C(LL)] = {
1921 [C(OP_READ)] = {
1922 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1923 [C(RESULT_MISS)] = 0,
1924 },
1925 [C(OP_WRITE)] = {
1926 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1927 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1928 },
1929 [C(OP_PREFETCH)] = {
1930 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1931 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1932 },
1933 },
1934 };
1935
1936 /*
1937 * Used from PMIs where the LBRs are already disabled.
1938 *
1939 * This function could be called consecutively. It is required to remain in
1940 * disabled state if called consecutively.
1941 *
1942 * During consecutive calls, the same disable value will be written to related
1943 * registers, so the PMU state remains unchanged.
1944 *
1945 * intel_bts events don't coexist with intel PMU's BTS events because of
1946 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1947 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1948 *
1949 * Avoid PEBS_ENABLE MSR access in PMIs.
1950 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
1951 * It doesn't matter if the PEBS is enabled or not.
1952 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
1953 * access PEBS_ENABLE MSR in disable_all()/enable_all().
1954 * However, there are some cases which may change PEBS status, e.g. PMI
1955 * throttle. The PEBS_ENABLE should be updated where the status changes.
1956 */
1957 static void __intel_pmu_disable_all(void)
1958 {
1959 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1960
1961 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1962
1963 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1964 intel_pmu_disable_bts();
1965 }
1966
1967 static void intel_pmu_disable_all(void)
1968 {
1969 __intel_pmu_disable_all();
1970 intel_pmu_pebs_disable_all();
1971 intel_pmu_lbr_disable_all();
1972 }
1973
1974 static void __intel_pmu_enable_all(int added, bool pmi)
1975 {
1976 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1977
1978 intel_pmu_lbr_enable_all(pmi);
1979 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1980 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1981
1982 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1983 struct perf_event *event =
1984 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1985
1986 if (WARN_ON_ONCE(!event))
1987 return;
1988
1989 intel_pmu_enable_bts(event->hw.config);
1990 }
1991 }
1992
1993 static void intel_pmu_enable_all(int added)
1994 {
1995 intel_pmu_pebs_enable_all();
1996 __intel_pmu_enable_all(added, false);
1997 }
1998
1999 /*
2000 * Workaround for:
2001 * Intel Errata AAK100 (model 26)
2002 * Intel Errata AAP53 (model 30)
2003 * Intel Errata BD53 (model 44)
2004 *
2005 * The official story:
2006 * These chips need to be 'reset' when adding counters by programming the
2007 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2008 * in sequence on the same PMC or on different PMCs.
2009 *
2010 * In practise it appears some of these events do in fact count, and
2011 * we need to program all 4 events.
2012 */
2013 static void intel_pmu_nhm_workaround(void)
2014 {
2015 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2016 static const unsigned long nhm_magic[4] = {
2017 0x4300B5,
2018 0x4300D2,
2019 0x4300B1,
2020 0x4300B1
2021 };
2022 struct perf_event *event;
2023 int i;
2024
2025 /*
2026 * The Errata requires below steps:
2027 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2028 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2029 * the corresponding PMCx;
2030 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2031 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2032 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2033 */
2034
2035 /*
2036 * The real steps we choose are a little different from above.
2037 * A) To reduce MSR operations, we don't run step 1) as they
2038 * are already cleared before this function is called;
2039 * B) Call x86_perf_event_update to save PMCx before configuring
2040 * PERFEVTSELx with magic number;
2041 * C) With step 5), we do clear only when the PERFEVTSELx is
2042 * not used currently.
2043 * D) Call x86_perf_event_set_period to restore PMCx;
2044 */
2045
2046 /* We always operate 4 pairs of PERF Counters */
2047 for (i = 0; i < 4; i++) {
2048 event = cpuc->events[i];
2049 if (event)
2050 x86_perf_event_update(event);
2051 }
2052
2053 for (i = 0; i < 4; i++) {
2054 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2055 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2056 }
2057
2058 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2059 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2060
2061 for (i = 0; i < 4; i++) {
2062 event = cpuc->events[i];
2063
2064 if (event) {
2065 x86_perf_event_set_period(event);
2066 __x86_pmu_enable_event(&event->hw,
2067 ARCH_PERFMON_EVENTSEL_ENABLE);
2068 } else
2069 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2070 }
2071 }
2072
2073 static void intel_pmu_nhm_enable_all(int added)
2074 {
2075 if (added)
2076 intel_pmu_nhm_workaround();
2077 intel_pmu_enable_all(added);
2078 }
2079
2080 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2081 {
2082 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2083
2084 if (cpuc->tfa_shadow != val) {
2085 cpuc->tfa_shadow = val;
2086 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2087 }
2088 }
2089
2090 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2091 {
2092 /*
2093 * We're going to use PMC3, make sure TFA is set before we touch it.
2094 */
2095 if (cntr == 3)
2096 intel_set_tfa(cpuc, true);
2097 }
2098
2099 static void intel_tfa_pmu_enable_all(int added)
2100 {
2101 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2102
2103 /*
2104 * If we find PMC3 is no longer used when we enable the PMU, we can
2105 * clear TFA.
2106 */
2107 if (!test_bit(3, cpuc->active_mask))
2108 intel_set_tfa(cpuc, false);
2109
2110 intel_pmu_enable_all(added);
2111 }
2112
2113 static void enable_counter_freeze(void)
2114 {
2115 update_debugctlmsr(get_debugctlmsr() |
2116 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2117 }
2118
2119 static void disable_counter_freeze(void)
2120 {
2121 update_debugctlmsr(get_debugctlmsr() &
2122 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2123 }
2124
2125 static inline u64 intel_pmu_get_status(void)
2126 {
2127 u64 status;
2128
2129 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2130
2131 return status;
2132 }
2133
2134 static inline void intel_pmu_ack_status(u64 ack)
2135 {
2136 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2137 }
2138
2139 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
2140 {
2141 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2142 u64 ctrl_val, mask;
2143
2144 mask = 0xfULL << (idx * 4);
2145
2146 rdmsrl(hwc->config_base, ctrl_val);
2147 ctrl_val &= ~mask;
2148 wrmsrl(hwc->config_base, ctrl_val);
2149 }
2150
2151 static inline bool event_is_checkpointed(struct perf_event *event)
2152 {
2153 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2154 }
2155
2156 static void intel_pmu_disable_event(struct perf_event *event)
2157 {
2158 struct hw_perf_event *hwc = &event->hw;
2159 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2160
2161 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2162 intel_pmu_disable_bts();
2163 intel_pmu_drain_bts_buffer();
2164 return;
2165 }
2166
2167 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2168 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2169 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
2170
2171 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
2172 intel_pmu_disable_fixed(hwc);
2173 else
2174 x86_pmu_disable_event(event);
2175
2176 /*
2177 * Needs to be called after x86_pmu_disable_event,
2178 * so we don't trigger the event without PEBS bit set.
2179 */
2180 if (unlikely(event->attr.precise_ip))
2181 intel_pmu_pebs_disable(event);
2182 }
2183
2184 static void intel_pmu_del_event(struct perf_event *event)
2185 {
2186 if (needs_branch_stack(event))
2187 intel_pmu_lbr_del(event);
2188 if (event->attr.precise_ip)
2189 intel_pmu_pebs_del(event);
2190 }
2191
2192 static void intel_pmu_read_event(struct perf_event *event)
2193 {
2194 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2195 intel_pmu_auto_reload_read(event);
2196 else
2197 x86_perf_event_update(event);
2198 }
2199
2200 static void intel_pmu_enable_fixed(struct perf_event *event)
2201 {
2202 struct hw_perf_event *hwc = &event->hw;
2203 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2204 u64 ctrl_val, mask, bits = 0;
2205
2206 /*
2207 * Enable IRQ generation (0x8), if not PEBS,
2208 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2209 * if requested:
2210 */
2211 if (!event->attr.precise_ip)
2212 bits |= 0x8;
2213 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2214 bits |= 0x2;
2215 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2216 bits |= 0x1;
2217
2218 /*
2219 * ANY bit is supported in v3 and up
2220 */
2221 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2222 bits |= 0x4;
2223
2224 bits <<= (idx * 4);
2225 mask = 0xfULL << (idx * 4);
2226
2227 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2228 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2229 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2230 }
2231
2232 rdmsrl(hwc->config_base, ctrl_val);
2233 ctrl_val &= ~mask;
2234 ctrl_val |= bits;
2235 wrmsrl(hwc->config_base, ctrl_val);
2236 }
2237
2238 static void intel_pmu_enable_event(struct perf_event *event)
2239 {
2240 struct hw_perf_event *hwc = &event->hw;
2241 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2242
2243 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2244 if (!__this_cpu_read(cpu_hw_events.enabled))
2245 return;
2246
2247 intel_pmu_enable_bts(hwc->config);
2248 return;
2249 }
2250
2251 if (event->attr.exclude_host)
2252 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2253 if (event->attr.exclude_guest)
2254 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2255
2256 if (unlikely(event_is_checkpointed(event)))
2257 cpuc->intel_cp_status |= (1ull << hwc->idx);
2258
2259 if (unlikely(event->attr.precise_ip))
2260 intel_pmu_pebs_enable(event);
2261
2262 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2263 intel_pmu_enable_fixed(event);
2264 return;
2265 }
2266
2267 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2268 }
2269
2270 static void intel_pmu_add_event(struct perf_event *event)
2271 {
2272 if (event->attr.precise_ip)
2273 intel_pmu_pebs_add(event);
2274 if (needs_branch_stack(event))
2275 intel_pmu_lbr_add(event);
2276 }
2277
2278 /*
2279 * Save and restart an expired event. Called by NMI contexts,
2280 * so it has to be careful about preempting normal event ops:
2281 */
2282 int intel_pmu_save_and_restart(struct perf_event *event)
2283 {
2284 x86_perf_event_update(event);
2285 /*
2286 * For a checkpointed counter always reset back to 0. This
2287 * avoids a situation where the counter overflows, aborts the
2288 * transaction and is then set back to shortly before the
2289 * overflow, and overflows and aborts again.
2290 */
2291 if (unlikely(event_is_checkpointed(event))) {
2292 /* No race with NMIs because the counter should not be armed */
2293 wrmsrl(event->hw.event_base, 0);
2294 local64_set(&event->hw.prev_count, 0);
2295 }
2296 return x86_perf_event_set_period(event);
2297 }
2298
2299 static void intel_pmu_reset(void)
2300 {
2301 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2302 unsigned long flags;
2303 int idx;
2304
2305 if (!x86_pmu.num_counters)
2306 return;
2307
2308 local_irq_save(flags);
2309
2310 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2311
2312 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2313 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2314 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2315 }
2316 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2317 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2318
2319 if (ds)
2320 ds->bts_index = ds->bts_buffer_base;
2321
2322 /* Ack all overflows and disable fixed counters */
2323 if (x86_pmu.version >= 2) {
2324 intel_pmu_ack_status(intel_pmu_get_status());
2325 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2326 }
2327
2328 /* Reset LBRs and LBR freezing */
2329 if (x86_pmu.lbr_nr) {
2330 update_debugctlmsr(get_debugctlmsr() &
2331 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2332 }
2333
2334 local_irq_restore(flags);
2335 }
2336
2337 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2338 {
2339 struct perf_sample_data data;
2340 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2341 int bit;
2342 int handled = 0;
2343
2344 inc_irq_stat(apic_perf_irqs);
2345
2346 /*
2347 * Ignore a range of extra bits in status that do not indicate
2348 * overflow by themselves.
2349 */
2350 status &= ~(GLOBAL_STATUS_COND_CHG |
2351 GLOBAL_STATUS_ASIF |
2352 GLOBAL_STATUS_LBRS_FROZEN);
2353 if (!status)
2354 return 0;
2355 /*
2356 * In case multiple PEBS events are sampled at the same time,
2357 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2358 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2359 * having their bits set in the status register. This is a sign
2360 * that there was at least one PEBS record pending at the time
2361 * of the PMU interrupt. PEBS counters must only be processed
2362 * via the drain_pebs() calls and not via the regular sample
2363 * processing loop coming after that the function, otherwise
2364 * phony regular samples may be generated in the sampling buffer
2365 * not marked with the EXACT tag. Another possibility is to have
2366 * one PEBS event and at least one non-PEBS event whic hoverflows
2367 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2368 * not be set, yet the overflow status bit for the PEBS counter will
2369 * be on Skylake.
2370 *
2371 * To avoid this problem, we systematically ignore the PEBS-enabled
2372 * counters from the GLOBAL_STATUS mask and we always process PEBS
2373 * events via drain_pebs().
2374 */
2375 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2376 status &= ~cpuc->pebs_enabled;
2377 else
2378 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2379
2380 /*
2381 * PEBS overflow sets bit 62 in the global status register
2382 */
2383 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2384 u64 pebs_enabled = cpuc->pebs_enabled;
2385
2386 handled++;
2387 x86_pmu.drain_pebs(regs);
2388 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2389
2390 /*
2391 * PMI throttle may be triggered, which stops the PEBS event.
2392 * Although cpuc->pebs_enabled is updated accordingly, the
2393 * MSR_IA32_PEBS_ENABLE is not updated. Because the
2394 * cpuc->enabled has been forced to 0 in PMI.
2395 * Update the MSR if pebs_enabled is changed.
2396 */
2397 if (pebs_enabled != cpuc->pebs_enabled)
2398 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2399 }
2400
2401 /*
2402 * Intel PT
2403 */
2404 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2405 handled++;
2406 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2407 perf_guest_cbs->handle_intel_pt_intr))
2408 perf_guest_cbs->handle_intel_pt_intr();
2409 else
2410 intel_pt_interrupt();
2411 }
2412
2413 /*
2414 * Checkpointed counters can lead to 'spurious' PMIs because the
2415 * rollback caused by the PMI will have cleared the overflow status
2416 * bit. Therefore always force probe these counters.
2417 */
2418 status |= cpuc->intel_cp_status;
2419
2420 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2421 struct perf_event *event = cpuc->events[bit];
2422
2423 handled++;
2424
2425 if (!test_bit(bit, cpuc->active_mask))
2426 continue;
2427
2428 if (!intel_pmu_save_and_restart(event))
2429 continue;
2430
2431 perf_sample_data_init(&data, 0, event->hw.last_period);
2432
2433 if (has_branch_stack(event))
2434 data.br_stack = &cpuc->lbr_stack;
2435
2436 if (perf_event_overflow(event, &data, regs))
2437 x86_pmu_stop(event, 0);
2438 }
2439
2440 return handled;
2441 }
2442
2443 static bool disable_counter_freezing = true;
2444 static int __init intel_perf_counter_freezing_setup(char *s)
2445 {
2446 bool res;
2447
2448 if (kstrtobool(s, &res))
2449 return -EINVAL;
2450
2451 disable_counter_freezing = !res;
2452 return 1;
2453 }
2454 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
2455
2456 /*
2457 * Simplified handler for Arch Perfmon v4:
2458 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2459 * This is done automatically on PMU ack.
2460 * - Ack the PMU only after the APIC.
2461 */
2462
2463 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2464 {
2465 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2466 int handled = 0;
2467 bool bts = false;
2468 u64 status;
2469 int pmu_enabled = cpuc->enabled;
2470 int loops = 0;
2471
2472 /* PMU has been disabled because of counter freezing */
2473 cpuc->enabled = 0;
2474 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2475 bts = true;
2476 intel_bts_disable_local();
2477 handled = intel_pmu_drain_bts_buffer();
2478 handled += intel_bts_interrupt();
2479 }
2480 status = intel_pmu_get_status();
2481 if (!status)
2482 goto done;
2483 again:
2484 intel_pmu_lbr_read();
2485 if (++loops > 100) {
2486 static bool warned;
2487
2488 if (!warned) {
2489 WARN(1, "perfevents: irq loop stuck!\n");
2490 perf_event_print_debug();
2491 warned = true;
2492 }
2493 intel_pmu_reset();
2494 goto done;
2495 }
2496
2497
2498 handled += handle_pmi_common(regs, status);
2499 done:
2500 /* Ack the PMI in the APIC */
2501 apic_write(APIC_LVTPC, APIC_DM_NMI);
2502
2503 /*
2504 * The counters start counting immediately while ack the status.
2505 * Make it as close as possible to IRET. This avoids bogus
2506 * freezing on Skylake CPUs.
2507 */
2508 if (status) {
2509 intel_pmu_ack_status(status);
2510 } else {
2511 /*
2512 * CPU may issues two PMIs very close to each other.
2513 * When the PMI handler services the first one, the
2514 * GLOBAL_STATUS is already updated to reflect both.
2515 * When it IRETs, the second PMI is immediately
2516 * handled and it sees clear status. At the meantime,
2517 * there may be a third PMI, because the freezing bit
2518 * isn't set since the ack in first PMI handlers.
2519 * Double check if there is more work to be done.
2520 */
2521 status = intel_pmu_get_status();
2522 if (status)
2523 goto again;
2524 }
2525
2526 if (bts)
2527 intel_bts_enable_local();
2528 cpuc->enabled = pmu_enabled;
2529 return handled;
2530 }
2531
2532 /*
2533 * This handler is triggered by the local APIC, so the APIC IRQ handling
2534 * rules apply:
2535 */
2536 static int intel_pmu_handle_irq(struct pt_regs *regs)
2537 {
2538 struct cpu_hw_events *cpuc;
2539 int loops;
2540 u64 status;
2541 int handled;
2542 int pmu_enabled;
2543
2544 cpuc = this_cpu_ptr(&cpu_hw_events);
2545
2546 /*
2547 * Save the PMU state.
2548 * It needs to be restored when leaving the handler.
2549 */
2550 pmu_enabled = cpuc->enabled;
2551 /*
2552 * No known reason to not always do late ACK,
2553 * but just in case do it opt-in.
2554 */
2555 if (!x86_pmu.late_ack)
2556 apic_write(APIC_LVTPC, APIC_DM_NMI);
2557 intel_bts_disable_local();
2558 cpuc->enabled = 0;
2559 __intel_pmu_disable_all();
2560 handled = intel_pmu_drain_bts_buffer();
2561 handled += intel_bts_interrupt();
2562 status = intel_pmu_get_status();
2563 if (!status)
2564 goto done;
2565
2566 loops = 0;
2567 again:
2568 intel_pmu_lbr_read();
2569 intel_pmu_ack_status(status);
2570 if (++loops > 100) {
2571 static bool warned;
2572
2573 if (!warned) {
2574 WARN(1, "perfevents: irq loop stuck!\n");
2575 perf_event_print_debug();
2576 warned = true;
2577 }
2578 intel_pmu_reset();
2579 goto done;
2580 }
2581
2582 handled += handle_pmi_common(regs, status);
2583
2584 /*
2585 * Repeat if there is more work to be done:
2586 */
2587 status = intel_pmu_get_status();
2588 if (status)
2589 goto again;
2590
2591 done:
2592 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2593 cpuc->enabled = pmu_enabled;
2594 if (pmu_enabled)
2595 __intel_pmu_enable_all(0, true);
2596 intel_bts_enable_local();
2597
2598 /*
2599 * Only unmask the NMI after the overflow counters
2600 * have been reset. This avoids spurious NMIs on
2601 * Haswell CPUs.
2602 */
2603 if (x86_pmu.late_ack)
2604 apic_write(APIC_LVTPC, APIC_DM_NMI);
2605 return handled;
2606 }
2607
2608 static struct event_constraint *
2609 intel_bts_constraints(struct perf_event *event)
2610 {
2611 if (unlikely(intel_pmu_has_bts(event)))
2612 return &bts_constraint;
2613
2614 return NULL;
2615 }
2616
2617 static int intel_alt_er(int idx, u64 config)
2618 {
2619 int alt_idx = idx;
2620
2621 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2622 return idx;
2623
2624 if (idx == EXTRA_REG_RSP_0)
2625 alt_idx = EXTRA_REG_RSP_1;
2626
2627 if (idx == EXTRA_REG_RSP_1)
2628 alt_idx = EXTRA_REG_RSP_0;
2629
2630 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2631 return idx;
2632
2633 return alt_idx;
2634 }
2635
2636 static void intel_fixup_er(struct perf_event *event, int idx)
2637 {
2638 event->hw.extra_reg.idx = idx;
2639
2640 if (idx == EXTRA_REG_RSP_0) {
2641 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2642 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2643 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2644 } else if (idx == EXTRA_REG_RSP_1) {
2645 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2646 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2647 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2648 }
2649 }
2650
2651 /*
2652 * manage allocation of shared extra msr for certain events
2653 *
2654 * sharing can be:
2655 * per-cpu: to be shared between the various events on a single PMU
2656 * per-core: per-cpu + shared by HT threads
2657 */
2658 static struct event_constraint *
2659 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2660 struct perf_event *event,
2661 struct hw_perf_event_extra *reg)
2662 {
2663 struct event_constraint *c = &emptyconstraint;
2664 struct er_account *era;
2665 unsigned long flags;
2666 int idx = reg->idx;
2667
2668 /*
2669 * reg->alloc can be set due to existing state, so for fake cpuc we
2670 * need to ignore this, otherwise we might fail to allocate proper fake
2671 * state for this extra reg constraint. Also see the comment below.
2672 */
2673 if (reg->alloc && !cpuc->is_fake)
2674 return NULL; /* call x86_get_event_constraint() */
2675
2676 again:
2677 era = &cpuc->shared_regs->regs[idx];
2678 /*
2679 * we use spin_lock_irqsave() to avoid lockdep issues when
2680 * passing a fake cpuc
2681 */
2682 raw_spin_lock_irqsave(&era->lock, flags);
2683
2684 if (!atomic_read(&era->ref) || era->config == reg->config) {
2685
2686 /*
2687 * If its a fake cpuc -- as per validate_{group,event}() we
2688 * shouldn't touch event state and we can avoid doing so
2689 * since both will only call get_event_constraints() once
2690 * on each event, this avoids the need for reg->alloc.
2691 *
2692 * Not doing the ER fixup will only result in era->reg being
2693 * wrong, but since we won't actually try and program hardware
2694 * this isn't a problem either.
2695 */
2696 if (!cpuc->is_fake) {
2697 if (idx != reg->idx)
2698 intel_fixup_er(event, idx);
2699
2700 /*
2701 * x86_schedule_events() can call get_event_constraints()
2702 * multiple times on events in the case of incremental
2703 * scheduling(). reg->alloc ensures we only do the ER
2704 * allocation once.
2705 */
2706 reg->alloc = 1;
2707 }
2708
2709 /* lock in msr value */
2710 era->config = reg->config;
2711 era->reg = reg->reg;
2712
2713 /* one more user */
2714 atomic_inc(&era->ref);
2715
2716 /*
2717 * need to call x86_get_event_constraint()
2718 * to check if associated event has constraints
2719 */
2720 c = NULL;
2721 } else {
2722 idx = intel_alt_er(idx, reg->config);
2723 if (idx != reg->idx) {
2724 raw_spin_unlock_irqrestore(&era->lock, flags);
2725 goto again;
2726 }
2727 }
2728 raw_spin_unlock_irqrestore(&era->lock, flags);
2729
2730 return c;
2731 }
2732
2733 static void
2734 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2735 struct hw_perf_event_extra *reg)
2736 {
2737 struct er_account *era;
2738
2739 /*
2740 * Only put constraint if extra reg was actually allocated. Also takes
2741 * care of event which do not use an extra shared reg.
2742 *
2743 * Also, if this is a fake cpuc we shouldn't touch any event state
2744 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2745 * either since it'll be thrown out.
2746 */
2747 if (!reg->alloc || cpuc->is_fake)
2748 return;
2749
2750 era = &cpuc->shared_regs->regs[reg->idx];
2751
2752 /* one fewer user */
2753 atomic_dec(&era->ref);
2754
2755 /* allocate again next time */
2756 reg->alloc = 0;
2757 }
2758
2759 static struct event_constraint *
2760 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2761 struct perf_event *event)
2762 {
2763 struct event_constraint *c = NULL, *d;
2764 struct hw_perf_event_extra *xreg, *breg;
2765
2766 xreg = &event->hw.extra_reg;
2767 if (xreg->idx != EXTRA_REG_NONE) {
2768 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2769 if (c == &emptyconstraint)
2770 return c;
2771 }
2772 breg = &event->hw.branch_reg;
2773 if (breg->idx != EXTRA_REG_NONE) {
2774 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2775 if (d == &emptyconstraint) {
2776 __intel_shared_reg_put_constraints(cpuc, xreg);
2777 c = d;
2778 }
2779 }
2780 return c;
2781 }
2782
2783 struct event_constraint *
2784 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2785 struct perf_event *event)
2786 {
2787 struct event_constraint *c;
2788
2789 if (x86_pmu.event_constraints) {
2790 for_each_event_constraint(c, x86_pmu.event_constraints) {
2791 if (constraint_match(c, event->hw.config)) {
2792 event->hw.flags |= c->flags;
2793 return c;
2794 }
2795 }
2796 }
2797
2798 return &unconstrained;
2799 }
2800
2801 static struct event_constraint *
2802 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2803 struct perf_event *event)
2804 {
2805 struct event_constraint *c;
2806
2807 c = intel_bts_constraints(event);
2808 if (c)
2809 return c;
2810
2811 c = intel_shared_regs_constraints(cpuc, event);
2812 if (c)
2813 return c;
2814
2815 c = intel_pebs_constraints(event);
2816 if (c)
2817 return c;
2818
2819 return x86_get_event_constraints(cpuc, idx, event);
2820 }
2821
2822 static void
2823 intel_start_scheduling(struct cpu_hw_events *cpuc)
2824 {
2825 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2826 struct intel_excl_states *xl;
2827 int tid = cpuc->excl_thread_id;
2828
2829 /*
2830 * nothing needed if in group validation mode
2831 */
2832 if (cpuc->is_fake || !is_ht_workaround_enabled())
2833 return;
2834
2835 /*
2836 * no exclusion needed
2837 */
2838 if (WARN_ON_ONCE(!excl_cntrs))
2839 return;
2840
2841 xl = &excl_cntrs->states[tid];
2842
2843 xl->sched_started = true;
2844 /*
2845 * lock shared state until we are done scheduling
2846 * in stop_event_scheduling()
2847 * makes scheduling appear as a transaction
2848 */
2849 raw_spin_lock(&excl_cntrs->lock);
2850 }
2851
2852 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2853 {
2854 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2855 struct event_constraint *c = cpuc->event_constraint[idx];
2856 struct intel_excl_states *xl;
2857 int tid = cpuc->excl_thread_id;
2858
2859 if (cpuc->is_fake || !is_ht_workaround_enabled())
2860 return;
2861
2862 if (WARN_ON_ONCE(!excl_cntrs))
2863 return;
2864
2865 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2866 return;
2867
2868 xl = &excl_cntrs->states[tid];
2869
2870 lockdep_assert_held(&excl_cntrs->lock);
2871
2872 if (c->flags & PERF_X86_EVENT_EXCL)
2873 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2874 else
2875 xl->state[cntr] = INTEL_EXCL_SHARED;
2876 }
2877
2878 static void
2879 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2880 {
2881 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2882 struct intel_excl_states *xl;
2883 int tid = cpuc->excl_thread_id;
2884
2885 /*
2886 * nothing needed if in group validation mode
2887 */
2888 if (cpuc->is_fake || !is_ht_workaround_enabled())
2889 return;
2890 /*
2891 * no exclusion needed
2892 */
2893 if (WARN_ON_ONCE(!excl_cntrs))
2894 return;
2895
2896 xl = &excl_cntrs->states[tid];
2897
2898 xl->sched_started = false;
2899 /*
2900 * release shared state lock (acquired in intel_start_scheduling())
2901 */
2902 raw_spin_unlock(&excl_cntrs->lock);
2903 }
2904
2905 static struct event_constraint *
2906 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
2907 {
2908 WARN_ON_ONCE(!cpuc->constraint_list);
2909
2910 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2911 struct event_constraint *cx;
2912
2913 /*
2914 * grab pre-allocated constraint entry
2915 */
2916 cx = &cpuc->constraint_list[idx];
2917
2918 /*
2919 * initialize dynamic constraint
2920 * with static constraint
2921 */
2922 *cx = *c;
2923
2924 /*
2925 * mark constraint as dynamic
2926 */
2927 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2928 c = cx;
2929 }
2930
2931 return c;
2932 }
2933
2934 static struct event_constraint *
2935 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2936 int idx, struct event_constraint *c)
2937 {
2938 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2939 struct intel_excl_states *xlo;
2940 int tid = cpuc->excl_thread_id;
2941 int is_excl, i, w;
2942
2943 /*
2944 * validating a group does not require
2945 * enforcing cross-thread exclusion
2946 */
2947 if (cpuc->is_fake || !is_ht_workaround_enabled())
2948 return c;
2949
2950 /*
2951 * no exclusion needed
2952 */
2953 if (WARN_ON_ONCE(!excl_cntrs))
2954 return c;
2955
2956 /*
2957 * because we modify the constraint, we need
2958 * to make a copy. Static constraints come
2959 * from static const tables.
2960 *
2961 * only needed when constraint has not yet
2962 * been cloned (marked dynamic)
2963 */
2964 c = dyn_constraint(cpuc, c, idx);
2965
2966 /*
2967 * From here on, the constraint is dynamic.
2968 * Either it was just allocated above, or it
2969 * was allocated during a earlier invocation
2970 * of this function
2971 */
2972
2973 /*
2974 * state of sibling HT
2975 */
2976 xlo = &excl_cntrs->states[tid ^ 1];
2977
2978 /*
2979 * event requires exclusive counter access
2980 * across HT threads
2981 */
2982 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2983 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2984 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2985 if (!cpuc->n_excl++)
2986 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2987 }
2988
2989 /*
2990 * Modify static constraint with current dynamic
2991 * state of thread
2992 *
2993 * EXCLUSIVE: sibling counter measuring exclusive event
2994 * SHARED : sibling counter measuring non-exclusive event
2995 * UNUSED : sibling counter unused
2996 */
2997 w = c->weight;
2998 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2999 /*
3000 * exclusive event in sibling counter
3001 * our corresponding counter cannot be used
3002 * regardless of our event
3003 */
3004 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3005 __clear_bit(i, c->idxmsk);
3006 w--;
3007 continue;
3008 }
3009 /*
3010 * if measuring an exclusive event, sibling
3011 * measuring non-exclusive, then counter cannot
3012 * be used
3013 */
3014 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3015 __clear_bit(i, c->idxmsk);
3016 w--;
3017 continue;
3018 }
3019 }
3020
3021 /*
3022 * if we return an empty mask, then switch
3023 * back to static empty constraint to avoid
3024 * the cost of freeing later on
3025 */
3026 if (!w)
3027 c = &emptyconstraint;
3028
3029 c->weight = w;
3030
3031 return c;
3032 }
3033
3034 static struct event_constraint *
3035 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3036 struct perf_event *event)
3037 {
3038 struct event_constraint *c1, *c2;
3039
3040 c1 = cpuc->event_constraint[idx];
3041
3042 /*
3043 * first time only
3044 * - static constraint: no change across incremental scheduling calls
3045 * - dynamic constraint: handled by intel_get_excl_constraints()
3046 */
3047 c2 = __intel_get_event_constraints(cpuc, idx, event);
3048 if (c1) {
3049 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3050 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3051 c1->weight = c2->weight;
3052 c2 = c1;
3053 }
3054
3055 if (cpuc->excl_cntrs)
3056 return intel_get_excl_constraints(cpuc, event, idx, c2);
3057
3058 return c2;
3059 }
3060
3061 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3062 struct perf_event *event)
3063 {
3064 struct hw_perf_event *hwc = &event->hw;
3065 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3066 int tid = cpuc->excl_thread_id;
3067 struct intel_excl_states *xl;
3068
3069 /*
3070 * nothing needed if in group validation mode
3071 */
3072 if (cpuc->is_fake)
3073 return;
3074
3075 if (WARN_ON_ONCE(!excl_cntrs))
3076 return;
3077
3078 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3079 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3080 if (!--cpuc->n_excl)
3081 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3082 }
3083
3084 /*
3085 * If event was actually assigned, then mark the counter state as
3086 * unused now.
3087 */
3088 if (hwc->idx >= 0) {
3089 xl = &excl_cntrs->states[tid];
3090
3091 /*
3092 * put_constraint may be called from x86_schedule_events()
3093 * which already has the lock held so here make locking
3094 * conditional.
3095 */
3096 if (!xl->sched_started)
3097 raw_spin_lock(&excl_cntrs->lock);
3098
3099 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3100
3101 if (!xl->sched_started)
3102 raw_spin_unlock(&excl_cntrs->lock);
3103 }
3104 }
3105
3106 static void
3107 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3108 struct perf_event *event)
3109 {
3110 struct hw_perf_event_extra *reg;
3111
3112 reg = &event->hw.extra_reg;
3113 if (reg->idx != EXTRA_REG_NONE)
3114 __intel_shared_reg_put_constraints(cpuc, reg);
3115
3116 reg = &event->hw.branch_reg;
3117 if (reg->idx != EXTRA_REG_NONE)
3118 __intel_shared_reg_put_constraints(cpuc, reg);
3119 }
3120
3121 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3122 struct perf_event *event)
3123 {
3124 intel_put_shared_regs_event_constraints(cpuc, event);
3125
3126 /*
3127 * is PMU has exclusive counter restrictions, then
3128 * all events are subject to and must call the
3129 * put_excl_constraints() routine
3130 */
3131 if (cpuc->excl_cntrs)
3132 intel_put_excl_constraints(cpuc, event);
3133 }
3134
3135 static void intel_pebs_aliases_core2(struct perf_event *event)
3136 {
3137 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3138 /*
3139 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3140 * (0x003c) so that we can use it with PEBS.
3141 *
3142 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3143 * PEBS capable. However we can use INST_RETIRED.ANY_P
3144 * (0x00c0), which is a PEBS capable event, to get the same
3145 * count.
3146 *
3147 * INST_RETIRED.ANY_P counts the number of cycles that retires
3148 * CNTMASK instructions. By setting CNTMASK to a value (16)
3149 * larger than the maximum number of instructions that can be
3150 * retired per cycle (4) and then inverting the condition, we
3151 * count all cycles that retire 16 or less instructions, which
3152 * is every cycle.
3153 *
3154 * Thereby we gain a PEBS capable cycle counter.
3155 */
3156 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3157
3158 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3159 event->hw.config = alt_config;
3160 }
3161 }
3162
3163 static void intel_pebs_aliases_snb(struct perf_event *event)
3164 {
3165 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3166 /*
3167 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3168 * (0x003c) so that we can use it with PEBS.
3169 *
3170 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3171 * PEBS capable. However we can use UOPS_RETIRED.ALL
3172 * (0x01c2), which is a PEBS capable event, to get the same
3173 * count.
3174 *
3175 * UOPS_RETIRED.ALL counts the number of cycles that retires
3176 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3177 * larger than the maximum number of micro-ops that can be
3178 * retired per cycle (4) and then inverting the condition, we
3179 * count all cycles that retire 16 or less micro-ops, which
3180 * is every cycle.
3181 *
3182 * Thereby we gain a PEBS capable cycle counter.
3183 */
3184 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3185
3186 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3187 event->hw.config = alt_config;
3188 }
3189 }
3190
3191 static void intel_pebs_aliases_precdist(struct perf_event *event)
3192 {
3193 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3194 /*
3195 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3196 * (0x003c) so that we can use it with PEBS.
3197 *
3198 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3199 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3200 * (0x01c0), which is a PEBS capable event, to get the same
3201 * count.
3202 *
3203 * The PREC_DIST event has special support to minimize sample
3204 * shadowing effects. One drawback is that it can be
3205 * only programmed on counter 1, but that seems like an
3206 * acceptable trade off.
3207 */
3208 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3209
3210 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3211 event->hw.config = alt_config;
3212 }
3213 }
3214
3215 static void intel_pebs_aliases_ivb(struct perf_event *event)
3216 {
3217 if (event->attr.precise_ip < 3)
3218 return intel_pebs_aliases_snb(event);
3219 return intel_pebs_aliases_precdist(event);
3220 }
3221
3222 static void intel_pebs_aliases_skl(struct perf_event *event)
3223 {
3224 if (event->attr.precise_ip < 3)
3225 return intel_pebs_aliases_core2(event);
3226 return intel_pebs_aliases_precdist(event);
3227 }
3228
3229 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3230 {
3231 unsigned long flags = x86_pmu.large_pebs_flags;
3232
3233 if (event->attr.use_clockid)
3234 flags &= ~PERF_SAMPLE_TIME;
3235 if (!event->attr.exclude_kernel)
3236 flags &= ~PERF_SAMPLE_REGS_USER;
3237 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3238 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3239 return flags;
3240 }
3241
3242 static int intel_pmu_bts_config(struct perf_event *event)
3243 {
3244 struct perf_event_attr *attr = &event->attr;
3245
3246 if (unlikely(intel_pmu_has_bts(event))) {
3247 /* BTS is not supported by this architecture. */
3248 if (!x86_pmu.bts_active)
3249 return -EOPNOTSUPP;
3250
3251 /* BTS is currently only allowed for user-mode. */
3252 if (!attr->exclude_kernel)
3253 return -EOPNOTSUPP;
3254
3255 /* BTS is not allowed for precise events. */
3256 if (attr->precise_ip)
3257 return -EOPNOTSUPP;
3258
3259 /* disallow bts if conflicting events are present */
3260 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3261 return -EBUSY;
3262
3263 event->destroy = hw_perf_lbr_event_destroy;
3264 }
3265
3266 return 0;
3267 }
3268
3269 static int core_pmu_hw_config(struct perf_event *event)
3270 {
3271 int ret = x86_pmu_hw_config(event);
3272
3273 if (ret)
3274 return ret;
3275
3276 return intel_pmu_bts_config(event);
3277 }
3278
3279 static int intel_pmu_hw_config(struct perf_event *event)
3280 {
3281 int ret = x86_pmu_hw_config(event);
3282
3283 if (ret)
3284 return ret;
3285
3286 ret = intel_pmu_bts_config(event);
3287 if (ret)
3288 return ret;
3289
3290 if (event->attr.precise_ip) {
3291 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3292 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3293 if (!(event->attr.sample_type &
3294 ~intel_pmu_large_pebs_flags(event)))
3295 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3296 }
3297 if (x86_pmu.pebs_aliases)
3298 x86_pmu.pebs_aliases(event);
3299
3300 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3301 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3302 }
3303
3304 if (needs_branch_stack(event)) {
3305 ret = intel_pmu_setup_lbr_filter(event);
3306 if (ret)
3307 return ret;
3308
3309 /*
3310 * BTS is set up earlier in this path, so don't account twice
3311 */
3312 if (!unlikely(intel_pmu_has_bts(event))) {
3313 /* disallow lbr if conflicting events are present */
3314 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3315 return -EBUSY;
3316
3317 event->destroy = hw_perf_lbr_event_destroy;
3318 }
3319 }
3320
3321 if (event->attr.aux_output) {
3322 if (!event->attr.precise_ip)
3323 return -EINVAL;
3324
3325 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3326 }
3327
3328 if (event->attr.type != PERF_TYPE_RAW)
3329 return 0;
3330
3331 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3332 return 0;
3333
3334 if (x86_pmu.version < 3)
3335 return -EINVAL;
3336
3337 ret = perf_allow_cpu(&event->attr);
3338 if (ret)
3339 return ret;
3340
3341 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3342
3343 return 0;
3344 }
3345
3346 #ifdef CONFIG_RETPOLINE
3347 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr);
3348 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr);
3349 #endif
3350
3351 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3352 {
3353 #ifdef CONFIG_RETPOLINE
3354 if (x86_pmu.guest_get_msrs == intel_guest_get_msrs)
3355 return intel_guest_get_msrs(nr);
3356 else if (x86_pmu.guest_get_msrs == core_guest_get_msrs)
3357 return core_guest_get_msrs(nr);
3358 #endif
3359 if (x86_pmu.guest_get_msrs)
3360 return x86_pmu.guest_get_msrs(nr);
3361 *nr = 0;
3362 return NULL;
3363 }
3364 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3365
3366 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3367 {
3368 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3369 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3370
3371 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3372 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3373 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3374 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3375 arr[0].guest &= ~cpuc->pebs_enabled;
3376 else
3377 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3378 *nr = 1;
3379
3380 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3381 /*
3382 * If PMU counter has PEBS enabled it is not enough to
3383 * disable counter on a guest entry since PEBS memory
3384 * write can overshoot guest entry and corrupt guest
3385 * memory. Disabling PEBS solves the problem.
3386 *
3387 * Don't do this if the CPU already enforces it.
3388 */
3389 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3390 arr[1].host = cpuc->pebs_enabled;
3391 arr[1].guest = 0;
3392 *nr = 2;
3393 }
3394
3395 return arr;
3396 }
3397
3398 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3399 {
3400 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3401 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3402 int idx;
3403
3404 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3405 struct perf_event *event = cpuc->events[idx];
3406
3407 arr[idx].msr = x86_pmu_config_addr(idx);
3408 arr[idx].host = arr[idx].guest = 0;
3409
3410 if (!test_bit(idx, cpuc->active_mask))
3411 continue;
3412
3413 arr[idx].host = arr[idx].guest =
3414 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3415
3416 if (event->attr.exclude_host)
3417 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3418 else if (event->attr.exclude_guest)
3419 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3420 }
3421
3422 *nr = x86_pmu.num_counters;
3423 return arr;
3424 }
3425
3426 static void core_pmu_enable_event(struct perf_event *event)
3427 {
3428 if (!event->attr.exclude_host)
3429 x86_pmu_enable_event(event);
3430 }
3431
3432 static void core_pmu_enable_all(int added)
3433 {
3434 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3435 int idx;
3436
3437 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3438 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3439
3440 if (!test_bit(idx, cpuc->active_mask) ||
3441 cpuc->events[idx]->attr.exclude_host)
3442 continue;
3443
3444 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3445 }
3446 }
3447
3448 static int hsw_hw_config(struct perf_event *event)
3449 {
3450 int ret = intel_pmu_hw_config(event);
3451
3452 if (ret)
3453 return ret;
3454 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3455 return 0;
3456 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3457
3458 /*
3459 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3460 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3461 * this combination.
3462 */
3463 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3464 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3465 event->attr.precise_ip > 0))
3466 return -EOPNOTSUPP;
3467
3468 if (event_is_checkpointed(event)) {
3469 /*
3470 * Sampling of checkpointed events can cause situations where
3471 * the CPU constantly aborts because of a overflow, which is
3472 * then checkpointed back and ignored. Forbid checkpointing
3473 * for sampling.
3474 *
3475 * But still allow a long sampling period, so that perf stat
3476 * from KVM works.
3477 */
3478 if (event->attr.sample_period > 0 &&
3479 event->attr.sample_period < 0x7fffffff)
3480 return -EOPNOTSUPP;
3481 }
3482 return 0;
3483 }
3484
3485 static struct event_constraint counter0_constraint =
3486 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3487
3488 static struct event_constraint counter2_constraint =
3489 EVENT_CONSTRAINT(0, 0x4, 0);
3490
3491 static struct event_constraint fixed0_constraint =
3492 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3493
3494 static struct event_constraint fixed0_counter0_constraint =
3495 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3496
3497 static struct event_constraint *
3498 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3499 struct perf_event *event)
3500 {
3501 struct event_constraint *c;
3502
3503 c = intel_get_event_constraints(cpuc, idx, event);
3504
3505 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3506 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3507 if (c->idxmsk64 & (1U << 2))
3508 return &counter2_constraint;
3509 return &emptyconstraint;
3510 }
3511
3512 return c;
3513 }
3514
3515 static struct event_constraint *
3516 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3517 struct perf_event *event)
3518 {
3519 /*
3520 * Fixed counter 0 has less skid.
3521 * Force instruction:ppp in Fixed counter 0
3522 */
3523 if ((event->attr.precise_ip == 3) &&
3524 constraint_match(&fixed0_constraint, event->hw.config))
3525 return &fixed0_constraint;
3526
3527 return hsw_get_event_constraints(cpuc, idx, event);
3528 }
3529
3530 static struct event_constraint *
3531 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3532 struct perf_event *event)
3533 {
3534 struct event_constraint *c;
3535
3536 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3537 if (event->attr.precise_ip == 3)
3538 return &counter0_constraint;
3539
3540 c = intel_get_event_constraints(cpuc, idx, event);
3541
3542 return c;
3543 }
3544
3545 static struct event_constraint *
3546 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3547 struct perf_event *event)
3548 {
3549 struct event_constraint *c;
3550
3551 /*
3552 * :ppp means to do reduced skid PEBS,
3553 * which is available on PMC0 and fixed counter 0.
3554 */
3555 if (event->attr.precise_ip == 3) {
3556 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
3557 if (constraint_match(&fixed0_constraint, event->hw.config))
3558 return &fixed0_counter0_constraint;
3559
3560 return &counter0_constraint;
3561 }
3562
3563 c = intel_get_event_constraints(cpuc, idx, event);
3564
3565 return c;
3566 }
3567
3568 static bool allow_tsx_force_abort = true;
3569
3570 static struct event_constraint *
3571 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3572 struct perf_event *event)
3573 {
3574 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3575
3576 /*
3577 * Without TFA we must not use PMC3.
3578 */
3579 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3580 c = dyn_constraint(cpuc, c, idx);
3581 c->idxmsk64 &= ~(1ULL << 3);
3582 c->weight--;
3583 }
3584
3585 return c;
3586 }
3587
3588 /*
3589 * Broadwell:
3590 *
3591 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3592 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3593 * the two to enforce a minimum period of 128 (the smallest value that has bits
3594 * 0-5 cleared and >= 100).
3595 *
3596 * Because of how the code in x86_perf_event_set_period() works, the truncation
3597 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3598 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3599 *
3600 * Therefore the effective (average) period matches the requested period,
3601 * despite coarser hardware granularity.
3602 */
3603 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3604 {
3605 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3606 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3607 if (left < 128)
3608 left = 128;
3609 left &= ~0x3fULL;
3610 }
3611 return left;
3612 }
3613
3614 static u64 nhm_limit_period(struct perf_event *event, u64 left)
3615 {
3616 return max(left, 32ULL);
3617 }
3618
3619 PMU_FORMAT_ATTR(event, "config:0-7" );
3620 PMU_FORMAT_ATTR(umask, "config:8-15" );
3621 PMU_FORMAT_ATTR(edge, "config:18" );
3622 PMU_FORMAT_ATTR(pc, "config:19" );
3623 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3624 PMU_FORMAT_ATTR(inv, "config:23" );
3625 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3626 PMU_FORMAT_ATTR(in_tx, "config:32");
3627 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3628
3629 static struct attribute *intel_arch_formats_attr[] = {
3630 &format_attr_event.attr,
3631 &format_attr_umask.attr,
3632 &format_attr_edge.attr,
3633 &format_attr_pc.attr,
3634 &format_attr_inv.attr,
3635 &format_attr_cmask.attr,
3636 NULL,
3637 };
3638
3639 ssize_t intel_event_sysfs_show(char *page, u64 config)
3640 {
3641 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3642
3643 return x86_event_sysfs_show(page, config, event);
3644 }
3645
3646 static struct intel_shared_regs *allocate_shared_regs(int cpu)
3647 {
3648 struct intel_shared_regs *regs;
3649 int i;
3650
3651 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3652 GFP_KERNEL, cpu_to_node(cpu));
3653 if (regs) {
3654 /*
3655 * initialize the locks to keep lockdep happy
3656 */
3657 for (i = 0; i < EXTRA_REG_MAX; i++)
3658 raw_spin_lock_init(&regs->regs[i].lock);
3659
3660 regs->core_id = -1;
3661 }
3662 return regs;
3663 }
3664
3665 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3666 {
3667 struct intel_excl_cntrs *c;
3668
3669 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3670 GFP_KERNEL, cpu_to_node(cpu));
3671 if (c) {
3672 raw_spin_lock_init(&c->lock);
3673 c->core_id = -1;
3674 }
3675 return c;
3676 }
3677
3678
3679 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
3680 {
3681 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
3682
3683 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3684 cpuc->shared_regs = allocate_shared_regs(cpu);
3685 if (!cpuc->shared_regs)
3686 goto err;
3687 }
3688
3689 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
3690 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3691
3692 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
3693 if (!cpuc->constraint_list)
3694 goto err_shared_regs;
3695 }
3696
3697 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3698 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3699 if (!cpuc->excl_cntrs)
3700 goto err_constraint_list;
3701
3702 cpuc->excl_thread_id = 0;
3703 }
3704
3705 return 0;
3706
3707 err_constraint_list:
3708 kfree(cpuc->constraint_list);
3709 cpuc->constraint_list = NULL;
3710
3711 err_shared_regs:
3712 kfree(cpuc->shared_regs);
3713 cpuc->shared_regs = NULL;
3714
3715 err:
3716 return -ENOMEM;
3717 }
3718
3719 static int intel_pmu_cpu_prepare(int cpu)
3720 {
3721 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
3722 }
3723
3724 static void flip_smm_bit(void *data)
3725 {
3726 unsigned long set = *(unsigned long *)data;
3727
3728 if (set > 0) {
3729 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3730 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3731 } else {
3732 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3733 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3734 }
3735 }
3736
3737 static void intel_pmu_cpu_starting(int cpu)
3738 {
3739 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3740 int core_id = topology_core_id(cpu);
3741 int i;
3742
3743 init_debug_store_on_cpu(cpu);
3744 /*
3745 * Deal with CPUs that don't clear their LBRs on power-up.
3746 */
3747 intel_pmu_lbr_reset();
3748
3749 cpuc->lbr_sel = NULL;
3750
3751 if (x86_pmu.flags & PMU_FL_TFA) {
3752 WARN_ON_ONCE(cpuc->tfa_shadow);
3753 cpuc->tfa_shadow = ~0ULL;
3754 intel_set_tfa(cpuc, false);
3755 }
3756
3757 if (x86_pmu.version > 1)
3758 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
3759
3760 if (x86_pmu.counter_freezing)
3761 enable_counter_freeze();
3762
3763 if (!cpuc->shared_regs)
3764 return;
3765
3766 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3767 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3768 struct intel_shared_regs *pc;
3769
3770 pc = per_cpu(cpu_hw_events, i).shared_regs;
3771 if (pc && pc->core_id == core_id) {
3772 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3773 cpuc->shared_regs = pc;
3774 break;
3775 }
3776 }
3777 cpuc->shared_regs->core_id = core_id;
3778 cpuc->shared_regs->refcnt++;
3779 }
3780
3781 if (x86_pmu.lbr_sel_map)
3782 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3783
3784 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3785 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3786 struct cpu_hw_events *sibling;
3787 struct intel_excl_cntrs *c;
3788
3789 sibling = &per_cpu(cpu_hw_events, i);
3790 c = sibling->excl_cntrs;
3791 if (c && c->core_id == core_id) {
3792 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3793 cpuc->excl_cntrs = c;
3794 if (!sibling->excl_thread_id)
3795 cpuc->excl_thread_id = 1;
3796 break;
3797 }
3798 }
3799 cpuc->excl_cntrs->core_id = core_id;
3800 cpuc->excl_cntrs->refcnt++;
3801 }
3802 }
3803
3804 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
3805 {
3806 struct intel_excl_cntrs *c;
3807
3808 c = cpuc->excl_cntrs;
3809 if (c) {
3810 if (c->core_id == -1 || --c->refcnt == 0)
3811 kfree(c);
3812 cpuc->excl_cntrs = NULL;
3813 }
3814
3815 kfree(cpuc->constraint_list);
3816 cpuc->constraint_list = NULL;
3817 }
3818
3819 static void intel_pmu_cpu_dying(int cpu)
3820 {
3821 fini_debug_store_on_cpu(cpu);
3822
3823 if (x86_pmu.counter_freezing)
3824 disable_counter_freeze();
3825 }
3826
3827 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
3828 {
3829 struct intel_shared_regs *pc;
3830
3831 pc = cpuc->shared_regs;
3832 if (pc) {
3833 if (pc->core_id == -1 || --pc->refcnt == 0)
3834 kfree(pc);
3835 cpuc->shared_regs = NULL;
3836 }
3837
3838 free_excl_cntrs(cpuc);
3839 }
3840
3841 static void intel_pmu_cpu_dead(int cpu)
3842 {
3843 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
3844 }
3845
3846 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3847 bool sched_in)
3848 {
3849 intel_pmu_pebs_sched_task(ctx, sched_in);
3850 intel_pmu_lbr_sched_task(ctx, sched_in);
3851 }
3852
3853 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
3854 struct perf_event_context *next)
3855 {
3856 intel_pmu_lbr_swap_task_ctx(prev, next);
3857 }
3858
3859 static int intel_pmu_check_period(struct perf_event *event, u64 value)
3860 {
3861 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
3862 }
3863
3864 static int intel_pmu_aux_output_match(struct perf_event *event)
3865 {
3866 if (!x86_pmu.intel_cap.pebs_output_pt_available)
3867 return 0;
3868
3869 return is_intel_pt_event(event);
3870 }
3871
3872 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3873
3874 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3875
3876 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3877
3878 static struct attribute *intel_arch3_formats_attr[] = {
3879 &format_attr_event.attr,
3880 &format_attr_umask.attr,
3881 &format_attr_edge.attr,
3882 &format_attr_pc.attr,
3883 &format_attr_any.attr,
3884 &format_attr_inv.attr,
3885 &format_attr_cmask.attr,
3886 NULL,
3887 };
3888
3889 static struct attribute *hsw_format_attr[] = {
3890 &format_attr_in_tx.attr,
3891 &format_attr_in_tx_cp.attr,
3892 &format_attr_offcore_rsp.attr,
3893 &format_attr_ldlat.attr,
3894 NULL
3895 };
3896
3897 static struct attribute *nhm_format_attr[] = {
3898 &format_attr_offcore_rsp.attr,
3899 &format_attr_ldlat.attr,
3900 NULL
3901 };
3902
3903 static struct attribute *slm_format_attr[] = {
3904 &format_attr_offcore_rsp.attr,
3905 NULL
3906 };
3907
3908 static struct attribute *skl_format_attr[] = {
3909 &format_attr_frontend.attr,
3910 NULL,
3911 };
3912
3913 static __initconst const struct x86_pmu core_pmu = {
3914 .name = "core",
3915 .handle_irq = x86_pmu_handle_irq,
3916 .disable_all = x86_pmu_disable_all,
3917 .enable_all = core_pmu_enable_all,
3918 .enable = core_pmu_enable_event,
3919 .disable = x86_pmu_disable_event,
3920 .hw_config = core_pmu_hw_config,
3921 .schedule_events = x86_schedule_events,
3922 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3923 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3924 .event_map = intel_pmu_event_map,
3925 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3926 .apic = 1,
3927 .large_pebs_flags = LARGE_PEBS_FLAGS,
3928
3929 /*
3930 * Intel PMCs cannot be accessed sanely above 32-bit width,
3931 * so we install an artificial 1<<31 period regardless of
3932 * the generic event period:
3933 */
3934 .max_period = (1ULL<<31) - 1,
3935 .get_event_constraints = intel_get_event_constraints,
3936 .put_event_constraints = intel_put_event_constraints,
3937 .event_constraints = intel_core_event_constraints,
3938 .guest_get_msrs = core_guest_get_msrs,
3939 .format_attrs = intel_arch_formats_attr,
3940 .events_sysfs_show = intel_event_sysfs_show,
3941
3942 /*
3943 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3944 * together with PMU version 1 and thus be using core_pmu with
3945 * shared_regs. We need following callbacks here to allocate
3946 * it properly.
3947 */
3948 .cpu_prepare = intel_pmu_cpu_prepare,
3949 .cpu_starting = intel_pmu_cpu_starting,
3950 .cpu_dying = intel_pmu_cpu_dying,
3951 .cpu_dead = intel_pmu_cpu_dead,
3952
3953 .check_period = intel_pmu_check_period,
3954 };
3955
3956 static __initconst const struct x86_pmu intel_pmu = {
3957 .name = "Intel",
3958 .handle_irq = intel_pmu_handle_irq,
3959 .disable_all = intel_pmu_disable_all,
3960 .enable_all = intel_pmu_enable_all,
3961 .enable = intel_pmu_enable_event,
3962 .disable = intel_pmu_disable_event,
3963 .add = intel_pmu_add_event,
3964 .del = intel_pmu_del_event,
3965 .read = intel_pmu_read_event,
3966 .hw_config = intel_pmu_hw_config,
3967 .schedule_events = x86_schedule_events,
3968 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3969 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3970 .event_map = intel_pmu_event_map,
3971 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3972 .apic = 1,
3973 .large_pebs_flags = LARGE_PEBS_FLAGS,
3974 /*
3975 * Intel PMCs cannot be accessed sanely above 32 bit width,
3976 * so we install an artificial 1<<31 period regardless of
3977 * the generic event period:
3978 */
3979 .max_period = (1ULL << 31) - 1,
3980 .get_event_constraints = intel_get_event_constraints,
3981 .put_event_constraints = intel_put_event_constraints,
3982 .pebs_aliases = intel_pebs_aliases_core2,
3983
3984 .format_attrs = intel_arch3_formats_attr,
3985 .events_sysfs_show = intel_event_sysfs_show,
3986
3987 .cpu_prepare = intel_pmu_cpu_prepare,
3988 .cpu_starting = intel_pmu_cpu_starting,
3989 .cpu_dying = intel_pmu_cpu_dying,
3990 .cpu_dead = intel_pmu_cpu_dead,
3991
3992 .guest_get_msrs = intel_guest_get_msrs,
3993 .sched_task = intel_pmu_sched_task,
3994 .swap_task_ctx = intel_pmu_swap_task_ctx,
3995
3996 .check_period = intel_pmu_check_period,
3997
3998 .aux_output_match = intel_pmu_aux_output_match,
3999 };
4000
4001 static __init void intel_clovertown_quirk(void)
4002 {
4003 /*
4004 * PEBS is unreliable due to:
4005 *
4006 * AJ67 - PEBS may experience CPL leaks
4007 * AJ68 - PEBS PMI may be delayed by one event
4008 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4009 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4010 *
4011 * AJ67 could be worked around by restricting the OS/USR flags.
4012 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4013 *
4014 * AJ106 could possibly be worked around by not allowing LBR
4015 * usage from PEBS, including the fixup.
4016 * AJ68 could possibly be worked around by always programming
4017 * a pebs_event_reset[0] value and coping with the lost events.
4018 *
4019 * But taken together it might just make sense to not enable PEBS on
4020 * these chips.
4021 */
4022 pr_warn("PEBS disabled due to CPU errata\n");
4023 x86_pmu.pebs = 0;
4024 x86_pmu.pebs_constraints = NULL;
4025 }
4026
4027 static const struct x86_cpu_desc isolation_ucodes[] = {
4028 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4029 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4030 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4031 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4032 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4033 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4034 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4035 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4036 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4037 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4038 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4039 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014),
4040 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4041 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4042 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4043 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4044 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4045 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4046 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4047 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4048 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4049 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4050 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4051 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4052 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4053 {}
4054 };
4055
4056 static void intel_check_pebs_isolation(void)
4057 {
4058 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4059 }
4060
4061 static __init void intel_pebs_isolation_quirk(void)
4062 {
4063 WARN_ON_ONCE(x86_pmu.check_microcode);
4064 x86_pmu.check_microcode = intel_check_pebs_isolation;
4065 intel_check_pebs_isolation();
4066 }
4067
4068 static const struct x86_cpu_desc pebs_ucodes[] = {
4069 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4070 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4071 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4072 {}
4073 };
4074
4075 static bool intel_snb_pebs_broken(void)
4076 {
4077 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4078 }
4079
4080 static void intel_snb_check_microcode(void)
4081 {
4082 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4083 return;
4084
4085 /*
4086 * Serialized by the microcode lock..
4087 */
4088 if (x86_pmu.pebs_broken) {
4089 pr_info("PEBS enabled due to microcode update\n");
4090 x86_pmu.pebs_broken = 0;
4091 } else {
4092 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4093 x86_pmu.pebs_broken = 1;
4094 }
4095 }
4096
4097 static bool is_lbr_from(unsigned long msr)
4098 {
4099 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4100
4101 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4102 }
4103
4104 /*
4105 * Under certain circumstances, access certain MSR may cause #GP.
4106 * The function tests if the input MSR can be safely accessed.
4107 */
4108 static bool check_msr(unsigned long msr, u64 mask)
4109 {
4110 u64 val_old, val_new, val_tmp;
4111
4112 /*
4113 * Disable the check for real HW, so we don't
4114 * mess with potentionaly enabled registers:
4115 */
4116 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4117 return true;
4118
4119 /*
4120 * Read the current value, change it and read it back to see if it
4121 * matches, this is needed to detect certain hardware emulators
4122 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4123 */
4124 if (rdmsrl_safe(msr, &val_old))
4125 return false;
4126
4127 /*
4128 * Only change the bits which can be updated by wrmsrl.
4129 */
4130 val_tmp = val_old ^ mask;
4131
4132 if (is_lbr_from(msr))
4133 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4134
4135 if (wrmsrl_safe(msr, val_tmp) ||
4136 rdmsrl_safe(msr, &val_new))
4137 return false;
4138
4139 /*
4140 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4141 * should equal rdmsrl()'s even with the quirk.
4142 */
4143 if (val_new != val_tmp)
4144 return false;
4145
4146 if (is_lbr_from(msr))
4147 val_old = lbr_from_signext_quirk_wr(val_old);
4148
4149 /* Here it's sure that the MSR can be safely accessed.
4150 * Restore the old value and return.
4151 */
4152 wrmsrl(msr, val_old);
4153
4154 return true;
4155 }
4156
4157 static __init void intel_sandybridge_quirk(void)
4158 {
4159 x86_pmu.check_microcode = intel_snb_check_microcode;
4160 cpus_read_lock();
4161 intel_snb_check_microcode();
4162 cpus_read_unlock();
4163 }
4164
4165 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4166 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4167 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4168 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4169 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4170 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4171 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4172 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4173 };
4174
4175 static __init void intel_arch_events_quirk(void)
4176 {
4177 int bit;
4178
4179 /* disable event that reported as not presend by cpuid */
4180 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4181 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4182 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4183 intel_arch_events_map[bit].name);
4184 }
4185 }
4186
4187 static __init void intel_nehalem_quirk(void)
4188 {
4189 union cpuid10_ebx ebx;
4190
4191 ebx.full = x86_pmu.events_maskl;
4192 if (ebx.split.no_branch_misses_retired) {
4193 /*
4194 * Erratum AAJ80 detected, we work it around by using
4195 * the BR_MISP_EXEC.ANY event. This will over-count
4196 * branch-misses, but it's still much better than the
4197 * architectural event which is often completely bogus:
4198 */
4199 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4200 ebx.split.no_branch_misses_retired = 0;
4201 x86_pmu.events_maskl = ebx.full;
4202 pr_info("CPU erratum AAJ80 worked around\n");
4203 }
4204 }
4205
4206 static const struct x86_cpu_desc counter_freezing_ucodes[] = {
4207 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
4208 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
4209 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
4210 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
4211 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4212 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
4213 {}
4214 };
4215
4216 static bool intel_counter_freezing_broken(void)
4217 {
4218 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes);
4219 }
4220
4221 static __init void intel_counter_freezing_quirk(void)
4222 {
4223 /* Check if it's already disabled */
4224 if (disable_counter_freezing)
4225 return;
4226
4227 /*
4228 * If the system starts with the wrong ucode, leave the
4229 * counter-freezing feature permanently disabled.
4230 */
4231 if (intel_counter_freezing_broken()) {
4232 pr_info("PMU counter freezing disabled due to CPU errata,"
4233 "please upgrade microcode\n");
4234 x86_pmu.counter_freezing = false;
4235 x86_pmu.handle_irq = intel_pmu_handle_irq;
4236 }
4237 }
4238
4239 /*
4240 * enable software workaround for errata:
4241 * SNB: BJ122
4242 * IVB: BV98
4243 * HSW: HSD29
4244 *
4245 * Only needed when HT is enabled. However detecting
4246 * if HT is enabled is difficult (model specific). So instead,
4247 * we enable the workaround in the early boot, and verify if
4248 * it is needed in a later initcall phase once we have valid
4249 * topology information to check if HT is actually enabled
4250 */
4251 static __init void intel_ht_bug(void)
4252 {
4253 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4254
4255 x86_pmu.start_scheduling = intel_start_scheduling;
4256 x86_pmu.commit_scheduling = intel_commit_scheduling;
4257 x86_pmu.stop_scheduling = intel_stop_scheduling;
4258 }
4259
4260 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4261 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4262
4263 /* Haswell special events */
4264 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4265 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4266 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4267 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4268 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4269 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4270 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4271 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4272 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4273 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4274 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4275 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4276
4277 static struct attribute *hsw_events_attrs[] = {
4278 EVENT_PTR(td_slots_issued),
4279 EVENT_PTR(td_slots_retired),
4280 EVENT_PTR(td_fetch_bubbles),
4281 EVENT_PTR(td_total_slots),
4282 EVENT_PTR(td_total_slots_scale),
4283 EVENT_PTR(td_recovery_bubbles),
4284 EVENT_PTR(td_recovery_bubbles_scale),
4285 NULL
4286 };
4287
4288 static struct attribute *hsw_mem_events_attrs[] = {
4289 EVENT_PTR(mem_ld_hsw),
4290 EVENT_PTR(mem_st_hsw),
4291 NULL,
4292 };
4293
4294 static struct attribute *hsw_tsx_events_attrs[] = {
4295 EVENT_PTR(tx_start),
4296 EVENT_PTR(tx_commit),
4297 EVENT_PTR(tx_abort),
4298 EVENT_PTR(tx_capacity),
4299 EVENT_PTR(tx_conflict),
4300 EVENT_PTR(el_start),
4301 EVENT_PTR(el_commit),
4302 EVENT_PTR(el_abort),
4303 EVENT_PTR(el_capacity),
4304 EVENT_PTR(el_conflict),
4305 EVENT_PTR(cycles_t),
4306 EVENT_PTR(cycles_ct),
4307 NULL
4308 };
4309
4310 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4311 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4312 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4313 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4314
4315 static struct attribute *icl_events_attrs[] = {
4316 EVENT_PTR(mem_ld_hsw),
4317 EVENT_PTR(mem_st_hsw),
4318 NULL,
4319 };
4320
4321 static struct attribute *icl_tsx_events_attrs[] = {
4322 EVENT_PTR(tx_start),
4323 EVENT_PTR(tx_abort),
4324 EVENT_PTR(tx_commit),
4325 EVENT_PTR(tx_capacity_read),
4326 EVENT_PTR(tx_capacity_write),
4327 EVENT_PTR(tx_conflict),
4328 EVENT_PTR(el_start),
4329 EVENT_PTR(el_abort),
4330 EVENT_PTR(el_commit),
4331 EVENT_PTR(el_capacity_read),
4332 EVENT_PTR(el_capacity_write),
4333 EVENT_PTR(el_conflict),
4334 EVENT_PTR(cycles_t),
4335 EVENT_PTR(cycles_ct),
4336 NULL,
4337 };
4338
4339 static ssize_t freeze_on_smi_show(struct device *cdev,
4340 struct device_attribute *attr,
4341 char *buf)
4342 {
4343 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4344 }
4345
4346 static DEFINE_MUTEX(freeze_on_smi_mutex);
4347
4348 static ssize_t freeze_on_smi_store(struct device *cdev,
4349 struct device_attribute *attr,
4350 const char *buf, size_t count)
4351 {
4352 unsigned long val;
4353 ssize_t ret;
4354
4355 ret = kstrtoul(buf, 0, &val);
4356 if (ret)
4357 return ret;
4358
4359 if (val > 1)
4360 return -EINVAL;
4361
4362 mutex_lock(&freeze_on_smi_mutex);
4363
4364 if (x86_pmu.attr_freeze_on_smi == val)
4365 goto done;
4366
4367 x86_pmu.attr_freeze_on_smi = val;
4368
4369 get_online_cpus();
4370 on_each_cpu(flip_smm_bit, &val, 1);
4371 put_online_cpus();
4372 done:
4373 mutex_unlock(&freeze_on_smi_mutex);
4374
4375 return count;
4376 }
4377
4378 static void update_tfa_sched(void *ignored)
4379 {
4380 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4381
4382 /*
4383 * check if PMC3 is used
4384 * and if so force schedule out for all event types all contexts
4385 */
4386 if (test_bit(3, cpuc->active_mask))
4387 perf_pmu_resched(x86_get_pmu());
4388 }
4389
4390 static ssize_t show_sysctl_tfa(struct device *cdev,
4391 struct device_attribute *attr,
4392 char *buf)
4393 {
4394 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4395 }
4396
4397 static ssize_t set_sysctl_tfa(struct device *cdev,
4398 struct device_attribute *attr,
4399 const char *buf, size_t count)
4400 {
4401 bool val;
4402 ssize_t ret;
4403
4404 ret = kstrtobool(buf, &val);
4405 if (ret)
4406 return ret;
4407
4408 /* no change */
4409 if (val == allow_tsx_force_abort)
4410 return count;
4411
4412 allow_tsx_force_abort = val;
4413
4414 get_online_cpus();
4415 on_each_cpu(update_tfa_sched, NULL, 1);
4416 put_online_cpus();
4417
4418 return count;
4419 }
4420
4421
4422 static DEVICE_ATTR_RW(freeze_on_smi);
4423
4424 static ssize_t branches_show(struct device *cdev,
4425 struct device_attribute *attr,
4426 char *buf)
4427 {
4428 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4429 }
4430
4431 static DEVICE_ATTR_RO(branches);
4432
4433 static struct attribute *lbr_attrs[] = {
4434 &dev_attr_branches.attr,
4435 NULL
4436 };
4437
4438 static char pmu_name_str[30];
4439
4440 static ssize_t pmu_name_show(struct device *cdev,
4441 struct device_attribute *attr,
4442 char *buf)
4443 {
4444 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4445 }
4446
4447 static DEVICE_ATTR_RO(pmu_name);
4448
4449 static struct attribute *intel_pmu_caps_attrs[] = {
4450 &dev_attr_pmu_name.attr,
4451 NULL
4452 };
4453
4454 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4455 show_sysctl_tfa,
4456 set_sysctl_tfa);
4457
4458 static struct attribute *intel_pmu_attrs[] = {
4459 &dev_attr_freeze_on_smi.attr,
4460 &dev_attr_allow_tsx_force_abort.attr,
4461 NULL,
4462 };
4463
4464 static umode_t
4465 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4466 {
4467 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4468 }
4469
4470 static umode_t
4471 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4472 {
4473 return x86_pmu.pebs ? attr->mode : 0;
4474 }
4475
4476 static umode_t
4477 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4478 {
4479 return x86_pmu.lbr_nr ? attr->mode : 0;
4480 }
4481
4482 static umode_t
4483 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4484 {
4485 return x86_pmu.version >= 2 ? attr->mode : 0;
4486 }
4487
4488 static umode_t
4489 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4490 {
4491 if (attr == &dev_attr_allow_tsx_force_abort.attr)
4492 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
4493
4494 return attr->mode;
4495 }
4496
4497 static struct attribute_group group_events_td = {
4498 .name = "events",
4499 };
4500
4501 static struct attribute_group group_events_mem = {
4502 .name = "events",
4503 .is_visible = pebs_is_visible,
4504 };
4505
4506 static struct attribute_group group_events_tsx = {
4507 .name = "events",
4508 .is_visible = tsx_is_visible,
4509 };
4510
4511 static struct attribute_group group_caps_gen = {
4512 .name = "caps",
4513 .attrs = intel_pmu_caps_attrs,
4514 };
4515
4516 static struct attribute_group group_caps_lbr = {
4517 .name = "caps",
4518 .attrs = lbr_attrs,
4519 .is_visible = lbr_is_visible,
4520 };
4521
4522 static struct attribute_group group_format_extra = {
4523 .name = "format",
4524 .is_visible = exra_is_visible,
4525 };
4526
4527 static struct attribute_group group_format_extra_skl = {
4528 .name = "format",
4529 .is_visible = exra_is_visible,
4530 };
4531
4532 static struct attribute_group group_default = {
4533 .attrs = intel_pmu_attrs,
4534 .is_visible = default_is_visible,
4535 };
4536
4537 static const struct attribute_group *attr_update[] = {
4538 &group_events_td,
4539 &group_events_mem,
4540 &group_events_tsx,
4541 &group_caps_gen,
4542 &group_caps_lbr,
4543 &group_format_extra,
4544 &group_format_extra_skl,
4545 &group_default,
4546 NULL,
4547 };
4548
4549 static struct attribute *empty_attrs;
4550
4551 __init int intel_pmu_init(void)
4552 {
4553 struct attribute **extra_skl_attr = &empty_attrs;
4554 struct attribute **extra_attr = &empty_attrs;
4555 struct attribute **td_attr = &empty_attrs;
4556 struct attribute **mem_attr = &empty_attrs;
4557 struct attribute **tsx_attr = &empty_attrs;
4558 union cpuid10_edx edx;
4559 union cpuid10_eax eax;
4560 union cpuid10_ebx ebx;
4561 struct event_constraint *c;
4562 unsigned int unused;
4563 struct extra_reg *er;
4564 bool pmem = false;
4565 int version, i;
4566 char *name;
4567
4568 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4569 switch (boot_cpu_data.x86) {
4570 case 0x6:
4571 return p6_pmu_init();
4572 case 0xb:
4573 return knc_pmu_init();
4574 case 0xf:
4575 return p4_pmu_init();
4576 }
4577 return -ENODEV;
4578 }
4579
4580 /*
4581 * Check whether the Architectural PerfMon supports
4582 * Branch Misses Retired hw_event or not.
4583 */
4584 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4585 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4586 return -ENODEV;
4587
4588 version = eax.split.version_id;
4589 if (version < 2)
4590 x86_pmu = core_pmu;
4591 else
4592 x86_pmu = intel_pmu;
4593
4594 x86_pmu.version = version;
4595 x86_pmu.num_counters = eax.split.num_counters;
4596 x86_pmu.cntval_bits = eax.split.bit_width;
4597 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4598
4599 x86_pmu.events_maskl = ebx.full;
4600 x86_pmu.events_mask_len = eax.split.mask_length;
4601
4602 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4603
4604 /*
4605 * Quirk: v2 perfmon does not report fixed-purpose events, so
4606 * assume at least 3 events, when not running in a hypervisor:
4607 */
4608 if (version > 1) {
4609 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4610
4611 x86_pmu.num_counters_fixed =
4612 max((int)edx.split.num_counters_fixed, assume);
4613 }
4614
4615 if (version >= 4)
4616 x86_pmu.counter_freezing = !disable_counter_freezing;
4617
4618 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4619 u64 capabilities;
4620
4621 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4622 x86_pmu.intel_cap.capabilities = capabilities;
4623 }
4624
4625 intel_ds_init();
4626
4627 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4628
4629 /*
4630 * Install the hw-cache-events table:
4631 */
4632 switch (boot_cpu_data.x86_model) {
4633 case INTEL_FAM6_CORE_YONAH:
4634 pr_cont("Core events, ");
4635 name = "core";
4636 break;
4637
4638 case INTEL_FAM6_CORE2_MEROM:
4639 x86_add_quirk(intel_clovertown_quirk);
4640 /* fall through */
4641
4642 case INTEL_FAM6_CORE2_MEROM_L:
4643 case INTEL_FAM6_CORE2_PENRYN:
4644 case INTEL_FAM6_CORE2_DUNNINGTON:
4645 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
4646 sizeof(hw_cache_event_ids));
4647
4648 intel_pmu_lbr_init_core();
4649
4650 x86_pmu.event_constraints = intel_core2_event_constraints;
4651 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
4652 pr_cont("Core2 events, ");
4653 name = "core2";
4654 break;
4655
4656 case INTEL_FAM6_NEHALEM:
4657 case INTEL_FAM6_NEHALEM_EP:
4658 case INTEL_FAM6_NEHALEM_EX:
4659 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
4660 sizeof(hw_cache_event_ids));
4661 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4662 sizeof(hw_cache_extra_regs));
4663
4664 intel_pmu_lbr_init_nhm();
4665
4666 x86_pmu.event_constraints = intel_nehalem_event_constraints;
4667 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
4668 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4669 x86_pmu.extra_regs = intel_nehalem_extra_regs;
4670 x86_pmu.limit_period = nhm_limit_period;
4671
4672 mem_attr = nhm_mem_events_attrs;
4673
4674 /* UOPS_ISSUED.STALLED_CYCLES */
4675 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4676 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4677 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4678 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4679 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4680
4681 intel_pmu_pebs_data_source_nhm();
4682 x86_add_quirk(intel_nehalem_quirk);
4683 x86_pmu.pebs_no_tlb = 1;
4684 extra_attr = nhm_format_attr;
4685
4686 pr_cont("Nehalem events, ");
4687 name = "nehalem";
4688 break;
4689
4690 case INTEL_FAM6_ATOM_BONNELL:
4691 case INTEL_FAM6_ATOM_BONNELL_MID:
4692 case INTEL_FAM6_ATOM_SALTWELL:
4693 case INTEL_FAM6_ATOM_SALTWELL_MID:
4694 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
4695 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4696 sizeof(hw_cache_event_ids));
4697
4698 intel_pmu_lbr_init_atom();
4699
4700 x86_pmu.event_constraints = intel_gen_event_constraints;
4701 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
4702 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
4703 pr_cont("Atom events, ");
4704 name = "bonnell";
4705 break;
4706
4707 case INTEL_FAM6_ATOM_SILVERMONT:
4708 case INTEL_FAM6_ATOM_SILVERMONT_D:
4709 case INTEL_FAM6_ATOM_SILVERMONT_MID:
4710 case INTEL_FAM6_ATOM_AIRMONT:
4711 case INTEL_FAM6_ATOM_AIRMONT_MID:
4712 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4713 sizeof(hw_cache_event_ids));
4714 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4715 sizeof(hw_cache_extra_regs));
4716
4717 intel_pmu_lbr_init_slm();
4718
4719 x86_pmu.event_constraints = intel_slm_event_constraints;
4720 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4721 x86_pmu.extra_regs = intel_slm_extra_regs;
4722 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4723 td_attr = slm_events_attrs;
4724 extra_attr = slm_format_attr;
4725 pr_cont("Silvermont events, ");
4726 name = "silvermont";
4727 break;
4728
4729 case INTEL_FAM6_ATOM_GOLDMONT:
4730 case INTEL_FAM6_ATOM_GOLDMONT_D:
4731 x86_add_quirk(intel_counter_freezing_quirk);
4732 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4733 sizeof(hw_cache_event_ids));
4734 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4735 sizeof(hw_cache_extra_regs));
4736
4737 intel_pmu_lbr_init_skl();
4738
4739 x86_pmu.event_constraints = intel_slm_event_constraints;
4740 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4741 x86_pmu.extra_regs = intel_glm_extra_regs;
4742 /*
4743 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4744 * for precise cycles.
4745 * :pp is identical to :ppp
4746 */
4747 x86_pmu.pebs_aliases = NULL;
4748 x86_pmu.pebs_prec_dist = true;
4749 x86_pmu.lbr_pt_coexist = true;
4750 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4751 td_attr = glm_events_attrs;
4752 extra_attr = slm_format_attr;
4753 pr_cont("Goldmont events, ");
4754 name = "goldmont";
4755 break;
4756
4757 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4758 x86_add_quirk(intel_counter_freezing_quirk);
4759 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4760 sizeof(hw_cache_event_ids));
4761 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4762 sizeof(hw_cache_extra_regs));
4763
4764 intel_pmu_lbr_init_skl();
4765
4766 x86_pmu.event_constraints = intel_slm_event_constraints;
4767 x86_pmu.extra_regs = intel_glm_extra_regs;
4768 /*
4769 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4770 * for precise cycles.
4771 */
4772 x86_pmu.pebs_aliases = NULL;
4773 x86_pmu.pebs_prec_dist = true;
4774 x86_pmu.lbr_pt_coexist = true;
4775 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4776 x86_pmu.flags |= PMU_FL_PEBS_ALL;
4777 x86_pmu.get_event_constraints = glp_get_event_constraints;
4778 td_attr = glm_events_attrs;
4779 /* Goldmont Plus has 4-wide pipeline */
4780 event_attr_td_total_slots_scale_glm.event_str = "4";
4781 extra_attr = slm_format_attr;
4782 pr_cont("Goldmont plus events, ");
4783 name = "goldmont_plus";
4784 break;
4785
4786 case INTEL_FAM6_ATOM_TREMONT_D:
4787 case INTEL_FAM6_ATOM_TREMONT:
4788 x86_pmu.late_ack = true;
4789 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4790 sizeof(hw_cache_event_ids));
4791 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
4792 sizeof(hw_cache_extra_regs));
4793 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
4794
4795 intel_pmu_lbr_init_skl();
4796
4797 x86_pmu.event_constraints = intel_slm_event_constraints;
4798 x86_pmu.extra_regs = intel_tnt_extra_regs;
4799 /*
4800 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4801 * for precise cycles.
4802 */
4803 x86_pmu.pebs_aliases = NULL;
4804 x86_pmu.pebs_prec_dist = true;
4805 x86_pmu.lbr_pt_coexist = true;
4806 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4807 x86_pmu.get_event_constraints = tnt_get_event_constraints;
4808 extra_attr = slm_format_attr;
4809 pr_cont("Tremont events, ");
4810 name = "Tremont";
4811 break;
4812
4813 case INTEL_FAM6_WESTMERE:
4814 case INTEL_FAM6_WESTMERE_EP:
4815 case INTEL_FAM6_WESTMERE_EX:
4816 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4817 sizeof(hw_cache_event_ids));
4818 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4819 sizeof(hw_cache_extra_regs));
4820
4821 intel_pmu_lbr_init_nhm();
4822
4823 x86_pmu.event_constraints = intel_westmere_event_constraints;
4824 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4825 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
4826 x86_pmu.extra_regs = intel_westmere_extra_regs;
4827 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4828
4829 mem_attr = nhm_mem_events_attrs;
4830
4831 /* UOPS_ISSUED.STALLED_CYCLES */
4832 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4833 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4834 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4835 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4836 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4837
4838 intel_pmu_pebs_data_source_nhm();
4839 extra_attr = nhm_format_attr;
4840 pr_cont("Westmere events, ");
4841 name = "westmere";
4842 break;
4843
4844 case INTEL_FAM6_SANDYBRIDGE:
4845 case INTEL_FAM6_SANDYBRIDGE_X:
4846 x86_add_quirk(intel_sandybridge_quirk);
4847 x86_add_quirk(intel_ht_bug);
4848 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4849 sizeof(hw_cache_event_ids));
4850 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4851 sizeof(hw_cache_extra_regs));
4852
4853 intel_pmu_lbr_init_snb();
4854
4855 x86_pmu.event_constraints = intel_snb_event_constraints;
4856 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
4857 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
4858 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
4859 x86_pmu.extra_regs = intel_snbep_extra_regs;
4860 else
4861 x86_pmu.extra_regs = intel_snb_extra_regs;
4862
4863
4864 /* all extra regs are per-cpu when HT is on */
4865 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4866 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4867
4868 td_attr = snb_events_attrs;
4869 mem_attr = snb_mem_events_attrs;
4870
4871 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4872 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4873 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4874 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
4875 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4876 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
4877
4878 extra_attr = nhm_format_attr;
4879
4880 pr_cont("SandyBridge events, ");
4881 name = "sandybridge";
4882 break;
4883
4884 case INTEL_FAM6_IVYBRIDGE:
4885 case INTEL_FAM6_IVYBRIDGE_X:
4886 x86_add_quirk(intel_ht_bug);
4887 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4888 sizeof(hw_cache_event_ids));
4889 /* dTLB-load-misses on IVB is different than SNB */
4890 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4891
4892 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4893 sizeof(hw_cache_extra_regs));
4894
4895 intel_pmu_lbr_init_snb();
4896
4897 x86_pmu.event_constraints = intel_ivb_event_constraints;
4898 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
4899 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4900 x86_pmu.pebs_prec_dist = true;
4901 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
4902 x86_pmu.extra_regs = intel_snbep_extra_regs;
4903 else
4904 x86_pmu.extra_regs = intel_snb_extra_regs;
4905 /* all extra regs are per-cpu when HT is on */
4906 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4907 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4908
4909 td_attr = snb_events_attrs;
4910 mem_attr = snb_mem_events_attrs;
4911
4912 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4913 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4914 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4915
4916 extra_attr = nhm_format_attr;
4917
4918 pr_cont("IvyBridge events, ");
4919 name = "ivybridge";
4920 break;
4921
4922
4923 case INTEL_FAM6_HASWELL:
4924 case INTEL_FAM6_HASWELL_X:
4925 case INTEL_FAM6_HASWELL_L:
4926 case INTEL_FAM6_HASWELL_G:
4927 x86_add_quirk(intel_ht_bug);
4928 x86_add_quirk(intel_pebs_isolation_quirk);
4929 x86_pmu.late_ack = true;
4930 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4931 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4932
4933 intel_pmu_lbr_init_hsw();
4934
4935 x86_pmu.event_constraints = intel_hsw_event_constraints;
4936 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
4937 x86_pmu.extra_regs = intel_snbep_extra_regs;
4938 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4939 x86_pmu.pebs_prec_dist = true;
4940 /* all extra regs are per-cpu when HT is on */
4941 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4942 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4943
4944 x86_pmu.hw_config = hsw_hw_config;
4945 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4946 x86_pmu.lbr_double_abort = true;
4947 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4948 hsw_format_attr : nhm_format_attr;
4949 td_attr = hsw_events_attrs;
4950 mem_attr = hsw_mem_events_attrs;
4951 tsx_attr = hsw_tsx_events_attrs;
4952 pr_cont("Haswell events, ");
4953 name = "haswell";
4954 break;
4955
4956 case INTEL_FAM6_BROADWELL:
4957 case INTEL_FAM6_BROADWELL_D:
4958 case INTEL_FAM6_BROADWELL_G:
4959 case INTEL_FAM6_BROADWELL_X:
4960 x86_add_quirk(intel_pebs_isolation_quirk);
4961 x86_pmu.late_ack = true;
4962 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4963 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4964
4965 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4966 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4967 BDW_L3_MISS|HSW_SNOOP_DRAM;
4968 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4969 HSW_SNOOP_DRAM;
4970 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4971 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4972 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4973 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4974
4975 intel_pmu_lbr_init_hsw();
4976
4977 x86_pmu.event_constraints = intel_bdw_event_constraints;
4978 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
4979 x86_pmu.extra_regs = intel_snbep_extra_regs;
4980 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4981 x86_pmu.pebs_prec_dist = true;
4982 /* all extra regs are per-cpu when HT is on */
4983 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4984 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4985
4986 x86_pmu.hw_config = hsw_hw_config;
4987 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4988 x86_pmu.limit_period = bdw_limit_period;
4989 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4990 hsw_format_attr : nhm_format_attr;
4991 td_attr = hsw_events_attrs;
4992 mem_attr = hsw_mem_events_attrs;
4993 tsx_attr = hsw_tsx_events_attrs;
4994 pr_cont("Broadwell events, ");
4995 name = "broadwell";
4996 break;
4997
4998 case INTEL_FAM6_XEON_PHI_KNL:
4999 case INTEL_FAM6_XEON_PHI_KNM:
5000 memcpy(hw_cache_event_ids,
5001 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5002 memcpy(hw_cache_extra_regs,
5003 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5004 intel_pmu_lbr_init_knl();
5005
5006 x86_pmu.event_constraints = intel_slm_event_constraints;
5007 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5008 x86_pmu.extra_regs = intel_knl_extra_regs;
5009
5010 /* all extra regs are per-cpu when HT is on */
5011 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5012 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5013 extra_attr = slm_format_attr;
5014 pr_cont("Knights Landing/Mill events, ");
5015 name = "knights-landing";
5016 break;
5017
5018 case INTEL_FAM6_SKYLAKE_X:
5019 pmem = true;
5020 /* fall through */
5021 case INTEL_FAM6_SKYLAKE_L:
5022 case INTEL_FAM6_SKYLAKE:
5023 case INTEL_FAM6_KABYLAKE_L:
5024 case INTEL_FAM6_KABYLAKE:
5025 case INTEL_FAM6_COMETLAKE_L:
5026 case INTEL_FAM6_COMETLAKE:
5027 x86_add_quirk(intel_pebs_isolation_quirk);
5028 x86_pmu.late_ack = true;
5029 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5030 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5031 intel_pmu_lbr_init_skl();
5032
5033 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5034 event_attr_td_recovery_bubbles.event_str_noht =
5035 "event=0xd,umask=0x1,cmask=1";
5036 event_attr_td_recovery_bubbles.event_str_ht =
5037 "event=0xd,umask=0x1,cmask=1,any=1";
5038
5039 x86_pmu.event_constraints = intel_skl_event_constraints;
5040 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5041 x86_pmu.extra_regs = intel_skl_extra_regs;
5042 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5043 x86_pmu.pebs_prec_dist = true;
5044 /* all extra regs are per-cpu when HT is on */
5045 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5046 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5047
5048 x86_pmu.hw_config = hsw_hw_config;
5049 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5050 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5051 hsw_format_attr : nhm_format_attr;
5052 extra_skl_attr = skl_format_attr;
5053 td_attr = hsw_events_attrs;
5054 mem_attr = hsw_mem_events_attrs;
5055 tsx_attr = hsw_tsx_events_attrs;
5056 intel_pmu_pebs_data_source_skl(pmem);
5057
5058 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5059 x86_pmu.flags |= PMU_FL_TFA;
5060 x86_pmu.get_event_constraints = tfa_get_event_constraints;
5061 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5062 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5063 }
5064
5065 pr_cont("Skylake events, ");
5066 name = "skylake";
5067 break;
5068
5069 case INTEL_FAM6_ICELAKE_X:
5070 case INTEL_FAM6_ICELAKE_D:
5071 pmem = true;
5072 /* fall through */
5073 case INTEL_FAM6_ICELAKE_L:
5074 case INTEL_FAM6_ICELAKE:
5075 case INTEL_FAM6_TIGERLAKE_L:
5076 case INTEL_FAM6_TIGERLAKE:
5077 x86_pmu.late_ack = true;
5078 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5079 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5080 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5081 intel_pmu_lbr_init_skl();
5082
5083 x86_pmu.event_constraints = intel_icl_event_constraints;
5084 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5085 x86_pmu.extra_regs = intel_icl_extra_regs;
5086 x86_pmu.pebs_aliases = NULL;
5087 x86_pmu.pebs_prec_dist = true;
5088 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5089 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5090
5091 x86_pmu.hw_config = hsw_hw_config;
5092 x86_pmu.get_event_constraints = icl_get_event_constraints;
5093 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5094 hsw_format_attr : nhm_format_attr;
5095 extra_skl_attr = skl_format_attr;
5096 mem_attr = icl_events_attrs;
5097 tsx_attr = icl_tsx_events_attrs;
5098 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
5099 x86_pmu.lbr_pt_coexist = true;
5100 intel_pmu_pebs_data_source_skl(pmem);
5101 pr_cont("Icelake events, ");
5102 name = "icelake";
5103 break;
5104
5105 default:
5106 switch (x86_pmu.version) {
5107 case 1:
5108 x86_pmu.event_constraints = intel_v1_event_constraints;
5109 pr_cont("generic architected perfmon v1, ");
5110 name = "generic_arch_v1";
5111 break;
5112 default:
5113 /*
5114 * default constraints for v2 and up
5115 */
5116 x86_pmu.event_constraints = intel_gen_event_constraints;
5117 pr_cont("generic architected perfmon, ");
5118 name = "generic_arch_v2+";
5119 break;
5120 }
5121 }
5122
5123 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5124
5125
5126 group_events_td.attrs = td_attr;
5127 group_events_mem.attrs = mem_attr;
5128 group_events_tsx.attrs = tsx_attr;
5129 group_format_extra.attrs = extra_attr;
5130 group_format_extra_skl.attrs = extra_skl_attr;
5131
5132 x86_pmu.attr_update = attr_update;
5133
5134 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5135 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5136 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5137 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5138 }
5139 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5140
5141 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5142 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5143 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5144 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5145 }
5146
5147 x86_pmu.intel_ctrl |=
5148 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
5149
5150 if (x86_pmu.event_constraints) {
5151 /*
5152 * event on fixed counter2 (REF_CYCLES) only works on this
5153 * counter, so do not extend mask to generic counters
5154 */
5155 for_each_event_constraint(c, x86_pmu.event_constraints) {
5156 if (c->cmask == FIXED_EVENT_FLAGS
5157 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
5158 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5159 }
5160 c->idxmsk64 &=
5161 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5162 c->weight = hweight64(c->idxmsk64);
5163 }
5164 }
5165
5166 /*
5167 * Access LBR MSR may cause #GP under certain circumstances.
5168 * E.g. KVM doesn't support LBR MSR
5169 * Check all LBT MSR here.
5170 * Disable LBR access if any LBR MSRs can not be accessed.
5171 */
5172 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5173 x86_pmu.lbr_nr = 0;
5174 for (i = 0; i < x86_pmu.lbr_nr; i++) {
5175 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5176 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5177 x86_pmu.lbr_nr = 0;
5178 }
5179
5180 if (x86_pmu.lbr_nr)
5181 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5182
5183 /*
5184 * Access extra MSR may cause #GP under certain circumstances.
5185 * E.g. KVM doesn't support offcore event
5186 * Check all extra_regs here.
5187 */
5188 if (x86_pmu.extra_regs) {
5189 for (er = x86_pmu.extra_regs; er->msr; er++) {
5190 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5191 /* Disable LBR select mapping */
5192 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5193 x86_pmu.lbr_sel_map = NULL;
5194 }
5195 }
5196
5197 /* Support full width counters using alternative MSR range */
5198 if (x86_pmu.intel_cap.full_width_write) {
5199 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5200 x86_pmu.perfctr = MSR_IA32_PMC0;
5201 pr_cont("full-width counters, ");
5202 }
5203
5204 /*
5205 * For arch perfmon 4 use counter freezing to avoid
5206 * several MSR accesses in the PMI.
5207 */
5208 if (x86_pmu.counter_freezing)
5209 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
5210
5211 return 0;
5212 }
5213
5214 /*
5215 * HT bug: phase 2 init
5216 * Called once we have valid topology information to check
5217 * whether or not HT is enabled
5218 * If HT is off, then we disable the workaround
5219 */
5220 static __init int fixup_ht_bug(void)
5221 {
5222 int c;
5223 /*
5224 * problem not present on this CPU model, nothing to do
5225 */
5226 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5227 return 0;
5228
5229 if (topology_max_smt_threads() > 1) {
5230 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5231 return 0;
5232 }
5233
5234 cpus_read_lock();
5235
5236 hardlockup_detector_perf_stop();
5237
5238 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5239
5240 x86_pmu.start_scheduling = NULL;
5241 x86_pmu.commit_scheduling = NULL;
5242 x86_pmu.stop_scheduling = NULL;
5243
5244 hardlockup_detector_perf_restart();
5245
5246 for_each_online_cpu(c)
5247 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5248
5249 cpus_read_unlock();
5250 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5251 return 0;
5252 }
5253 subsys_initcall(fixup_ht_bug)
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