arch/x86/include/asm/arch-quark/quark.h

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _QUARK_H_
   8 #define _QUARK_H_
   9
  10 /* Message Bus Ports */
  11 #define MSG_PORT_MEM_ARBITER    0x00
  12 #define MSG_PORT_HOST_BRIDGE    0x03
  13 #define MSG_PORT_RMU            0x04
  14 #define MSG_PORT_MEM_MGR        0x05
  15 #define MSG_PORT_PCIE_AFE       0x16
  16 #define MSG_PORT_SOC_UNIT       0x31
  17
  18 /* Port 0x00: Memory Arbiter Message Port Registers */
  19
  20 /* Enhanced Configuration Space */
  21 #define AEC_CTRL                0x00
  22
  23 /* Port 0x03: Host Bridge Message Port Registers */
  24
  25 /* Host Miscellaneous Controls 2 */
  26 #define HMISC2                  0x03
  27
  28 #define HMISC2_SEGE             0x00000002
  29 #define HMISC2_SEGF             0x00000004
  30 #define HMISC2_SEGAB            0x00000010
  31
  32 /* Host Memory I/O Boundary */
  33 #define HM_BOUND                0x08
  34
  35 /* Extended Configuration Space */
  36 #define HEC_REG                 0x09
  37
  38 /* Port 0x04: Remote Management Unit Message Port Registers */
  39
  40 /* ACPI PBLK Base Address Register */
  41 #define PBLK_BA                 0x70
  42
  43 /* SPI DMA Base Address Register */
  44 #define SPI_DMA_BA              0x7a
  45
  46 /* Port 0x05: Memory Manager Message Port Registers */
  47
  48 /* eSRAM Block Page Control */
  49 #define ESRAM_BLK_CTRL          0x82
  50 #define ESRAM_BLOCK_MODE        0x10000000
  51
  52 /* Port 0x16: PCIe AFE Unit Port Registers */
  53
  54 #define PCIE_RXPICTRL0_L0       0x2080
  55 #define PCIE_RXPICTRL0_L1       0x2180
  56
  57 /* Port 0x31: SoC Unit Port Registers */
  58
  59 /* PCIe Controller Config */
  60 #define PCIE_CFG                0x36
  61 #define PCIE_CTLR_PRI_RST       0x00010000
  62 #define PCIE_PHY_SB_RST         0x00020000
  63 #define PCIE_CTLR_SB_RST        0x00040000
  64 #define PCIE_PHY_LANE_RST       0x00090000
  65 #define PCIE_CTLR_MAIN_RST      0x00100000
  66
  67 /* DRAM */
  68 #define DRAM_BASE               0x00000000
  69 #define DRAM_MAX_SIZE           0x80000000
  70
  71 /* eSRAM */
  72 #define ESRAM_SIZE              0x80000
  73
  74 /* Memory BAR Enable */
  75 #define MEM_BAR_EN              0x00000001
  76
  77 /* I/O BAR Enable */
  78 #define IO_BAR_EN               0x80000000
  79
  80 /* 64KiB of RMU binary in flash */
  81 #define RMU_BINARY_SIZE         0x10000
  82
  83 /* Legacy Bridge PCI Configuration Registers */
  84 #define LB_GBA                  0x44
  85 #define LB_PM1BLK               0x48
  86 #define LB_GPE0BLK              0x4c
  87 #define LB_ACTL                 0x58
  88 #define LB_PABCDRC              0x60
  89 #define LB_PEFGHRC              0x64
  90 #define LB_WDTBA                0x84
  91 #define LB_BCE                  0xd4
  92 #define LB_BC                   0xd8
  93 #define LB_RCBA                 0xf0
  94
  95 #ifndef __ASSEMBLY__
  96
  97 /* Root Complex Register Block */
  98 struct quark_rcba {
  99         u32     rctl;
 100         u32     esd;
 101         u32     rsvd1[3150];
 102         u16     rmu_ir;
 103         u16     d23_ir;
 104         u16     core_ir;
 105         u16     d20d21_ir;
 106 };
 107
 108 #include <asm/io.h>
 109 #include <asm/pci.h>
 110
 111 /**
 112  * qrk_pci_read_config_dword() - Read a configuration value
 113  *
 114  * @dev:        PCI device address: bus, device and function
 115  * @offset:     Dword offset within the device's configuration space
 116  * @valuep:     Place to put the returned value
 117  *
 118  * Note: This routine is inlined to provide better performance on Quark
 119  */
 120 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
 121                                              u32 *valuep)
 122 {
 123         outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
 124         *valuep = inl(PCI_REG_DATA);
 125 }
 126
 127 /**
 128  * qrk_pci_write_config_dword() - Write a PCI configuration value
 129  *
 130  * @dev:        PCI device address: bus, device and function
 131  * @offset:     Dword offset within the device's configuration space
 132  * @value:      Value to write
 133  *
 134  * Note: This routine is inlined to provide better performance on Quark
 135  */
 136 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
 137                                               u32 value)
 138 {
 139         outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
 140         outl(value, PCI_REG_DATA);
 141 }
 142
 143 /**
 144  * board_assert_perst() - Assert the PERST# pin
 145  *
 146  * The CPU interface to the PERST# signal on Quark is platform dependent.
 147  * Board-specific codes need supply this routine to assert PCIe slot reset.
 148  *
 149  * The tricky part in this routine is that any APIs that may trigger PCI
 150  * enumeration process are strictly forbidden, as any access to PCIe root
 151  * port's configuration registers will cause system hang while it is held
 152  * in reset.
 153  */
 154 void board_assert_perst(void);
 155
 156 /**
 157  * board_deassert_perst() - De-assert the PERST# pin
 158  *
 159  * The CPU interface to the PERST# signal on Quark is platform dependent.
 160  * Board-specific codes need supply this routine to de-assert PCIe slot reset.
 161  *
 162  * The tricky part in this routine is that any APIs that may trigger PCI
 163  * enumeration process are strictly forbidden, as any access to PCIe root
 164  * port's configuration registers will cause system hang while it is held
 165  * in reset.
 166  */
 167 void board_deassert_perst(void);
 168
 169 #endif /* __ASSEMBLY__ */
 170
 171 #endif /* _QUARK_H_ */