1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
5 #include <asm/processor-flags.h>
7 /* Forward declaration, a strange C thing */
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
49 static inline void *current_text_addr(void)
53 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
59 * These alignment constraints are for performance in the vSMP case,
60 * but in the task_struct case we must also meet hardware imposed
61 * alignment requirements of the FPU state:
63 #ifdef CONFIG_X86_VSMP
64 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
67 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
68 # define ARCH_MIN_MMSTRUCT_ALIGN 0
76 extern u16 __read_mostly tlb_lli_4k
[NR_INFO
];
77 extern u16 __read_mostly tlb_lli_2m
[NR_INFO
];
78 extern u16 __read_mostly tlb_lli_4m
[NR_INFO
];
79 extern u16 __read_mostly tlb_lld_4k
[NR_INFO
];
80 extern u16 __read_mostly tlb_lld_2m
[NR_INFO
];
81 extern u16 __read_mostly tlb_lld_4m
[NR_INFO
];
82 extern u16 __read_mostly tlb_lld_1g
[NR_INFO
];
85 * CPU type and hardware bug flags. Kept separately for each CPU.
86 * Members of this structure are referenced in head_32.S, so think twice
87 * before touching them. [mj]
91 __u8 x86
; /* CPU family */
92 __u8 x86_vendor
; /* CPU vendor */
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits
;
104 /* Max extended CPUID function supported: */
105 __u32 extended_cpuid_level
;
106 /* Maximum supported CPUID level, -1=no CPUID: */
108 __u32 x86_capability
[NCAPINTS
+ NBUGINTS
];
109 char x86_vendor_id
[16];
110 char x86_model_id
[64];
111 /* in KB - valid for CPUS which support this call: */
113 int x86_cache_alignment
; /* In bytes */
114 /* Cache QoS architectural values: */
115 int x86_cache_max_rmid
; /* max index */
116 int x86_cache_occ_scale
; /* scale to bytes */
118 unsigned long loops_per_jiffy
;
119 /* cpuid returned max cores value: */
123 u16 x86_clflush_size
;
124 /* number of cores as seen by the OS: */
126 /* Physical processor id: */
128 /* Logical processor id: */
132 /* Index into per_cpu list: */
135 } __randomize_layout
;
138 u32 eax
, ebx
, ecx
, edx
;
141 enum cpuid_regs_idx
{
148 #define X86_VENDOR_INTEL 0
149 #define X86_VENDOR_CYRIX 1
150 #define X86_VENDOR_AMD 2
151 #define X86_VENDOR_UMC 3
152 #define X86_VENDOR_CENTAUR 5
153 #define X86_VENDOR_TRANSMETA 7
154 #define X86_VENDOR_NSC 8
155 #define X86_VENDOR_NUM 9
157 #define X86_VENDOR_UNKNOWN 0xff
160 * capabilities of CPUs
162 extern struct cpuinfo_x86 boot_cpu_data
;
163 extern struct cpuinfo_x86 new_cpu_data
;
165 extern struct x86_hw_tss doublefault_tss
;
166 extern __u32 cpu_caps_cleared
[NCAPINTS
+ NBUGINTS
];
167 extern __u32 cpu_caps_set
[NCAPINTS
+ NBUGINTS
];
170 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
171 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
173 #define cpu_info boot_cpu_data
174 #define cpu_data(cpu) boot_cpu_data
177 extern const struct seq_operations cpuinfo_op
;
179 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
181 extern void cpu_detect(struct cpuinfo_x86
*c
);
183 extern void early_cpu_init(void);
184 extern void identify_boot_cpu(void);
185 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
186 extern void print_cpu_info(struct cpuinfo_x86
*);
187 void print_cpu_msr(struct cpuinfo_x86
*);
188 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
189 extern u32
get_scattered_cpuid_leaf(unsigned int level
,
190 unsigned int sub_leaf
,
191 enum cpuid_regs_idx reg
);
192 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
193 extern void init_amd_cacheinfo(struct cpuinfo_x86
*c
);
195 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
196 extern void detect_ht(struct cpuinfo_x86
*c
);
199 extern int have_cpuid_p(void);
201 static inline int have_cpuid_p(void)
206 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
207 unsigned int *ecx
, unsigned int *edx
)
209 /* ecx is often an input as well as an output. */
215 : "0" (*eax
), "2" (*ecx
)
219 #define native_cpuid_reg(reg) \
220 static inline unsigned int native_cpuid_##reg(unsigned int op) \
222 unsigned int eax = op, ebx, ecx = 0, edx; \
224 native_cpuid(&eax, &ebx, &ecx, &edx); \
230 * Native CPUID functions returning a single datum.
232 native_cpuid_reg(eax
)
233 native_cpuid_reg(ebx
)
234 native_cpuid_reg(ecx
)
235 native_cpuid_reg(edx
)
238 * Friendlier CR3 helpers.
240 static inline unsigned long read_cr3_pa(void)
242 return __read_cr3() & CR3_ADDR_MASK
;
245 static inline unsigned long native_read_cr3_pa(void)
247 return __native_read_cr3() & CR3_ADDR_MASK
;
250 static inline void load_cr3(pgd_t
*pgdir
)
252 write_cr3(__sme_pa(pgdir
));
256 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
257 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
258 * unrelated to the task-switch mechanism:
261 /* This is the TSS defined by the hardware. */
263 unsigned short back_link
, __blh
;
265 unsigned short ss0
, __ss0h
;
269 * We don't use ring 1, so ss1 is a convenient scratch space in
270 * the same cacheline as sp0. We use ss1 to cache the value in
271 * MSR_IA32_SYSENTER_CS. When we context switch
272 * MSR_IA32_SYSENTER_CS, we first check if the new value being
273 * written matches ss1, and, if it's not, then we wrmsr the new
274 * value and update ss1.
276 * The only reason we context switch MSR_IA32_SYSENTER_CS is
277 * that we set it to zero in vm86 tasks to avoid corrupting the
278 * stack if we were to go through the sysenter path from vm86
281 unsigned short ss1
; /* MSR_IA32_SYSENTER_CS */
283 unsigned short __ss1h
;
285 unsigned short ss2
, __ss2h
;
297 unsigned short es
, __esh
;
298 unsigned short cs
, __csh
;
299 unsigned short ss
, __ssh
;
300 unsigned short ds
, __dsh
;
301 unsigned short fs
, __fsh
;
302 unsigned short gs
, __gsh
;
303 unsigned short ldt
, __ldth
;
304 unsigned short trace
;
305 unsigned short io_bitmap_base
;
307 } __attribute__((packed
));
314 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
315 * Linux does not use ring 1, so sp1 is not otherwise needed.
327 } __attribute__((packed
));
333 #define IO_BITMAP_BITS 65536
334 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
335 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
336 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
337 #define INVALID_IO_BITMAP_OFFSET 0x8000
340 unsigned long words
[64];
343 struct entry_stack_page
{
344 struct entry_stack stack
;
345 } __aligned(PAGE_SIZE
);
349 * The fixed hardware portion. This must not cross a page boundary
350 * at risk of violating the SDM's advice and potentially triggering
353 struct x86_hw_tss x86_tss
;
356 * The extra 1 is there because the CPU will access an
357 * additional byte beyond the end of the IO permission
358 * bitmap. The extra byte must be all 1 bits, and must
359 * be within the limit.
361 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
362 } __aligned(PAGE_SIZE
);
364 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct
, cpu_tss_rw
);
367 * sizeof(unsigned long) coming from an extra "long" at the end
370 * -1? seg base+limit should be pointing to the address of the
373 #define __KERNEL_TSS_LIMIT \
374 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
377 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack
);
379 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
380 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
384 * Save the original ist values for checking stack pointers during debugging
387 unsigned long ist
[7];
391 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
393 union irq_stack_union
{
394 char irq_stack
[IRQ_STACK_SIZE
];
396 * GCC hardcodes the stack canary as %gs:40. Since the
397 * irq_stack is the object at %gs:0, we reserve the bottom
398 * 48 bytes of the irq stack for the canary.
402 unsigned long stack_canary
;
406 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
) __visible
;
407 DECLARE_INIT_PER_CPU(irq_stack_union
);
409 DECLARE_PER_CPU(char *, irq_stack_ptr
);
410 DECLARE_PER_CPU(unsigned int, irq_count
);
411 extern asmlinkage
void ignore_sysret(void);
413 #ifdef CONFIG_CC_STACKPROTECTOR
415 * Make sure stack canary segment base is cached-aligned:
416 * "For Intel Atom processors, avoid non zero segment base address
417 * that is not aligned to cache line boundary at all cost."
418 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
420 struct stack_canary
{
421 char __pad
[20]; /* canary at %gs:20 */
422 unsigned long canary
;
424 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
427 * per-CPU IRQ handling stacks
430 u32 stack
[THREAD_SIZE
/sizeof(u32
)];
431 } __aligned(THREAD_SIZE
);
433 DECLARE_PER_CPU(struct irq_stack
*, hardirq_stack
);
434 DECLARE_PER_CPU(struct irq_stack
*, softirq_stack
);
437 extern unsigned int fpu_kernel_xstate_size
;
438 extern unsigned int fpu_user_xstate_size
;
446 struct thread_struct
{
447 /* Cached TLS descriptors: */
448 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
454 unsigned long sysenter_cs
;
458 unsigned short fsindex
;
459 unsigned short gsindex
;
462 u32 status
; /* thread synchronous flags */
465 unsigned long fsbase
;
466 unsigned long gsbase
;
469 * XXX: this could presumably be unsigned short. Alternatively,
470 * 32-bit kernels could be taught to use fsindex instead.
476 /* Save middle states of ptrace breakpoints */
477 struct perf_event
*ptrace_bps
[HBP_NUM
];
478 /* Debug status used for traps, single steps, etc... */
479 unsigned long debugreg6
;
480 /* Keep track of the exact dr7 value set by the user */
481 unsigned long ptrace_dr7
;
484 unsigned long trap_nr
;
485 unsigned long error_code
;
487 /* Virtual 86 mode info */
490 /* IO permissions: */
491 unsigned long *io_bitmap_ptr
;
493 /* Max allowed port in the bitmap, in bytes: */
494 unsigned io_bitmap_max
;
496 mm_segment_t addr_limit
;
498 unsigned int sig_on_uaccess_err
:1;
499 unsigned int uaccess_err
:1; /* uaccess failed */
501 /* Floating point and extended processor state */
504 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
510 * Thread-synchronous status.
512 * This is different from the flags in that nobody else
513 * ever touches our thread-synchronous status, so we don't
514 * have to worry about atomic accesses.
516 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
519 * Set IOPL bits in EFLAGS from given mask
521 static inline void native_set_iopl_mask(unsigned mask
)
526 asm volatile ("pushfl;"
533 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
538 native_load_sp0(unsigned long sp0
)
540 this_cpu_write(cpu_tss_rw
.x86_tss
.sp0
, sp0
);
543 static inline void native_swapgs(void)
546 asm volatile("swapgs" ::: "memory");
550 static inline unsigned long current_top_of_stack(void)
553 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
554 * and around vm86 mode and sp0 on x86_64 is special because of the
557 return this_cpu_read_stable(cpu_current_top_of_stack
);
560 static inline bool on_thread_stack(void)
562 return (unsigned long)(current_top_of_stack() -
563 current_stack_pointer
) < THREAD_SIZE
;
566 #ifdef CONFIG_PARAVIRT
567 #include <asm/paravirt.h>
569 #define __cpuid native_cpuid
571 static inline void load_sp0(unsigned long sp0
)
573 native_load_sp0(sp0
);
576 #define set_iopl_mask native_set_iopl_mask
577 #endif /* CONFIG_PARAVIRT */
579 /* Free all resources held by a thread. */
580 extern void release_thread(struct task_struct
*);
582 unsigned long get_wchan(struct task_struct
*p
);
585 * Generic CPUID function
586 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
587 * resulting in stale register contents being returned.
589 static inline void cpuid(unsigned int op
,
590 unsigned int *eax
, unsigned int *ebx
,
591 unsigned int *ecx
, unsigned int *edx
)
595 __cpuid(eax
, ebx
, ecx
, edx
);
598 /* Some CPUID calls want 'count' to be placed in ecx */
599 static inline void cpuid_count(unsigned int op
, int count
,
600 unsigned int *eax
, unsigned int *ebx
,
601 unsigned int *ecx
, unsigned int *edx
)
605 __cpuid(eax
, ebx
, ecx
, edx
);
609 * CPUID functions returning a single datum
611 static inline unsigned int cpuid_eax(unsigned int op
)
613 unsigned int eax
, ebx
, ecx
, edx
;
615 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
620 static inline unsigned int cpuid_ebx(unsigned int op
)
622 unsigned int eax
, ebx
, ecx
, edx
;
624 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
629 static inline unsigned int cpuid_ecx(unsigned int op
)
631 unsigned int eax
, ebx
, ecx
, edx
;
633 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
638 static inline unsigned int cpuid_edx(unsigned int op
)
640 unsigned int eax
, ebx
, ecx
, edx
;
642 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
647 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
648 static __always_inline
void rep_nop(void)
650 asm volatile("rep; nop" ::: "memory");
653 static __always_inline
void cpu_relax(void)
659 * This function forces the icache and prefetched instruction stream to
660 * catch up with reality in two very specific cases:
662 * a) Text was modified using one virtual address and is about to be executed
663 * from the same physical page at a different virtual address.
665 * b) Text was modified on a different CPU, may subsequently be
666 * executed on this CPU, and you want to make sure the new version
667 * gets executed. This generally means you're calling this in a IPI.
669 * If you're calling this for a different reason, you're probably doing
672 static inline void sync_core(void)
675 * There are quite a few ways to do this. IRET-to-self is nice
676 * because it works on every CPU, at any CPL (so it's compatible
677 * with paravirtualization), and it never exits to a hypervisor.
678 * The only down sides are that it's a bit slow (it seems to be
679 * a bit more than 2x slower than the fastest options) and that
680 * it unmasks NMIs. The "push %cs" is needed because, in
681 * paravirtual environments, __KERNEL_CS may not be a valid CS
682 * value when we do IRET directly.
684 * In case NMI unmasking or performance ever becomes a problem,
685 * the next best option appears to be MOV-to-CR2 and an
686 * unconditional jump. That sequence also works on all CPUs,
687 * but it will fault at CPL3 (i.e. Xen PV).
689 * CPUID is the conventional way, but it's nasty: it doesn't
690 * exist on some 486-like CPUs, and it usually exits to a
693 * Like all of Linux's memory ordering operations, this is a
694 * compiler barrier as well.
703 : ASM_CALL_CONSTRAINT
: : "memory");
712 "addq $8, (%%rsp)\n\t"
720 : "=&r" (tmp
), ASM_CALL_CONSTRAINT
: : "cc", "memory");
724 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
725 extern void amd_e400_c1e_apic_setup(void);
727 extern unsigned long boot_option_idle_override
;
729 enum idle_boot_override
{IDLE_NO_OVERRIDE
=0, IDLE_HALT
, IDLE_NOMWAIT
,
732 extern void enable_sep_cpu(void);
733 extern int sysenter_setup(void);
735 extern void early_trap_init(void);
736 void early_trap_pf_init(void);
738 /* Defined in head.S */
739 extern struct desc_ptr early_gdt_descr
;
741 extern void cpu_set_gdt(int);
742 extern void switch_to_new_gdt(int);
743 extern void load_direct_gdt(int);
744 extern void load_fixmap_gdt(int);
745 extern void load_percpu_segment(int);
746 extern void cpu_init(void);
748 static inline unsigned long get_debugctlmsr(void)
750 unsigned long debugctlmsr
= 0;
752 #ifndef CONFIG_X86_DEBUGCTLMSR
753 if (boot_cpu_data
.x86
< 6)
756 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
761 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
763 #ifndef CONFIG_X86_DEBUGCTLMSR
764 if (boot_cpu_data
.x86
< 6)
767 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
770 extern void set_task_blockstep(struct task_struct
*task
, bool on
);
772 /* Boot loader type from the setup header: */
773 extern int bootloader_type
;
774 extern int bootloader_version
;
776 extern char ignore_fpu_irq
;
778 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
779 #define ARCH_HAS_PREFETCHW
780 #define ARCH_HAS_SPINLOCK_PREFETCH
783 # define BASE_PREFETCH ""
784 # define ARCH_HAS_PREFETCH
786 # define BASE_PREFETCH "prefetcht0 %P1"
790 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
792 * It's not worth to care about 3dnow prefetches for the K6
793 * because they are microcoded there and very slow.
795 static inline void prefetch(const void *x
)
797 alternative_input(BASE_PREFETCH
, "prefetchnta %P1",
799 "m" (*(const char *)x
));
803 * 3dnow prefetch to get an exclusive cache line.
804 * Useful for spinlocks to avoid one state transition in the
805 * cache coherency protocol:
807 static inline void prefetchw(const void *x
)
809 alternative_input(BASE_PREFETCH
, "prefetchw %P1",
810 X86_FEATURE_3DNOWPREFETCH
,
811 "m" (*(const char *)x
));
814 static inline void spin_lock_prefetch(const void *x
)
819 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
820 TOP_OF_KERNEL_STACK_PADDING)
822 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
824 #define task_pt_regs(task) \
826 unsigned long __ptr = (unsigned long)task_stack_page(task); \
827 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
828 ((struct pt_regs *)__ptr) - 1; \
833 * User space process size: 3GB (default).
835 #define IA32_PAGE_OFFSET PAGE_OFFSET
836 #define TASK_SIZE PAGE_OFFSET
837 #define TASK_SIZE_LOW TASK_SIZE
838 #define TASK_SIZE_MAX TASK_SIZE
839 #define DEFAULT_MAP_WINDOW TASK_SIZE
840 #define STACK_TOP TASK_SIZE
841 #define STACK_TOP_MAX STACK_TOP
843 #define INIT_THREAD { \
844 .sp0 = TOP_OF_INIT_STACK, \
845 .sysenter_cs = __KERNEL_CS, \
846 .io_bitmap_ptr = NULL, \
847 .addr_limit = KERNEL_DS, \
850 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
854 * User space process size. This is the first address outside the user range.
855 * There are a few constraints that determine this:
857 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
858 * address, then that syscall will enter the kernel with a
859 * non-canonical return address, and SYSRET will explode dangerously.
860 * We avoid this particular problem by preventing anything executable
861 * from being mapped at the maximum canonical address.
863 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
864 * CPUs malfunction if they execute code from the highest canonical page.
865 * They'll speculate right off the end of the canonical space, and
866 * bad things happen. This is worked around in the same way as the
869 * With page table isolation enabled, we map the LDT in ... [stay tuned]
871 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
873 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
875 /* This decides where the kernel will search for a free chunk of vm
876 * space during mmap's.
878 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
879 0xc0000000 : 0xFFFFe000)
881 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
882 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
883 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
884 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
885 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
886 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
888 #define STACK_TOP TASK_SIZE_LOW
889 #define STACK_TOP_MAX TASK_SIZE_MAX
891 #define INIT_THREAD { \
892 .addr_limit = KERNEL_DS, \
895 extern unsigned long KSTK_ESP(struct task_struct
*task
);
897 #endif /* CONFIG_X86_64 */
899 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
900 unsigned long new_sp
);
903 * This decides where the kernel will search for a free chunk of vm
904 * space during mmap's.
906 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
907 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
909 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
911 /* Get/set a process' ability to use the timestamp counter instruction */
912 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
913 #define SET_TSC_CTL(val) set_tsc_mode((val))
915 extern int get_tsc_mode(unsigned long adr
);
916 extern int set_tsc_mode(unsigned int val
);
918 DECLARE_PER_CPU(u64
, msr_misc_features_shadow
);
920 /* Register/unregister a process' MPX related resource */
921 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
922 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
924 #ifdef CONFIG_X86_INTEL_MPX
925 extern int mpx_enable_management(void);
926 extern int mpx_disable_management(void);
928 static inline int mpx_enable_management(void)
932 static inline int mpx_disable_management(void)
936 #endif /* CONFIG_X86_INTEL_MPX */
938 #ifdef CONFIG_CPU_SUP_AMD
939 extern u16
amd_get_nb_id(int cpu
);
940 extern u32
amd_get_nodes_per_socket(void);
942 static inline u16
amd_get_nb_id(int cpu
) { return 0; }
943 static inline u32
amd_get_nodes_per_socket(void) { return 0; }
946 static inline uint32_t hypervisor_cpuid_base(const char *sig
, uint32_t leaves
)
948 uint32_t base
, eax
, signature
[3];
950 for (base
= 0x40000000; base
< 0x40010000; base
+= 0x100) {
951 cpuid(base
, &eax
, &signature
[0], &signature
[1], &signature
[2]);
953 if (!memcmp(sig
, signature
, 12) &&
954 (leaves
== 0 || ((eax
- base
) >= leaves
)))
961 extern unsigned long arch_align_stack(unsigned long sp
);
962 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
964 void default_idle(void);
966 bool xen_set_default_idle(void);
968 #define xen_set_default_idle 0
971 void stop_this_cpu(void *dummy
);
972 void df_debug(struct pt_regs
*regs
, long error_code
);
973 #endif /* _ASM_X86_PROCESSOR_H */