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[people/arne_f/kernel.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
62
63 /****************************************************************************
64 *
65 * Helper functions
66 *
67 ****************************************************************************/
68
69 static inline u16 get_device_id(struct device *dev)
70 {
71 struct pci_dev *pdev = to_pci_dev(dev);
72
73 return calc_devid(pdev->bus->number, pdev->devfn);
74 }
75
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
77 {
78 return dev->archdata.iommu;
79 }
80
81 /*
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
84 */
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
86 {
87 struct dma_ops_domain *entry, *ret = NULL;
88 unsigned long flags;
89 u16 alias = amd_iommu_alias_table[devid];
90
91 if (list_empty(&iommu_pd_list))
92 return NULL;
93
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
95
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
99 ret = entry;
100 break;
101 }
102 }
103
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
105
106 return ret;
107 }
108
109 /*
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
112 */
113 static bool check_device(struct device *dev)
114 {
115 u16 devid;
116
117 if (!dev || !dev->dma_mask)
118 return false;
119
120 /* No device or no PCI device */
121 if (!dev || dev->bus != &pci_bus_type)
122 return false;
123
124 devid = get_device_id(dev);
125
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
128 return false;
129
130 if (amd_iommu_rlookup_table[devid] == NULL)
131 return false;
132
133 return true;
134 }
135
136 static int iommu_init_device(struct device *dev)
137 {
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
140 u16 devid, alias;
141
142 if (dev->archdata.iommu)
143 return 0;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return -ENOMEM;
148
149 dev_data->dev = dev;
150
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
154 if (pdev)
155 dev_data->alias = &pdev->dev;
156
157 atomic_set(&dev_data->bind, 0);
158
159 dev->archdata.iommu = dev_data;
160
161
162 return 0;
163 }
164
165 static void iommu_uninit_device(struct device *dev)
166 {
167 kfree(dev->archdata.iommu);
168 }
169
170 void __init amd_iommu_uninit_devices(void)
171 {
172 struct pci_dev *pdev = NULL;
173
174 for_each_pci_dev(pdev) {
175
176 if (!check_device(&pdev->dev))
177 continue;
178
179 iommu_uninit_device(&pdev->dev);
180 }
181 }
182
183 int __init amd_iommu_init_devices(void)
184 {
185 struct pci_dev *pdev = NULL;
186 int ret = 0;
187
188 for_each_pci_dev(pdev) {
189
190 if (!check_device(&pdev->dev))
191 continue;
192
193 ret = iommu_init_device(&pdev->dev);
194 if (ret)
195 goto out_free;
196 }
197
198 return 0;
199
200 out_free:
201
202 amd_iommu_uninit_devices();
203
204 return ret;
205 }
206 #ifdef CONFIG_AMD_IOMMU_STATS
207
208 /*
209 * Initialization code for statistics collection
210 */
211
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
224
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
227
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
229 {
230 if (stats_dir == NULL)
231 return;
232
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
234 &cnt->value);
235 }
236
237 static void amd_iommu_stats_init(void)
238 {
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
241 return;
242
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
245
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
258 }
259
260 #endif
261
262 /****************************************************************************
263 *
264 * Interrupt handling functions
265 *
266 ****************************************************************************/
267
268 static void dump_dte_entry(u16 devid)
269 {
270 int i;
271
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
275 }
276
277 static void dump_command(unsigned long phys_addr)
278 {
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
280 int i;
281
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
284 }
285
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
287 {
288 u32 *event = __evt;
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
294
295 printk(KERN_ERR "AMD-Vi: Event logged [");
296
297 switch (type) {
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
302 address, flags);
303 dump_dte_entry(devid);
304 break;
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
310 break;
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
315 address, flags);
316 break;
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
322 break;
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 iommu->reset_in_progress = true;
326 reset_iommu_command_buffer(iommu);
327 dump_command(address);
328 break;
329 case EVENT_TYPE_CMD_HARD_ERR:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address, flags);
332 break;
333 case EVENT_TYPE_IOTLB_INV_TO:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
337 address);
338 break;
339 case EVENT_TYPE_INV_DEV_REQ:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
343 address, flags);
344 break;
345 default:
346 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
347 }
348 }
349
350 static void iommu_poll_events(struct amd_iommu *iommu)
351 {
352 u32 head, tail;
353 unsigned long flags;
354
355 spin_lock_irqsave(&iommu->lock, flags);
356
357 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
358 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
359
360 while (head != tail) {
361 iommu_print_event(iommu, iommu->evt_buf + head);
362 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
363 }
364
365 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
366
367 spin_unlock_irqrestore(&iommu->lock, flags);
368 }
369
370 irqreturn_t amd_iommu_int_handler(int irq, void *data)
371 {
372 struct amd_iommu *iommu;
373
374 for_each_iommu(iommu)
375 iommu_poll_events(iommu);
376
377 return IRQ_HANDLED;
378 }
379
380 /****************************************************************************
381 *
382 * IOMMU command queuing functions
383 *
384 ****************************************************************************/
385
386 /*
387 * Writes the command to the IOMMUs command buffer and informs the
388 * hardware about the new command. Must be called with iommu->lock held.
389 */
390 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
391 {
392 u32 tail, head;
393 u8 *target;
394
395 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
396 target = iommu->cmd_buf + tail;
397 memcpy_toio(target, cmd, sizeof(*cmd));
398 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
399 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
400 if (tail == head)
401 return -ENOMEM;
402 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
403
404 return 0;
405 }
406
407 /*
408 * General queuing function for commands. Takes iommu->lock and calls
409 * __iommu_queue_command().
410 */
411 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
412 {
413 unsigned long flags;
414 int ret;
415
416 spin_lock_irqsave(&iommu->lock, flags);
417 ret = __iommu_queue_command(iommu, cmd);
418 if (!ret)
419 iommu->need_sync = true;
420 spin_unlock_irqrestore(&iommu->lock, flags);
421
422 return ret;
423 }
424
425 /*
426 * This function waits until an IOMMU has completed a completion
427 * wait command
428 */
429 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
430 {
431 int ready = 0;
432 unsigned status = 0;
433 unsigned long i = 0;
434
435 INC_STATS_COUNTER(compl_wait);
436
437 while (!ready && (i < EXIT_LOOP_COUNT)) {
438 ++i;
439 /* wait for the bit to become one */
440 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
441 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
442 }
443
444 /* set bit back to zero */
445 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
446 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
447
448 if (unlikely(i == EXIT_LOOP_COUNT))
449 iommu->reset_in_progress = true;
450 }
451
452 /*
453 * This function queues a completion wait command into the command
454 * buffer of an IOMMU
455 */
456 static int __iommu_completion_wait(struct amd_iommu *iommu)
457 {
458 struct iommu_cmd cmd;
459
460 memset(&cmd, 0, sizeof(cmd));
461 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
462 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
463
464 return __iommu_queue_command(iommu, &cmd);
465 }
466
467 /*
468 * This function is called whenever we need to ensure that the IOMMU has
469 * completed execution of all commands we sent. It sends a
470 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
471 * us about that by writing a value to a physical address we pass with
472 * the command.
473 */
474 static int iommu_completion_wait(struct amd_iommu *iommu)
475 {
476 int ret = 0;
477 unsigned long flags;
478
479 spin_lock_irqsave(&iommu->lock, flags);
480
481 if (!iommu->need_sync)
482 goto out;
483
484 ret = __iommu_completion_wait(iommu);
485
486 iommu->need_sync = false;
487
488 if (ret)
489 goto out;
490
491 __iommu_wait_for_completion(iommu);
492
493 out:
494 spin_unlock_irqrestore(&iommu->lock, flags);
495
496 if (iommu->reset_in_progress)
497 reset_iommu_command_buffer(iommu);
498
499 return 0;
500 }
501
502 static void iommu_flush_complete(struct protection_domain *domain)
503 {
504 int i;
505
506 for (i = 0; i < amd_iommus_present; ++i) {
507 if (!domain->dev_iommu[i])
508 continue;
509
510 /*
511 * Devices of this domain are behind this IOMMU
512 * We need to wait for completion of all commands.
513 */
514 iommu_completion_wait(amd_iommus[i]);
515 }
516 }
517
518 /*
519 * Command send function for invalidating a device table entry
520 */
521 static int iommu_flush_device(struct device *dev)
522 {
523 struct amd_iommu *iommu;
524 struct iommu_cmd cmd;
525 u16 devid;
526
527 devid = get_device_id(dev);
528 iommu = amd_iommu_rlookup_table[devid];
529
530 /* Build command */
531 memset(&cmd, 0, sizeof(cmd));
532 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
533 cmd.data[0] = devid;
534
535 return iommu_queue_command(iommu, &cmd);
536 }
537
538 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
539 u16 domid, int pde, int s)
540 {
541 memset(cmd, 0, sizeof(*cmd));
542 address &= PAGE_MASK;
543 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
544 cmd->data[1] |= domid;
545 cmd->data[2] = lower_32_bits(address);
546 cmd->data[3] = upper_32_bits(address);
547 if (s) /* size bit - we flush more than one 4kb page */
548 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
549 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
550 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
551 }
552
553 /*
554 * Generic command send function for invalidaing TLB entries
555 */
556 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
557 u64 address, u16 domid, int pde, int s)
558 {
559 struct iommu_cmd cmd;
560 int ret;
561
562 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
563
564 ret = iommu_queue_command(iommu, &cmd);
565
566 return ret;
567 }
568
569 /*
570 * TLB invalidation function which is called from the mapping functions.
571 * It invalidates a single PTE if the range to flush is within a single
572 * page. Otherwise it flushes the whole TLB of the IOMMU.
573 */
574 static void __iommu_flush_pages(struct protection_domain *domain,
575 u64 address, size_t size, int pde)
576 {
577 int s = 0, i;
578 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
579
580 address &= PAGE_MASK;
581
582 if (pages > 1) {
583 /*
584 * If we have to flush more than one page, flush all
585 * TLB entries for this domain
586 */
587 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
588 s = 1;
589 }
590
591
592 for (i = 0; i < amd_iommus_present; ++i) {
593 if (!domain->dev_iommu[i])
594 continue;
595
596 /*
597 * Devices of this domain are behind this IOMMU
598 * We need a TLB flush
599 */
600 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
601 domain->id, pde, s);
602 }
603
604 return;
605 }
606
607 static void iommu_flush_pages(struct protection_domain *domain,
608 u64 address, size_t size)
609 {
610 __iommu_flush_pages(domain, address, size, 0);
611 }
612
613 /* Flush the whole IO/TLB for a given protection domain */
614 static void iommu_flush_tlb(struct protection_domain *domain)
615 {
616 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
617 }
618
619 /* Flush the whole IO/TLB for a given protection domain - including PDE */
620 static void iommu_flush_tlb_pde(struct protection_domain *domain)
621 {
622 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
623 }
624
625
626 /*
627 * This function flushes the DTEs for all devices in domain
628 */
629 static void iommu_flush_domain_devices(struct protection_domain *domain)
630 {
631 struct iommu_dev_data *dev_data;
632 unsigned long flags;
633
634 spin_lock_irqsave(&domain->lock, flags);
635
636 list_for_each_entry(dev_data, &domain->dev_list, list)
637 iommu_flush_device(dev_data->dev);
638
639 spin_unlock_irqrestore(&domain->lock, flags);
640 }
641
642 static void iommu_flush_all_domain_devices(void)
643 {
644 struct protection_domain *domain;
645 unsigned long flags;
646
647 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
648
649 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
650 iommu_flush_domain_devices(domain);
651 iommu_flush_complete(domain);
652 }
653
654 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
655 }
656
657 void amd_iommu_flush_all_devices(void)
658 {
659 iommu_flush_all_domain_devices();
660 }
661
662 /*
663 * This function uses heavy locking and may disable irqs for some time. But
664 * this is no issue because it is only called during resume.
665 */
666 void amd_iommu_flush_all_domains(void)
667 {
668 struct protection_domain *domain;
669 unsigned long flags;
670
671 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
672
673 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
674 spin_lock(&domain->lock);
675 iommu_flush_tlb_pde(domain);
676 iommu_flush_complete(domain);
677 spin_unlock(&domain->lock);
678 }
679
680 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
681 }
682
683 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
684 {
685 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
686
687 if (iommu->reset_in_progress)
688 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
689
690 amd_iommu_reset_cmd_buffer(iommu);
691 amd_iommu_flush_all_devices();
692 amd_iommu_flush_all_domains();
693
694 iommu->reset_in_progress = false;
695 }
696
697 /****************************************************************************
698 *
699 * The functions below are used the create the page table mappings for
700 * unity mapped regions.
701 *
702 ****************************************************************************/
703
704 /*
705 * This function is used to add another level to an IO page table. Adding
706 * another level increases the size of the address space by 9 bits to a size up
707 * to 64 bits.
708 */
709 static bool increase_address_space(struct protection_domain *domain,
710 gfp_t gfp)
711 {
712 u64 *pte;
713
714 if (domain->mode == PAGE_MODE_6_LEVEL)
715 /* address space already 64 bit large */
716 return false;
717
718 pte = (void *)get_zeroed_page(gfp);
719 if (!pte)
720 return false;
721
722 *pte = PM_LEVEL_PDE(domain->mode,
723 virt_to_phys(domain->pt_root));
724 domain->pt_root = pte;
725 domain->mode += 1;
726 domain->updated = true;
727
728 return true;
729 }
730
731 static u64 *alloc_pte(struct protection_domain *domain,
732 unsigned long address,
733 int end_lvl,
734 u64 **pte_page,
735 gfp_t gfp)
736 {
737 u64 *pte, *page;
738 int level;
739
740 while (address > PM_LEVEL_SIZE(domain->mode))
741 increase_address_space(domain, gfp);
742
743 level = domain->mode - 1;
744 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
745
746 while (level > end_lvl) {
747 if (!IOMMU_PTE_PRESENT(*pte)) {
748 page = (u64 *)get_zeroed_page(gfp);
749 if (!page)
750 return NULL;
751 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
752 }
753
754 level -= 1;
755
756 pte = IOMMU_PTE_PAGE(*pte);
757
758 if (pte_page && level == end_lvl)
759 *pte_page = pte;
760
761 pte = &pte[PM_LEVEL_INDEX(level, address)];
762 }
763
764 return pte;
765 }
766
767 /*
768 * This function checks if there is a PTE for a given dma address. If
769 * there is one, it returns the pointer to it.
770 */
771 static u64 *fetch_pte(struct protection_domain *domain,
772 unsigned long address, int map_size)
773 {
774 int level;
775 u64 *pte;
776
777 level = domain->mode - 1;
778 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
779
780 while (level > map_size) {
781 if (!IOMMU_PTE_PRESENT(*pte))
782 return NULL;
783
784 level -= 1;
785
786 pte = IOMMU_PTE_PAGE(*pte);
787 pte = &pte[PM_LEVEL_INDEX(level, address)];
788
789 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
790 pte = NULL;
791 break;
792 }
793 }
794
795 return pte;
796 }
797
798 /*
799 * Generic mapping functions. It maps a physical address into a DMA
800 * address space. It allocates the page table pages if necessary.
801 * In the future it can be extended to a generic mapping function
802 * supporting all features of AMD IOMMU page tables like level skipping
803 * and full 64 bit address spaces.
804 */
805 static int iommu_map_page(struct protection_domain *dom,
806 unsigned long bus_addr,
807 unsigned long phys_addr,
808 int prot,
809 int map_size)
810 {
811 u64 __pte, *pte;
812
813 bus_addr = PAGE_ALIGN(bus_addr);
814 phys_addr = PAGE_ALIGN(phys_addr);
815
816 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
817 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
818
819 if (!(prot & IOMMU_PROT_MASK))
820 return -EINVAL;
821
822 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
823
824 if (IOMMU_PTE_PRESENT(*pte))
825 return -EBUSY;
826
827 __pte = phys_addr | IOMMU_PTE_P;
828 if (prot & IOMMU_PROT_IR)
829 __pte |= IOMMU_PTE_IR;
830 if (prot & IOMMU_PROT_IW)
831 __pte |= IOMMU_PTE_IW;
832
833 *pte = __pte;
834
835 update_domain(dom);
836
837 return 0;
838 }
839
840 static void iommu_unmap_page(struct protection_domain *dom,
841 unsigned long bus_addr, int map_size)
842 {
843 u64 *pte = fetch_pte(dom, bus_addr, map_size);
844
845 if (pte)
846 *pte = 0;
847 }
848
849 /*
850 * This function checks if a specific unity mapping entry is needed for
851 * this specific IOMMU.
852 */
853 static int iommu_for_unity_map(struct amd_iommu *iommu,
854 struct unity_map_entry *entry)
855 {
856 u16 bdf, i;
857
858 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
859 bdf = amd_iommu_alias_table[i];
860 if (amd_iommu_rlookup_table[bdf] == iommu)
861 return 1;
862 }
863
864 return 0;
865 }
866
867 /*
868 * This function actually applies the mapping to the page table of the
869 * dma_ops domain.
870 */
871 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
872 struct unity_map_entry *e)
873 {
874 u64 addr;
875 int ret;
876
877 for (addr = e->address_start; addr < e->address_end;
878 addr += PAGE_SIZE) {
879 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
880 PM_MAP_4k);
881 if (ret)
882 return ret;
883 /*
884 * if unity mapping is in aperture range mark the page
885 * as allocated in the aperture
886 */
887 if (addr < dma_dom->aperture_size)
888 __set_bit(addr >> PAGE_SHIFT,
889 dma_dom->aperture[0]->bitmap);
890 }
891
892 return 0;
893 }
894
895 /*
896 * Init the unity mappings for a specific IOMMU in the system
897 *
898 * Basically iterates over all unity mapping entries and applies them to
899 * the default domain DMA of that IOMMU if necessary.
900 */
901 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
902 {
903 struct unity_map_entry *entry;
904 int ret;
905
906 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
907 if (!iommu_for_unity_map(iommu, entry))
908 continue;
909 ret = dma_ops_unity_map(iommu->default_dom, entry);
910 if (ret)
911 return ret;
912 }
913
914 return 0;
915 }
916
917 /*
918 * Inits the unity mappings required for a specific device
919 */
920 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
921 u16 devid)
922 {
923 struct unity_map_entry *e;
924 int ret;
925
926 list_for_each_entry(e, &amd_iommu_unity_map, list) {
927 if (!(devid >= e->devid_start && devid <= e->devid_end))
928 continue;
929 ret = dma_ops_unity_map(dma_dom, e);
930 if (ret)
931 return ret;
932 }
933
934 return 0;
935 }
936
937 /****************************************************************************
938 *
939 * The next functions belong to the address allocator for the dma_ops
940 * interface functions. They work like the allocators in the other IOMMU
941 * drivers. Its basically a bitmap which marks the allocated pages in
942 * the aperture. Maybe it could be enhanced in the future to a more
943 * efficient allocator.
944 *
945 ****************************************************************************/
946
947 /*
948 * The address allocator core functions.
949 *
950 * called with domain->lock held
951 */
952
953 /*
954 * Used to reserve address ranges in the aperture (e.g. for exclusion
955 * ranges.
956 */
957 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
958 unsigned long start_page,
959 unsigned int pages)
960 {
961 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
962
963 if (start_page + pages > last_page)
964 pages = last_page - start_page;
965
966 for (i = start_page; i < start_page + pages; ++i) {
967 int index = i / APERTURE_RANGE_PAGES;
968 int page = i % APERTURE_RANGE_PAGES;
969 __set_bit(page, dom->aperture[index]->bitmap);
970 }
971 }
972
973 /*
974 * This function is used to add a new aperture range to an existing
975 * aperture in case of dma_ops domain allocation or address allocation
976 * failure.
977 */
978 static int alloc_new_range(struct dma_ops_domain *dma_dom,
979 bool populate, gfp_t gfp)
980 {
981 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
982 struct amd_iommu *iommu;
983 unsigned long i;
984
985 #ifdef CONFIG_IOMMU_STRESS
986 populate = false;
987 #endif
988
989 if (index >= APERTURE_MAX_RANGES)
990 return -ENOMEM;
991
992 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
993 if (!dma_dom->aperture[index])
994 return -ENOMEM;
995
996 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
997 if (!dma_dom->aperture[index]->bitmap)
998 goto out_free;
999
1000 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1001
1002 if (populate) {
1003 unsigned long address = dma_dom->aperture_size;
1004 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1005 u64 *pte, *pte_page;
1006
1007 for (i = 0; i < num_ptes; ++i) {
1008 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
1009 &pte_page, gfp);
1010 if (!pte)
1011 goto out_free;
1012
1013 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1014
1015 address += APERTURE_RANGE_SIZE / 64;
1016 }
1017 }
1018
1019 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1020
1021 /* Intialize the exclusion range if necessary */
1022 for_each_iommu(iommu) {
1023 if (iommu->exclusion_start &&
1024 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1025 && iommu->exclusion_start < dma_dom->aperture_size) {
1026 unsigned long startpage;
1027 int pages = iommu_num_pages(iommu->exclusion_start,
1028 iommu->exclusion_length,
1029 PAGE_SIZE);
1030 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1031 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1032 }
1033 }
1034
1035 /*
1036 * Check for areas already mapped as present in the new aperture
1037 * range and mark those pages as reserved in the allocator. Such
1038 * mappings may already exist as a result of requested unity
1039 * mappings for devices.
1040 */
1041 for (i = dma_dom->aperture[index]->offset;
1042 i < dma_dom->aperture_size;
1043 i += PAGE_SIZE) {
1044 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1045 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1046 continue;
1047
1048 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1049 }
1050
1051 update_domain(&dma_dom->domain);
1052
1053 return 0;
1054
1055 out_free:
1056 update_domain(&dma_dom->domain);
1057
1058 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1059
1060 kfree(dma_dom->aperture[index]);
1061 dma_dom->aperture[index] = NULL;
1062
1063 return -ENOMEM;
1064 }
1065
1066 static unsigned long dma_ops_area_alloc(struct device *dev,
1067 struct dma_ops_domain *dom,
1068 unsigned int pages,
1069 unsigned long align_mask,
1070 u64 dma_mask,
1071 unsigned long start)
1072 {
1073 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1074 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1075 int i = start >> APERTURE_RANGE_SHIFT;
1076 unsigned long boundary_size;
1077 unsigned long address = -1;
1078 unsigned long limit;
1079
1080 next_bit >>= PAGE_SHIFT;
1081
1082 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1083 PAGE_SIZE) >> PAGE_SHIFT;
1084
1085 for (;i < max_index; ++i) {
1086 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1087
1088 if (dom->aperture[i]->offset >= dma_mask)
1089 break;
1090
1091 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1092 dma_mask >> PAGE_SHIFT);
1093
1094 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1095 limit, next_bit, pages, 0,
1096 boundary_size, align_mask);
1097 if (address != -1) {
1098 address = dom->aperture[i]->offset +
1099 (address << PAGE_SHIFT);
1100 dom->next_address = address + (pages << PAGE_SHIFT);
1101 break;
1102 }
1103
1104 next_bit = 0;
1105 }
1106
1107 return address;
1108 }
1109
1110 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1111 struct dma_ops_domain *dom,
1112 unsigned int pages,
1113 unsigned long align_mask,
1114 u64 dma_mask)
1115 {
1116 unsigned long address;
1117
1118 #ifdef CONFIG_IOMMU_STRESS
1119 dom->next_address = 0;
1120 dom->need_flush = true;
1121 #endif
1122
1123 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1124 dma_mask, dom->next_address);
1125
1126 if (address == -1) {
1127 dom->next_address = 0;
1128 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1129 dma_mask, 0);
1130 dom->need_flush = true;
1131 }
1132
1133 if (unlikely(address == -1))
1134 address = DMA_ERROR_CODE;
1135
1136 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1137
1138 return address;
1139 }
1140
1141 /*
1142 * The address free function.
1143 *
1144 * called with domain->lock held
1145 */
1146 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1147 unsigned long address,
1148 unsigned int pages)
1149 {
1150 unsigned i = address >> APERTURE_RANGE_SHIFT;
1151 struct aperture_range *range = dom->aperture[i];
1152
1153 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1154
1155 #ifdef CONFIG_IOMMU_STRESS
1156 if (i < 4)
1157 return;
1158 #endif
1159
1160 if (address >= dom->next_address)
1161 dom->need_flush = true;
1162
1163 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1164
1165 bitmap_clear(range->bitmap, address, pages);
1166
1167 }
1168
1169 /****************************************************************************
1170 *
1171 * The next functions belong to the domain allocation. A domain is
1172 * allocated for every IOMMU as the default domain. If device isolation
1173 * is enabled, every device get its own domain. The most important thing
1174 * about domains is the page table mapping the DMA address space they
1175 * contain.
1176 *
1177 ****************************************************************************/
1178
1179 /*
1180 * This function adds a protection domain to the global protection domain list
1181 */
1182 static void add_domain_to_list(struct protection_domain *domain)
1183 {
1184 unsigned long flags;
1185
1186 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1187 list_add(&domain->list, &amd_iommu_pd_list);
1188 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1189 }
1190
1191 /*
1192 * This function removes a protection domain to the global
1193 * protection domain list
1194 */
1195 static void del_domain_from_list(struct protection_domain *domain)
1196 {
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1200 list_del(&domain->list);
1201 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1202 }
1203
1204 static u16 domain_id_alloc(void)
1205 {
1206 unsigned long flags;
1207 int id;
1208
1209 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1210 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1211 BUG_ON(id == 0);
1212 if (id > 0 && id < MAX_DOMAIN_ID)
1213 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1214 else
1215 id = 0;
1216 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1217
1218 return id;
1219 }
1220
1221 static void domain_id_free(int id)
1222 {
1223 unsigned long flags;
1224
1225 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1226 if (id > 0 && id < MAX_DOMAIN_ID)
1227 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1228 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1229 }
1230
1231 static void free_pagetable(struct protection_domain *domain)
1232 {
1233 int i, j;
1234 u64 *p1, *p2, *p3;
1235
1236 p1 = domain->pt_root;
1237
1238 if (!p1)
1239 return;
1240
1241 for (i = 0; i < 512; ++i) {
1242 if (!IOMMU_PTE_PRESENT(p1[i]))
1243 continue;
1244
1245 p2 = IOMMU_PTE_PAGE(p1[i]);
1246 for (j = 0; j < 512; ++j) {
1247 if (!IOMMU_PTE_PRESENT(p2[j]))
1248 continue;
1249 p3 = IOMMU_PTE_PAGE(p2[j]);
1250 free_page((unsigned long)p3);
1251 }
1252
1253 free_page((unsigned long)p2);
1254 }
1255
1256 free_page((unsigned long)p1);
1257
1258 domain->pt_root = NULL;
1259 }
1260
1261 /*
1262 * Free a domain, only used if something went wrong in the
1263 * allocation path and we need to free an already allocated page table
1264 */
1265 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1266 {
1267 int i;
1268
1269 if (!dom)
1270 return;
1271
1272 del_domain_from_list(&dom->domain);
1273
1274 free_pagetable(&dom->domain);
1275
1276 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1277 if (!dom->aperture[i])
1278 continue;
1279 free_page((unsigned long)dom->aperture[i]->bitmap);
1280 kfree(dom->aperture[i]);
1281 }
1282
1283 kfree(dom);
1284 }
1285
1286 /*
1287 * Allocates a new protection domain usable for the dma_ops functions.
1288 * It also intializes the page table and the address allocator data
1289 * structures required for the dma_ops interface
1290 */
1291 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1292 {
1293 struct dma_ops_domain *dma_dom;
1294
1295 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1296 if (!dma_dom)
1297 return NULL;
1298
1299 spin_lock_init(&dma_dom->domain.lock);
1300
1301 dma_dom->domain.id = domain_id_alloc();
1302 if (dma_dom->domain.id == 0)
1303 goto free_dma_dom;
1304 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1305 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1306 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1307 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1308 dma_dom->domain.priv = dma_dom;
1309 if (!dma_dom->domain.pt_root)
1310 goto free_dma_dom;
1311
1312 dma_dom->need_flush = false;
1313 dma_dom->target_dev = 0xffff;
1314
1315 add_domain_to_list(&dma_dom->domain);
1316
1317 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1318 goto free_dma_dom;
1319
1320 /*
1321 * mark the first page as allocated so we never return 0 as
1322 * a valid dma-address. So we can use 0 as error value
1323 */
1324 dma_dom->aperture[0]->bitmap[0] = 1;
1325 dma_dom->next_address = 0;
1326
1327
1328 return dma_dom;
1329
1330 free_dma_dom:
1331 dma_ops_domain_free(dma_dom);
1332
1333 return NULL;
1334 }
1335
1336 /*
1337 * little helper function to check whether a given protection domain is a
1338 * dma_ops domain
1339 */
1340 static bool dma_ops_domain(struct protection_domain *domain)
1341 {
1342 return domain->flags & PD_DMA_OPS_MASK;
1343 }
1344
1345 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1346 {
1347 u64 pte_root = virt_to_phys(domain->pt_root);
1348
1349 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1350 << DEV_ENTRY_MODE_SHIFT;
1351 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1352
1353 amd_iommu_dev_table[devid].data[2] = domain->id;
1354 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1355 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1356 }
1357
1358 static void clear_dte_entry(u16 devid)
1359 {
1360 /* remove entry from the device table seen by the hardware */
1361 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1362 amd_iommu_dev_table[devid].data[1] = 0;
1363 amd_iommu_dev_table[devid].data[2] = 0;
1364
1365 amd_iommu_apply_erratum_63(devid);
1366 }
1367
1368 static void do_attach(struct device *dev, struct protection_domain *domain)
1369 {
1370 struct iommu_dev_data *dev_data;
1371 struct amd_iommu *iommu;
1372 u16 devid;
1373
1374 devid = get_device_id(dev);
1375 iommu = amd_iommu_rlookup_table[devid];
1376 dev_data = get_dev_data(dev);
1377
1378 /* Update data structures */
1379 dev_data->domain = domain;
1380 list_add(&dev_data->list, &domain->dev_list);
1381 set_dte_entry(devid, domain);
1382
1383 /* Do reference counting */
1384 domain->dev_iommu[iommu->index] += 1;
1385 domain->dev_cnt += 1;
1386
1387 /* Flush the DTE entry */
1388 iommu_flush_device(dev);
1389 }
1390
1391 static void do_detach(struct device *dev)
1392 {
1393 struct iommu_dev_data *dev_data;
1394 struct amd_iommu *iommu;
1395 u16 devid;
1396
1397 devid = get_device_id(dev);
1398 iommu = amd_iommu_rlookup_table[devid];
1399 dev_data = get_dev_data(dev);
1400
1401 /* decrease reference counters */
1402 dev_data->domain->dev_iommu[iommu->index] -= 1;
1403 dev_data->domain->dev_cnt -= 1;
1404
1405 /* Update data structures */
1406 dev_data->domain = NULL;
1407 list_del(&dev_data->list);
1408 clear_dte_entry(devid);
1409
1410 /* Flush the DTE entry */
1411 iommu_flush_device(dev);
1412 }
1413
1414 /*
1415 * If a device is not yet associated with a domain, this function does
1416 * assigns it visible for the hardware
1417 */
1418 static int __attach_device(struct device *dev,
1419 struct protection_domain *domain)
1420 {
1421 struct iommu_dev_data *dev_data, *alias_data;
1422
1423 dev_data = get_dev_data(dev);
1424 alias_data = get_dev_data(dev_data->alias);
1425
1426 if (!alias_data)
1427 return -EINVAL;
1428
1429 /* lock domain */
1430 spin_lock(&domain->lock);
1431
1432 /* Some sanity checks */
1433 if (alias_data->domain != NULL &&
1434 alias_data->domain != domain)
1435 return -EBUSY;
1436
1437 if (dev_data->domain != NULL &&
1438 dev_data->domain != domain)
1439 return -EBUSY;
1440
1441 /* Do real assignment */
1442 if (dev_data->alias != dev) {
1443 alias_data = get_dev_data(dev_data->alias);
1444 if (alias_data->domain == NULL)
1445 do_attach(dev_data->alias, domain);
1446
1447 atomic_inc(&alias_data->bind);
1448 }
1449
1450 if (dev_data->domain == NULL)
1451 do_attach(dev, domain);
1452
1453 atomic_inc(&dev_data->bind);
1454
1455 /* ready */
1456 spin_unlock(&domain->lock);
1457
1458 return 0;
1459 }
1460
1461 /*
1462 * If a device is not yet associated with a domain, this function does
1463 * assigns it visible for the hardware
1464 */
1465 static int attach_device(struct device *dev,
1466 struct protection_domain *domain)
1467 {
1468 unsigned long flags;
1469 int ret;
1470
1471 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1472 ret = __attach_device(dev, domain);
1473 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1474
1475 /*
1476 * We might boot into a crash-kernel here. The crashed kernel
1477 * left the caches in the IOMMU dirty. So we have to flush
1478 * here to evict all dirty stuff.
1479 */
1480 iommu_flush_tlb_pde(domain);
1481
1482 return ret;
1483 }
1484
1485 /*
1486 * Removes a device from a protection domain (unlocked)
1487 */
1488 static void __detach_device(struct device *dev)
1489 {
1490 struct iommu_dev_data *dev_data = get_dev_data(dev);
1491 struct iommu_dev_data *alias_data;
1492 struct protection_domain *domain;
1493 unsigned long flags;
1494
1495 BUG_ON(!dev_data->domain);
1496
1497 domain = dev_data->domain;
1498
1499 spin_lock_irqsave(&domain->lock, flags);
1500
1501 if (dev_data->alias != dev) {
1502 alias_data = get_dev_data(dev_data->alias);
1503 if (atomic_dec_and_test(&alias_data->bind))
1504 do_detach(dev_data->alias);
1505 }
1506
1507 if (atomic_dec_and_test(&dev_data->bind))
1508 do_detach(dev);
1509
1510 spin_unlock_irqrestore(&domain->lock, flags);
1511
1512 /*
1513 * If we run in passthrough mode the device must be assigned to the
1514 * passthrough domain if it is detached from any other domain.
1515 * Make sure we can deassign from the pt_domain itself.
1516 */
1517 if (iommu_pass_through &&
1518 (dev_data->domain == NULL && domain != pt_domain))
1519 __attach_device(dev, pt_domain);
1520 }
1521
1522 /*
1523 * Removes a device from a protection domain (with devtable_lock held)
1524 */
1525 static void detach_device(struct device *dev)
1526 {
1527 unsigned long flags;
1528
1529 /* lock device table */
1530 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1531 __detach_device(dev);
1532 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1533 }
1534
1535 /*
1536 * Find out the protection domain structure for a given PCI device. This
1537 * will give us the pointer to the page table root for example.
1538 */
1539 static struct protection_domain *domain_for_device(struct device *dev)
1540 {
1541 struct protection_domain *dom;
1542 struct iommu_dev_data *dev_data, *alias_data;
1543 unsigned long flags;
1544 u16 devid, alias;
1545
1546 devid = get_device_id(dev);
1547 alias = amd_iommu_alias_table[devid];
1548 dev_data = get_dev_data(dev);
1549 alias_data = get_dev_data(dev_data->alias);
1550 if (!alias_data)
1551 return NULL;
1552
1553 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1554 dom = dev_data->domain;
1555 if (dom == NULL &&
1556 alias_data->domain != NULL) {
1557 __attach_device(dev, alias_data->domain);
1558 dom = alias_data->domain;
1559 }
1560
1561 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1562
1563 return dom;
1564 }
1565
1566 static int device_change_notifier(struct notifier_block *nb,
1567 unsigned long action, void *data)
1568 {
1569 struct device *dev = data;
1570 u16 devid;
1571 struct protection_domain *domain;
1572 struct dma_ops_domain *dma_domain;
1573 struct amd_iommu *iommu;
1574 unsigned long flags;
1575
1576 if (!check_device(dev))
1577 return 0;
1578
1579 devid = get_device_id(dev);
1580 iommu = amd_iommu_rlookup_table[devid];
1581
1582 switch (action) {
1583 case BUS_NOTIFY_UNBOUND_DRIVER:
1584
1585 domain = domain_for_device(dev);
1586
1587 if (!domain)
1588 goto out;
1589 if (iommu_pass_through)
1590 break;
1591 detach_device(dev);
1592 break;
1593 case BUS_NOTIFY_ADD_DEVICE:
1594
1595 iommu_init_device(dev);
1596
1597 domain = domain_for_device(dev);
1598
1599 /* allocate a protection domain if a device is added */
1600 dma_domain = find_protection_domain(devid);
1601 if (dma_domain)
1602 goto out;
1603 dma_domain = dma_ops_domain_alloc();
1604 if (!dma_domain)
1605 goto out;
1606 dma_domain->target_dev = devid;
1607
1608 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1609 list_add_tail(&dma_domain->list, &iommu_pd_list);
1610 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1611
1612 break;
1613 case BUS_NOTIFY_DEL_DEVICE:
1614
1615 iommu_uninit_device(dev);
1616
1617 default:
1618 goto out;
1619 }
1620
1621 iommu_flush_device(dev);
1622 iommu_completion_wait(iommu);
1623
1624 out:
1625 return 0;
1626 }
1627
1628 static struct notifier_block device_nb = {
1629 .notifier_call = device_change_notifier,
1630 };
1631
1632 void amd_iommu_init_notifier(void)
1633 {
1634 bus_register_notifier(&pci_bus_type, &device_nb);
1635 }
1636
1637 /*****************************************************************************
1638 *
1639 * The next functions belong to the dma_ops mapping/unmapping code.
1640 *
1641 *****************************************************************************/
1642
1643 /*
1644 * In the dma_ops path we only have the struct device. This function
1645 * finds the corresponding IOMMU, the protection domain and the
1646 * requestor id for a given device.
1647 * If the device is not yet associated with a domain this is also done
1648 * in this function.
1649 */
1650 static struct protection_domain *get_domain(struct device *dev)
1651 {
1652 struct protection_domain *domain;
1653 struct dma_ops_domain *dma_dom;
1654 u16 devid = get_device_id(dev);
1655
1656 if (!check_device(dev))
1657 return ERR_PTR(-EINVAL);
1658
1659 domain = domain_for_device(dev);
1660 if (domain != NULL && !dma_ops_domain(domain))
1661 return ERR_PTR(-EBUSY);
1662
1663 if (domain != NULL)
1664 return domain;
1665
1666 /* Device not bount yet - bind it */
1667 dma_dom = find_protection_domain(devid);
1668 if (!dma_dom)
1669 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1670 attach_device(dev, &dma_dom->domain);
1671 DUMP_printk("Using protection domain %d for device %s\n",
1672 dma_dom->domain.id, dev_name(dev));
1673
1674 return &dma_dom->domain;
1675 }
1676
1677 static void update_device_table(struct protection_domain *domain)
1678 {
1679 struct iommu_dev_data *dev_data;
1680
1681 list_for_each_entry(dev_data, &domain->dev_list, list) {
1682 u16 devid = get_device_id(dev_data->dev);
1683 set_dte_entry(devid, domain);
1684 }
1685 }
1686
1687 static void update_domain(struct protection_domain *domain)
1688 {
1689 if (!domain->updated)
1690 return;
1691
1692 update_device_table(domain);
1693 iommu_flush_domain_devices(domain);
1694 iommu_flush_tlb_pde(domain);
1695
1696 domain->updated = false;
1697 }
1698
1699 /*
1700 * This function fetches the PTE for a given address in the aperture
1701 */
1702 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1703 unsigned long address)
1704 {
1705 struct aperture_range *aperture;
1706 u64 *pte, *pte_page;
1707
1708 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1709 if (!aperture)
1710 return NULL;
1711
1712 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1713 if (!pte) {
1714 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1715 GFP_ATOMIC);
1716 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1717 } else
1718 pte += PM_LEVEL_INDEX(0, address);
1719
1720 update_domain(&dom->domain);
1721
1722 return pte;
1723 }
1724
1725 /*
1726 * This is the generic map function. It maps one 4kb page at paddr to
1727 * the given address in the DMA address space for the domain.
1728 */
1729 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1730 unsigned long address,
1731 phys_addr_t paddr,
1732 int direction)
1733 {
1734 u64 *pte, __pte;
1735
1736 WARN_ON(address > dom->aperture_size);
1737
1738 paddr &= PAGE_MASK;
1739
1740 pte = dma_ops_get_pte(dom, address);
1741 if (!pte)
1742 return DMA_ERROR_CODE;
1743
1744 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1745
1746 if (direction == DMA_TO_DEVICE)
1747 __pte |= IOMMU_PTE_IR;
1748 else if (direction == DMA_FROM_DEVICE)
1749 __pte |= IOMMU_PTE_IW;
1750 else if (direction == DMA_BIDIRECTIONAL)
1751 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1752
1753 WARN_ON(*pte);
1754
1755 *pte = __pte;
1756
1757 return (dma_addr_t)address;
1758 }
1759
1760 /*
1761 * The generic unmapping function for on page in the DMA address space.
1762 */
1763 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1764 unsigned long address)
1765 {
1766 struct aperture_range *aperture;
1767 u64 *pte;
1768
1769 if (address >= dom->aperture_size)
1770 return;
1771
1772 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1773 if (!aperture)
1774 return;
1775
1776 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1777 if (!pte)
1778 return;
1779
1780 pte += PM_LEVEL_INDEX(0, address);
1781
1782 WARN_ON(!*pte);
1783
1784 *pte = 0ULL;
1785 }
1786
1787 /*
1788 * This function contains common code for mapping of a physically
1789 * contiguous memory region into DMA address space. It is used by all
1790 * mapping functions provided with this IOMMU driver.
1791 * Must be called with the domain lock held.
1792 */
1793 static dma_addr_t __map_single(struct device *dev,
1794 struct dma_ops_domain *dma_dom,
1795 phys_addr_t paddr,
1796 size_t size,
1797 int dir,
1798 bool align,
1799 u64 dma_mask)
1800 {
1801 dma_addr_t offset = paddr & ~PAGE_MASK;
1802 dma_addr_t address, start, ret;
1803 unsigned int pages;
1804 unsigned long align_mask = 0;
1805 int i;
1806
1807 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1808 paddr &= PAGE_MASK;
1809
1810 INC_STATS_COUNTER(total_map_requests);
1811
1812 if (pages > 1)
1813 INC_STATS_COUNTER(cross_page);
1814
1815 if (align)
1816 align_mask = (1UL << get_order(size)) - 1;
1817
1818 retry:
1819 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1820 dma_mask);
1821 if (unlikely(address == DMA_ERROR_CODE)) {
1822 /*
1823 * setting next_address here will let the address
1824 * allocator only scan the new allocated range in the
1825 * first run. This is a small optimization.
1826 */
1827 dma_dom->next_address = dma_dom->aperture_size;
1828
1829 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1830 goto out;
1831
1832 /*
1833 * aperture was successfully enlarged by 128 MB, try
1834 * allocation again
1835 */
1836 goto retry;
1837 }
1838
1839 start = address;
1840 for (i = 0; i < pages; ++i) {
1841 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1842 if (ret == DMA_ERROR_CODE)
1843 goto out_unmap;
1844
1845 paddr += PAGE_SIZE;
1846 start += PAGE_SIZE;
1847 }
1848 address += offset;
1849
1850 ADD_STATS_COUNTER(alloced_io_mem, size);
1851
1852 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1853 iommu_flush_tlb(&dma_dom->domain);
1854 dma_dom->need_flush = false;
1855 } else if (unlikely(amd_iommu_np_cache))
1856 iommu_flush_pages(&dma_dom->domain, address, size);
1857
1858 out:
1859 return address;
1860
1861 out_unmap:
1862
1863 for (--i; i >= 0; --i) {
1864 start -= PAGE_SIZE;
1865 dma_ops_domain_unmap(dma_dom, start);
1866 }
1867
1868 dma_ops_free_addresses(dma_dom, address, pages);
1869
1870 return DMA_ERROR_CODE;
1871 }
1872
1873 /*
1874 * Does the reverse of the __map_single function. Must be called with
1875 * the domain lock held too
1876 */
1877 static void __unmap_single(struct dma_ops_domain *dma_dom,
1878 dma_addr_t dma_addr,
1879 size_t size,
1880 int dir)
1881 {
1882 dma_addr_t i, start;
1883 unsigned int pages;
1884
1885 if ((dma_addr == DMA_ERROR_CODE) ||
1886 (dma_addr + size > dma_dom->aperture_size))
1887 return;
1888
1889 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1890 dma_addr &= PAGE_MASK;
1891 start = dma_addr;
1892
1893 for (i = 0; i < pages; ++i) {
1894 dma_ops_domain_unmap(dma_dom, start);
1895 start += PAGE_SIZE;
1896 }
1897
1898 SUB_STATS_COUNTER(alloced_io_mem, size);
1899
1900 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1901
1902 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1903 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1904 dma_dom->need_flush = false;
1905 }
1906 }
1907
1908 /*
1909 * The exported map_single function for dma_ops.
1910 */
1911 static dma_addr_t map_page(struct device *dev, struct page *page,
1912 unsigned long offset, size_t size,
1913 enum dma_data_direction dir,
1914 struct dma_attrs *attrs)
1915 {
1916 unsigned long flags;
1917 struct protection_domain *domain;
1918 dma_addr_t addr;
1919 u64 dma_mask;
1920 phys_addr_t paddr = page_to_phys(page) + offset;
1921
1922 INC_STATS_COUNTER(cnt_map_single);
1923
1924 domain = get_domain(dev);
1925 if (PTR_ERR(domain) == -EINVAL)
1926 return (dma_addr_t)paddr;
1927 else if (IS_ERR(domain))
1928 return DMA_ERROR_CODE;
1929
1930 dma_mask = *dev->dma_mask;
1931
1932 spin_lock_irqsave(&domain->lock, flags);
1933
1934 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1935 dma_mask);
1936 if (addr == DMA_ERROR_CODE)
1937 goto out;
1938
1939 iommu_flush_complete(domain);
1940
1941 out:
1942 spin_unlock_irqrestore(&domain->lock, flags);
1943
1944 return addr;
1945 }
1946
1947 /*
1948 * The exported unmap_single function for dma_ops.
1949 */
1950 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1951 enum dma_data_direction dir, struct dma_attrs *attrs)
1952 {
1953 unsigned long flags;
1954 struct protection_domain *domain;
1955
1956 INC_STATS_COUNTER(cnt_unmap_single);
1957
1958 domain = get_domain(dev);
1959 if (IS_ERR(domain))
1960 return;
1961
1962 spin_lock_irqsave(&domain->lock, flags);
1963
1964 __unmap_single(domain->priv, dma_addr, size, dir);
1965
1966 iommu_flush_complete(domain);
1967
1968 spin_unlock_irqrestore(&domain->lock, flags);
1969 }
1970
1971 /*
1972 * This is a special map_sg function which is used if we should map a
1973 * device which is not handled by an AMD IOMMU in the system.
1974 */
1975 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1976 int nelems, int dir)
1977 {
1978 struct scatterlist *s;
1979 int i;
1980
1981 for_each_sg(sglist, s, nelems, i) {
1982 s->dma_address = (dma_addr_t)sg_phys(s);
1983 s->dma_length = s->length;
1984 }
1985
1986 return nelems;
1987 }
1988
1989 /*
1990 * The exported map_sg function for dma_ops (handles scatter-gather
1991 * lists).
1992 */
1993 static int map_sg(struct device *dev, struct scatterlist *sglist,
1994 int nelems, enum dma_data_direction dir,
1995 struct dma_attrs *attrs)
1996 {
1997 unsigned long flags;
1998 struct protection_domain *domain;
1999 int i;
2000 struct scatterlist *s;
2001 phys_addr_t paddr;
2002 int mapped_elems = 0;
2003 u64 dma_mask;
2004
2005 INC_STATS_COUNTER(cnt_map_sg);
2006
2007 domain = get_domain(dev);
2008 if (PTR_ERR(domain) == -EINVAL)
2009 return map_sg_no_iommu(dev, sglist, nelems, dir);
2010 else if (IS_ERR(domain))
2011 return 0;
2012
2013 dma_mask = *dev->dma_mask;
2014
2015 spin_lock_irqsave(&domain->lock, flags);
2016
2017 for_each_sg(sglist, s, nelems, i) {
2018 paddr = sg_phys(s);
2019
2020 s->dma_address = __map_single(dev, domain->priv,
2021 paddr, s->length, dir, false,
2022 dma_mask);
2023
2024 if (s->dma_address) {
2025 s->dma_length = s->length;
2026 mapped_elems++;
2027 } else
2028 goto unmap;
2029 }
2030
2031 iommu_flush_complete(domain);
2032
2033 out:
2034 spin_unlock_irqrestore(&domain->lock, flags);
2035
2036 return mapped_elems;
2037 unmap:
2038 for_each_sg(sglist, s, mapped_elems, i) {
2039 if (s->dma_address)
2040 __unmap_single(domain->priv, s->dma_address,
2041 s->dma_length, dir);
2042 s->dma_address = s->dma_length = 0;
2043 }
2044
2045 mapped_elems = 0;
2046
2047 goto out;
2048 }
2049
2050 /*
2051 * The exported map_sg function for dma_ops (handles scatter-gather
2052 * lists).
2053 */
2054 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2055 int nelems, enum dma_data_direction dir,
2056 struct dma_attrs *attrs)
2057 {
2058 unsigned long flags;
2059 struct protection_domain *domain;
2060 struct scatterlist *s;
2061 int i;
2062
2063 INC_STATS_COUNTER(cnt_unmap_sg);
2064
2065 domain = get_domain(dev);
2066 if (IS_ERR(domain))
2067 return;
2068
2069 spin_lock_irqsave(&domain->lock, flags);
2070
2071 for_each_sg(sglist, s, nelems, i) {
2072 __unmap_single(domain->priv, s->dma_address,
2073 s->dma_length, dir);
2074 s->dma_address = s->dma_length = 0;
2075 }
2076
2077 iommu_flush_complete(domain);
2078
2079 spin_unlock_irqrestore(&domain->lock, flags);
2080 }
2081
2082 /*
2083 * The exported alloc_coherent function for dma_ops.
2084 */
2085 static void *alloc_coherent(struct device *dev, size_t size,
2086 dma_addr_t *dma_addr, gfp_t flag)
2087 {
2088 unsigned long flags;
2089 void *virt_addr;
2090 struct protection_domain *domain;
2091 phys_addr_t paddr;
2092 u64 dma_mask = dev->coherent_dma_mask;
2093
2094 INC_STATS_COUNTER(cnt_alloc_coherent);
2095
2096 domain = get_domain(dev);
2097 if (PTR_ERR(domain) == -EINVAL) {
2098 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2099 *dma_addr = __pa(virt_addr);
2100 return virt_addr;
2101 } else if (IS_ERR(domain))
2102 return NULL;
2103
2104 dma_mask = dev->coherent_dma_mask;
2105 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2106 flag |= __GFP_ZERO;
2107
2108 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2109 if (!virt_addr)
2110 return NULL;
2111
2112 paddr = virt_to_phys(virt_addr);
2113
2114 if (!dma_mask)
2115 dma_mask = *dev->dma_mask;
2116
2117 spin_lock_irqsave(&domain->lock, flags);
2118
2119 *dma_addr = __map_single(dev, domain->priv, paddr,
2120 size, DMA_BIDIRECTIONAL, true, dma_mask);
2121
2122 if (*dma_addr == DMA_ERROR_CODE) {
2123 spin_unlock_irqrestore(&domain->lock, flags);
2124 goto out_free;
2125 }
2126
2127 iommu_flush_complete(domain);
2128
2129 spin_unlock_irqrestore(&domain->lock, flags);
2130
2131 return virt_addr;
2132
2133 out_free:
2134
2135 free_pages((unsigned long)virt_addr, get_order(size));
2136
2137 return NULL;
2138 }
2139
2140 /*
2141 * The exported free_coherent function for dma_ops.
2142 */
2143 static void free_coherent(struct device *dev, size_t size,
2144 void *virt_addr, dma_addr_t dma_addr)
2145 {
2146 unsigned long flags;
2147 struct protection_domain *domain;
2148
2149 INC_STATS_COUNTER(cnt_free_coherent);
2150
2151 domain = get_domain(dev);
2152 if (IS_ERR(domain))
2153 goto free_mem;
2154
2155 spin_lock_irqsave(&domain->lock, flags);
2156
2157 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2158
2159 iommu_flush_complete(domain);
2160
2161 spin_unlock_irqrestore(&domain->lock, flags);
2162
2163 free_mem:
2164 free_pages((unsigned long)virt_addr, get_order(size));
2165 }
2166
2167 /*
2168 * This function is called by the DMA layer to find out if we can handle a
2169 * particular device. It is part of the dma_ops.
2170 */
2171 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2172 {
2173 return check_device(dev);
2174 }
2175
2176 /*
2177 * The function for pre-allocating protection domains.
2178 *
2179 * If the driver core informs the DMA layer if a driver grabs a device
2180 * we don't need to preallocate the protection domains anymore.
2181 * For now we have to.
2182 */
2183 static void prealloc_protection_domains(void)
2184 {
2185 struct pci_dev *dev = NULL;
2186 struct dma_ops_domain *dma_dom;
2187 u16 devid;
2188
2189 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2190
2191 /* Do we handle this device? */
2192 if (!check_device(&dev->dev))
2193 continue;
2194
2195 /* Is there already any domain for it? */
2196 if (domain_for_device(&dev->dev))
2197 continue;
2198
2199 devid = get_device_id(&dev->dev);
2200
2201 dma_dom = dma_ops_domain_alloc();
2202 if (!dma_dom)
2203 continue;
2204 init_unity_mappings_for_device(dma_dom, devid);
2205 dma_dom->target_dev = devid;
2206
2207 attach_device(&dev->dev, &dma_dom->domain);
2208
2209 list_add_tail(&dma_dom->list, &iommu_pd_list);
2210 }
2211 }
2212
2213 static struct dma_map_ops amd_iommu_dma_ops = {
2214 .alloc_coherent = alloc_coherent,
2215 .free_coherent = free_coherent,
2216 .map_page = map_page,
2217 .unmap_page = unmap_page,
2218 .map_sg = map_sg,
2219 .unmap_sg = unmap_sg,
2220 .dma_supported = amd_iommu_dma_supported,
2221 };
2222
2223 /*
2224 * The function which clues the AMD IOMMU driver into dma_ops.
2225 */
2226
2227 void __init amd_iommu_init_api(void)
2228 {
2229 register_iommu(&amd_iommu_ops);
2230 }
2231
2232 int __init amd_iommu_init_dma_ops(void)
2233 {
2234 struct amd_iommu *iommu;
2235 int ret;
2236
2237 /*
2238 * first allocate a default protection domain for every IOMMU we
2239 * found in the system. Devices not assigned to any other
2240 * protection domain will be assigned to the default one.
2241 */
2242 for_each_iommu(iommu) {
2243 iommu->default_dom = dma_ops_domain_alloc();
2244 if (iommu->default_dom == NULL)
2245 return -ENOMEM;
2246 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2247 ret = iommu_init_unity_mappings(iommu);
2248 if (ret)
2249 goto free_domains;
2250 }
2251
2252 /*
2253 * Pre-allocate the protection domains for each device.
2254 */
2255 prealloc_protection_domains();
2256
2257 iommu_detected = 1;
2258 swiotlb = 0;
2259 #ifdef CONFIG_GART_IOMMU
2260 gart_iommu_aperture_disabled = 1;
2261 gart_iommu_aperture = 0;
2262 #endif
2263
2264 /* Make the driver finally visible to the drivers */
2265 dma_ops = &amd_iommu_dma_ops;
2266
2267 amd_iommu_stats_init();
2268
2269 return 0;
2270
2271 free_domains:
2272
2273 for_each_iommu(iommu) {
2274 if (iommu->default_dom)
2275 dma_ops_domain_free(iommu->default_dom);
2276 }
2277
2278 return ret;
2279 }
2280
2281 /*****************************************************************************
2282 *
2283 * The following functions belong to the exported interface of AMD IOMMU
2284 *
2285 * This interface allows access to lower level functions of the IOMMU
2286 * like protection domain handling and assignement of devices to domains
2287 * which is not possible with the dma_ops interface.
2288 *
2289 *****************************************************************************/
2290
2291 static void cleanup_domain(struct protection_domain *domain)
2292 {
2293 struct iommu_dev_data *dev_data, *next;
2294 unsigned long flags;
2295
2296 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2297
2298 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2299 struct device *dev = dev_data->dev;
2300
2301 do_detach(dev);
2302 atomic_set(&dev_data->bind, 0);
2303 }
2304
2305 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2306 }
2307
2308 static void protection_domain_free(struct protection_domain *domain)
2309 {
2310 if (!domain)
2311 return;
2312
2313 del_domain_from_list(domain);
2314
2315 if (domain->id)
2316 domain_id_free(domain->id);
2317
2318 kfree(domain);
2319 }
2320
2321 static struct protection_domain *protection_domain_alloc(void)
2322 {
2323 struct protection_domain *domain;
2324
2325 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2326 if (!domain)
2327 return NULL;
2328
2329 spin_lock_init(&domain->lock);
2330 domain->id = domain_id_alloc();
2331 if (!domain->id)
2332 goto out_err;
2333 INIT_LIST_HEAD(&domain->dev_list);
2334
2335 add_domain_to_list(domain);
2336
2337 return domain;
2338
2339 out_err:
2340 kfree(domain);
2341
2342 return NULL;
2343 }
2344
2345 static int amd_iommu_domain_init(struct iommu_domain *dom)
2346 {
2347 struct protection_domain *domain;
2348
2349 domain = protection_domain_alloc();
2350 if (!domain)
2351 goto out_free;
2352
2353 domain->mode = PAGE_MODE_3_LEVEL;
2354 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2355 if (!domain->pt_root)
2356 goto out_free;
2357
2358 dom->priv = domain;
2359
2360 return 0;
2361
2362 out_free:
2363 protection_domain_free(domain);
2364
2365 return -ENOMEM;
2366 }
2367
2368 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2369 {
2370 struct protection_domain *domain = dom->priv;
2371
2372 if (!domain)
2373 return;
2374
2375 if (domain->dev_cnt > 0)
2376 cleanup_domain(domain);
2377
2378 BUG_ON(domain->dev_cnt != 0);
2379
2380 free_pagetable(domain);
2381
2382 domain_id_free(domain->id);
2383
2384 kfree(domain);
2385
2386 dom->priv = NULL;
2387 }
2388
2389 static void amd_iommu_detach_device(struct iommu_domain *dom,
2390 struct device *dev)
2391 {
2392 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2393 struct amd_iommu *iommu;
2394 u16 devid;
2395
2396 if (!check_device(dev))
2397 return;
2398
2399 devid = get_device_id(dev);
2400
2401 if (dev_data->domain != NULL)
2402 detach_device(dev);
2403
2404 iommu = amd_iommu_rlookup_table[devid];
2405 if (!iommu)
2406 return;
2407
2408 iommu_flush_device(dev);
2409 iommu_completion_wait(iommu);
2410 }
2411
2412 static int amd_iommu_attach_device(struct iommu_domain *dom,
2413 struct device *dev)
2414 {
2415 struct protection_domain *domain = dom->priv;
2416 struct iommu_dev_data *dev_data;
2417 struct amd_iommu *iommu;
2418 int ret;
2419 u16 devid;
2420
2421 if (!check_device(dev))
2422 return -EINVAL;
2423
2424 dev_data = dev->archdata.iommu;
2425
2426 devid = get_device_id(dev);
2427
2428 iommu = amd_iommu_rlookup_table[devid];
2429 if (!iommu)
2430 return -EINVAL;
2431
2432 if (dev_data->domain)
2433 detach_device(dev);
2434
2435 ret = attach_device(dev, domain);
2436
2437 iommu_completion_wait(iommu);
2438
2439 return ret;
2440 }
2441
2442 static int amd_iommu_map_range(struct iommu_domain *dom,
2443 unsigned long iova, phys_addr_t paddr,
2444 size_t size, int iommu_prot)
2445 {
2446 struct protection_domain *domain = dom->priv;
2447 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2448 int prot = 0;
2449 int ret;
2450
2451 if (iommu_prot & IOMMU_READ)
2452 prot |= IOMMU_PROT_IR;
2453 if (iommu_prot & IOMMU_WRITE)
2454 prot |= IOMMU_PROT_IW;
2455
2456 iova &= PAGE_MASK;
2457 paddr &= PAGE_MASK;
2458
2459 for (i = 0; i < npages; ++i) {
2460 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2461 if (ret)
2462 return ret;
2463
2464 iova += PAGE_SIZE;
2465 paddr += PAGE_SIZE;
2466 }
2467
2468 return 0;
2469 }
2470
2471 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2472 unsigned long iova, size_t size)
2473 {
2474
2475 struct protection_domain *domain = dom->priv;
2476 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2477
2478 iova &= PAGE_MASK;
2479
2480 for (i = 0; i < npages; ++i) {
2481 iommu_unmap_page(domain, iova, PM_MAP_4k);
2482 iova += PAGE_SIZE;
2483 }
2484
2485 iommu_flush_tlb_pde(domain);
2486 }
2487
2488 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2489 unsigned long iova)
2490 {
2491 struct protection_domain *domain = dom->priv;
2492 unsigned long offset = iova & ~PAGE_MASK;
2493 phys_addr_t paddr;
2494 u64 *pte;
2495
2496 pte = fetch_pte(domain, iova, PM_MAP_4k);
2497
2498 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2499 return 0;
2500
2501 paddr = *pte & IOMMU_PAGE_MASK;
2502 paddr |= offset;
2503
2504 return paddr;
2505 }
2506
2507 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2508 unsigned long cap)
2509 {
2510 return 0;
2511 }
2512
2513 static struct iommu_ops amd_iommu_ops = {
2514 .domain_init = amd_iommu_domain_init,
2515 .domain_destroy = amd_iommu_domain_destroy,
2516 .attach_dev = amd_iommu_attach_device,
2517 .detach_dev = amd_iommu_detach_device,
2518 .map = amd_iommu_map_range,
2519 .unmap = amd_iommu_unmap_range,
2520 .iova_to_phys = amd_iommu_iova_to_phys,
2521 .domain_has_cap = amd_iommu_domain_has_cap,
2522 };
2523
2524 /*****************************************************************************
2525 *
2526 * The next functions do a basic initialization of IOMMU for pass through
2527 * mode
2528 *
2529 * In passthrough mode the IOMMU is initialized and enabled but not used for
2530 * DMA-API translation.
2531 *
2532 *****************************************************************************/
2533
2534 int __init amd_iommu_init_passthrough(void)
2535 {
2536 struct amd_iommu *iommu;
2537 struct pci_dev *dev = NULL;
2538 u16 devid;
2539
2540 /* allocate passthrough domain */
2541 pt_domain = protection_domain_alloc();
2542 if (!pt_domain)
2543 return -ENOMEM;
2544
2545 pt_domain->mode |= PAGE_MODE_NONE;
2546
2547 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2548
2549 if (!check_device(&dev->dev))
2550 continue;
2551
2552 devid = get_device_id(&dev->dev);
2553
2554 iommu = amd_iommu_rlookup_table[devid];
2555 if (!iommu)
2556 continue;
2557
2558 attach_device(&dev->dev, pt_domain);
2559 }
2560
2561 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2562
2563 return 0;
2564 }
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