2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
33 static u64 perf_event_mask __read_mostly
;
35 /* The maximal number of PEBS events: */
36 #define MAX_PEBS_EVENTS 4
38 /* The size of a BTS record in bytes: */
39 #define BTS_RECORD_SIZE 24
41 /* The size of a per-cpu BTS buffer in bytes: */
42 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
44 /* The BTS overflow threshold in bytes from the end of the buffer: */
45 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
49 * Bits in the debugctlmsr controlling branch tracing.
51 #define X86_DEBUGCTL_TR (1 << 6)
52 #define X86_DEBUGCTL_BTS (1 << 7)
53 #define X86_DEBUGCTL_BTINT (1 << 8)
54 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
55 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
58 * A debug store configuration.
60 * We only support architectures that use 64bit fields.
65 u64 bts_absolute_maximum
;
66 u64 bts_interrupt_threshold
;
69 u64 pebs_absolute_maximum
;
70 u64 pebs_interrupt_threshold
;
71 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
74 struct event_constraint
{
76 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
85 int nb_id
; /* NorthBridge id */
86 int refcnt
; /* reference count */
87 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
88 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
91 struct cpu_hw_events
{
92 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
93 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
94 unsigned long interrupts
;
96 struct debug_store
*ds
;
100 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
101 u64 tags
[X86_PMC_IDX_MAX
];
102 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
103 struct amd_nb
*amd_nb
;
106 #define __EVENT_CONSTRAINT(c, n, m, w) {\
107 { .idxmsk64 = (n) }, \
113 #define EVENT_CONSTRAINT(c, n, m) \
114 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
116 #define INTEL_EVENT_CONSTRAINT(c, n) \
117 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
119 #define FIXED_EVENT_CONSTRAINT(c, n) \
120 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
122 #define EVENT_CONSTRAINT_END \
123 EVENT_CONSTRAINT(0, 0, 0)
125 #define for_each_event_constraint(e, c) \
126 for ((e) = (c); (e)->cmask; (e)++)
129 * struct x86_pmu - generic x86 pmu
134 int (*handle_irq
)(struct pt_regs
*);
135 void (*disable_all
)(void);
136 void (*enable_all
)(void);
137 void (*enable
)(struct perf_event
*);
138 void (*disable
)(struct perf_event
*);
141 u64 (*event_map
)(int);
142 u64 (*raw_event
)(u64
);
145 int num_events_fixed
;
151 void (*enable_bts
)(u64 config
);
152 void (*disable_bts
)(void);
154 struct event_constraint
*
155 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
156 struct perf_event
*event
);
158 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
159 struct perf_event
*event
);
160 struct event_constraint
*event_constraints
;
162 void (*cpu_prepare
)(int cpu
);
163 void (*cpu_starting
)(int cpu
);
164 void (*cpu_dying
)(int cpu
);
165 void (*cpu_dead
)(int cpu
);
168 static struct x86_pmu x86_pmu __read_mostly
;
170 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
174 static int x86_perf_event_set_period(struct perf_event
*event
);
177 * Generalized hw caching related hw_event table, filled
178 * in on a per model basis. A value of 0 means
179 * 'not supported', -1 means 'hw_event makes no sense on
180 * this CPU', any other value means the raw hw_event
184 #define C(x) PERF_COUNT_HW_CACHE_##x
186 static u64 __read_mostly hw_cache_event_ids
187 [PERF_COUNT_HW_CACHE_MAX
]
188 [PERF_COUNT_HW_CACHE_OP_MAX
]
189 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
192 * Propagate event elapsed time into the generic event.
193 * Can only be executed on the CPU where the event is active.
194 * Returns the delta events processed.
197 x86_perf_event_update(struct perf_event
*event
)
199 struct hw_perf_event
*hwc
= &event
->hw
;
200 int shift
= 64 - x86_pmu
.event_bits
;
201 u64 prev_raw_count
, new_raw_count
;
205 if (idx
== X86_PMC_IDX_FIXED_BTS
)
209 * Careful: an NMI might modify the previous event value.
211 * Our tactic to handle this is to first atomically read and
212 * exchange a new raw count - then add that new-prev delta
213 * count to the generic event atomically:
216 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
217 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
219 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
220 new_raw_count
) != prev_raw_count
)
224 * Now we have the new raw value and have updated the prev
225 * timestamp already. We can now calculate the elapsed delta
226 * (event-)time and add that to the generic event.
228 * Careful, not all hw sign-extends above the physical width
231 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
234 atomic64_add(delta
, &event
->count
);
235 atomic64_sub(delta
, &hwc
->period_left
);
237 return new_raw_count
;
240 static atomic_t active_events
;
241 static DEFINE_MUTEX(pmc_reserve_mutex
);
243 static bool reserve_pmc_hardware(void)
245 #ifdef CONFIG_X86_LOCAL_APIC
248 if (nmi_watchdog
== NMI_LOCAL_APIC
)
249 disable_lapic_nmi_watchdog();
251 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
252 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
256 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
257 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
264 #ifdef CONFIG_X86_LOCAL_APIC
266 for (i
--; i
>= 0; i
--)
267 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
269 i
= x86_pmu
.num_events
;
272 for (i
--; i
>= 0; i
--)
273 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
275 if (nmi_watchdog
== NMI_LOCAL_APIC
)
276 enable_lapic_nmi_watchdog();
282 static void release_pmc_hardware(void)
284 #ifdef CONFIG_X86_LOCAL_APIC
287 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
288 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
289 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
292 if (nmi_watchdog
== NMI_LOCAL_APIC
)
293 enable_lapic_nmi_watchdog();
297 static inline bool bts_available(void)
299 return x86_pmu
.enable_bts
!= NULL
;
302 static void init_debug_store_on_cpu(int cpu
)
304 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
309 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
,
310 (u32
)((u64
)(unsigned long)ds
),
311 (u32
)((u64
)(unsigned long)ds
>> 32));
314 static void fini_debug_store_on_cpu(int cpu
)
316 if (!per_cpu(cpu_hw_events
, cpu
).ds
)
319 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
, 0, 0);
322 static void release_bts_hardware(void)
326 if (!bts_available())
331 for_each_online_cpu(cpu
)
332 fini_debug_store_on_cpu(cpu
);
334 for_each_possible_cpu(cpu
) {
335 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
340 per_cpu(cpu_hw_events
, cpu
).ds
= NULL
;
342 kfree((void *)(unsigned long)ds
->bts_buffer_base
);
349 static int reserve_bts_hardware(void)
353 if (!bts_available())
358 for_each_possible_cpu(cpu
) {
359 struct debug_store
*ds
;
363 buffer
= kzalloc(BTS_BUFFER_SIZE
, GFP_KERNEL
);
364 if (unlikely(!buffer
))
367 ds
= kzalloc(sizeof(*ds
), GFP_KERNEL
);
373 ds
->bts_buffer_base
= (u64
)(unsigned long)buffer
;
374 ds
->bts_index
= ds
->bts_buffer_base
;
375 ds
->bts_absolute_maximum
=
376 ds
->bts_buffer_base
+ BTS_BUFFER_SIZE
;
377 ds
->bts_interrupt_threshold
=
378 ds
->bts_absolute_maximum
- BTS_OVFL_TH
;
380 per_cpu(cpu_hw_events
, cpu
).ds
= ds
;
385 release_bts_hardware();
387 for_each_online_cpu(cpu
)
388 init_debug_store_on_cpu(cpu
);
396 static void hw_perf_event_destroy(struct perf_event
*event
)
398 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
399 release_pmc_hardware();
400 release_bts_hardware();
401 mutex_unlock(&pmc_reserve_mutex
);
405 static inline int x86_pmu_initialized(void)
407 return x86_pmu
.handle_irq
!= NULL
;
411 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
413 unsigned int cache_type
, cache_op
, cache_result
;
416 config
= attr
->config
;
418 cache_type
= (config
>> 0) & 0xff;
419 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
422 cache_op
= (config
>> 8) & 0xff;
423 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
426 cache_result
= (config
>> 16) & 0xff;
427 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
430 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
444 * Setup the hardware configuration for a given attr_type
446 static int __hw_perf_event_init(struct perf_event
*event
)
448 struct perf_event_attr
*attr
= &event
->attr
;
449 struct hw_perf_event
*hwc
= &event
->hw
;
453 if (!x86_pmu_initialized())
457 if (!atomic_inc_not_zero(&active_events
)) {
458 mutex_lock(&pmc_reserve_mutex
);
459 if (atomic_read(&active_events
) == 0) {
460 if (!reserve_pmc_hardware())
463 err
= reserve_bts_hardware();
466 atomic_inc(&active_events
);
467 mutex_unlock(&pmc_reserve_mutex
);
472 event
->destroy
= hw_perf_event_destroy
;
476 * (keep 'enabled' bit clear for now)
478 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
482 hwc
->last_tag
= ~0ULL;
485 * Count user and OS events unless requested not to.
487 if (!attr
->exclude_user
)
488 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
489 if (!attr
->exclude_kernel
)
490 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
492 if (!hwc
->sample_period
) {
493 hwc
->sample_period
= x86_pmu
.max_period
;
494 hwc
->last_period
= hwc
->sample_period
;
495 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
498 * If we have a PMU initialized but no APIC
499 * interrupts, we cannot sample hardware
500 * events (user-space has to fall back and
501 * sample via a hrtimer based software event):
508 * Raw hw_event type provide the config in the hw_event structure
510 if (attr
->type
== PERF_TYPE_RAW
) {
511 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
512 if ((hwc
->config
& ARCH_PERFMON_EVENTSEL_ANY
) &&
513 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN
))
518 if (attr
->type
== PERF_TYPE_HW_CACHE
)
519 return set_ext_hw_attr(hwc
, attr
);
521 if (attr
->config
>= x86_pmu
.max_events
)
527 config
= x86_pmu
.event_map(attr
->config
);
538 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
539 (hwc
->sample_period
== 1)) {
540 /* BTS is not supported by this architecture. */
541 if (!bts_available())
544 /* BTS is currently only allowed for user-mode. */
545 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
549 hwc
->config
|= config
;
554 static void x86_pmu_disable_all(void)
556 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
559 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
562 if (!test_bit(idx
, cpuc
->active_mask
))
564 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
565 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
567 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
568 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
572 void hw_perf_disable(void)
574 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
576 if (!x86_pmu_initialized())
586 x86_pmu
.disable_all();
589 static void x86_pmu_enable_all(void)
591 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
594 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
595 struct perf_event
*event
= cpuc
->events
[idx
];
598 if (!test_bit(idx
, cpuc
->active_mask
))
601 val
= event
->hw
.config
;
602 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
603 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
607 static const struct pmu pmu
;
609 static inline int is_x86_event(struct perf_event
*event
)
611 return event
->pmu
== &pmu
;
614 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
616 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
617 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
618 int i
, j
, w
, wmax
, num
= 0;
619 struct hw_perf_event
*hwc
;
621 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
623 for (i
= 0; i
< n
; i
++) {
624 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
629 * fastpath, try to reuse previous register
631 for (i
= 0; i
< n
; i
++) {
632 hwc
= &cpuc
->event_list
[i
]->hw
;
639 /* constraint still honored */
640 if (!test_bit(hwc
->idx
, c
->idxmsk
))
643 /* not already used */
644 if (test_bit(hwc
->idx
, used_mask
))
647 __set_bit(hwc
->idx
, used_mask
);
649 assign
[i
] = hwc
->idx
;
658 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
661 * weight = number of possible counters
663 * 1 = most constrained, only works on one counter
664 * wmax = least constrained, works on any counter
666 * assign events to counters starting with most
667 * constrained events.
669 wmax
= x86_pmu
.num_events
;
672 * when fixed event counters are present,
673 * wmax is incremented by 1 to account
674 * for one more choice
676 if (x86_pmu
.num_events_fixed
)
679 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
681 for (i
= 0; num
&& i
< n
; i
++) {
683 hwc
= &cpuc
->event_list
[i
]->hw
;
688 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
689 if (!test_bit(j
, used_mask
))
693 if (j
== X86_PMC_IDX_MAX
)
696 __set_bit(j
, used_mask
);
705 * scheduling failed or is just a simulation,
706 * free resources if necessary
708 if (!assign
|| num
) {
709 for (i
= 0; i
< n
; i
++) {
710 if (x86_pmu
.put_event_constraints
)
711 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
714 return num
? -ENOSPC
: 0;
718 * dogrp: true if must collect siblings events (group)
719 * returns total number of events and error code
721 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
723 struct perf_event
*event
;
726 max_count
= x86_pmu
.num_events
+ x86_pmu
.num_events_fixed
;
728 /* current number of events already accepted */
731 if (is_x86_event(leader
)) {
734 cpuc
->event_list
[n
] = leader
;
740 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
741 if (!is_x86_event(event
) ||
742 event
->state
<= PERF_EVENT_STATE_OFF
)
748 cpuc
->event_list
[n
] = event
;
754 static inline void x86_assign_hw_event(struct perf_event
*event
,
755 struct cpu_hw_events
*cpuc
, int i
)
757 struct hw_perf_event
*hwc
= &event
->hw
;
759 hwc
->idx
= cpuc
->assign
[i
];
760 hwc
->last_cpu
= smp_processor_id();
761 hwc
->last_tag
= ++cpuc
->tags
[i
];
763 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
764 hwc
->config_base
= 0;
766 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
767 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
769 * We set it so that event_base + idx in wrmsr/rdmsr maps to
770 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
773 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
775 hwc
->config_base
= x86_pmu
.eventsel
;
776 hwc
->event_base
= x86_pmu
.perfctr
;
780 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
781 struct cpu_hw_events
*cpuc
,
784 return hwc
->idx
== cpuc
->assign
[i
] &&
785 hwc
->last_cpu
== smp_processor_id() &&
786 hwc
->last_tag
== cpuc
->tags
[i
];
789 static int x86_pmu_start(struct perf_event
*event
);
790 static void x86_pmu_stop(struct perf_event
*event
);
792 void hw_perf_enable(void)
794 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
795 struct perf_event
*event
;
796 struct hw_perf_event
*hwc
;
799 if (!x86_pmu_initialized())
806 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
808 * apply assignment obtained either from
809 * hw_perf_group_sched_in() or x86_pmu_enable()
811 * step1: save events moving to new counters
812 * step2: reprogram moved events into new counters
814 for (i
= 0; i
< n_running
; i
++) {
815 event
= cpuc
->event_list
[i
];
819 * we can avoid reprogramming counter if:
820 * - assigned same counter as last time
821 * - running on same CPU as last time
822 * - no other event has used the counter since
824 if (hwc
->idx
== -1 ||
825 match_prev_assignment(hwc
, cpuc
, i
))
831 for (i
= 0; i
< cpuc
->n_events
; i
++) {
832 event
= cpuc
->event_list
[i
];
835 if (!match_prev_assignment(hwc
, cpuc
, i
))
836 x86_assign_hw_event(event
, cpuc
, i
);
837 else if (i
< n_running
)
840 x86_pmu_start(event
);
843 perf_events_lapic_init();
849 x86_pmu
.enable_all();
852 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
)
854 (void)checking_wrmsrl(hwc
->config_base
+ hwc
->idx
,
855 hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
);
858 static inline void x86_pmu_disable_event(struct perf_event
*event
)
860 struct hw_perf_event
*hwc
= &event
->hw
;
861 (void)checking_wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
864 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
867 * Set the next IRQ period, based on the hwc->period_left value.
868 * To be called with the event disabled in hw:
871 x86_perf_event_set_period(struct perf_event
*event
)
873 struct hw_perf_event
*hwc
= &event
->hw
;
874 s64 left
= atomic64_read(&hwc
->period_left
);
875 s64 period
= hwc
->sample_period
;
876 int err
, ret
= 0, idx
= hwc
->idx
;
878 if (idx
== X86_PMC_IDX_FIXED_BTS
)
882 * If we are way outside a reasonable range then just skip forward:
884 if (unlikely(left
<= -period
)) {
886 atomic64_set(&hwc
->period_left
, left
);
887 hwc
->last_period
= period
;
891 if (unlikely(left
<= 0)) {
893 atomic64_set(&hwc
->period_left
, left
);
894 hwc
->last_period
= period
;
898 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
900 if (unlikely(left
< 2))
903 if (left
> x86_pmu
.max_period
)
904 left
= x86_pmu
.max_period
;
906 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
909 * The hw event starts counting from this event offset,
910 * mark it to be able to extra future deltas:
912 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
914 err
= checking_wrmsrl(hwc
->event_base
+ idx
,
915 (u64
)(-left
) & x86_pmu
.event_mask
);
917 perf_event_update_userpage(event
);
922 static void x86_pmu_enable_event(struct perf_event
*event
)
924 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
926 __x86_pmu_enable_event(&event
->hw
);
930 * activate a single event
932 * The event is added to the group of enabled events
933 * but only if it can be scehduled with existing events.
935 * Called with PMU disabled. If successful and return value 1,
936 * then guaranteed to call perf_enable() and hw_perf_enable()
938 static int x86_pmu_enable(struct perf_event
*event
)
940 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
941 struct hw_perf_event
*hwc
;
942 int assign
[X86_PMC_IDX_MAX
];
948 n
= collect_events(cpuc
, event
, false);
952 ret
= x86_schedule_events(cpuc
, n
, assign
);
956 * copy new assignment, now we know it is possible
957 * will be used by hw_perf_enable()
959 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
962 cpuc
->n_added
+= n
- n0
;
967 static int x86_pmu_start(struct perf_event
*event
)
969 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
970 int idx
= event
->hw
.idx
;
975 x86_perf_event_set_period(event
);
976 cpuc
->events
[idx
] = event
;
977 __set_bit(idx
, cpuc
->active_mask
);
978 x86_pmu
.enable(event
);
979 perf_event_update_userpage(event
);
984 static void x86_pmu_unthrottle(struct perf_event
*event
)
986 int ret
= x86_pmu_start(event
);
990 void perf_event_print_debug(void)
992 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
993 struct cpu_hw_events
*cpuc
;
997 if (!x86_pmu
.num_events
)
1000 local_irq_save(flags
);
1002 cpu
= smp_processor_id();
1003 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1005 if (x86_pmu
.version
>= 2) {
1006 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1007 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1008 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1009 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1012 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1013 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1014 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1015 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1017 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1019 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1020 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1021 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1023 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1025 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1026 cpu
, idx
, pmc_ctrl
);
1027 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1028 cpu
, idx
, pmc_count
);
1029 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1030 cpu
, idx
, prev_left
);
1032 for (idx
= 0; idx
< x86_pmu
.num_events_fixed
; idx
++) {
1033 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1035 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1036 cpu
, idx
, pmc_count
);
1038 local_irq_restore(flags
);
1041 static void x86_pmu_stop(struct perf_event
*event
)
1043 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1044 struct hw_perf_event
*hwc
= &event
->hw
;
1047 if (!__test_and_clear_bit(idx
, cpuc
->active_mask
))
1050 x86_pmu
.disable(event
);
1053 * Drain the remaining delta count out of a event
1054 * that we are disabling:
1056 x86_perf_event_update(event
);
1058 cpuc
->events
[idx
] = NULL
;
1061 static void x86_pmu_disable(struct perf_event
*event
)
1063 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1066 x86_pmu_stop(event
);
1068 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1069 if (event
== cpuc
->event_list
[i
]) {
1071 if (x86_pmu
.put_event_constraints
)
1072 x86_pmu
.put_event_constraints(cpuc
, event
);
1074 while (++i
< cpuc
->n_events
)
1075 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1081 perf_event_update_userpage(event
);
1084 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1086 struct perf_sample_data data
;
1087 struct cpu_hw_events
*cpuc
;
1088 struct perf_event
*event
;
1089 struct hw_perf_event
*hwc
;
1090 int idx
, handled
= 0;
1093 perf_sample_data_init(&data
, 0);
1095 cpuc
= &__get_cpu_var(cpu_hw_events
);
1097 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1098 if (!test_bit(idx
, cpuc
->active_mask
))
1101 event
= cpuc
->events
[idx
];
1104 val
= x86_perf_event_update(event
);
1105 if (val
& (1ULL << (x86_pmu
.event_bits
- 1)))
1112 data
.period
= event
->hw
.last_period
;
1114 if (!x86_perf_event_set_period(event
))
1117 if (perf_event_overflow(event
, 1, &data
, regs
))
1118 x86_pmu_stop(event
);
1122 inc_irq_stat(apic_perf_irqs
);
1127 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1131 inc_irq_stat(apic_pending_irqs
);
1132 perf_event_do_pending();
1136 void set_perf_event_pending(void)
1138 #ifdef CONFIG_X86_LOCAL_APIC
1139 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1142 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1146 void perf_events_lapic_init(void)
1148 #ifdef CONFIG_X86_LOCAL_APIC
1149 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1153 * Always use NMI for PMU
1155 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1159 static int __kprobes
1160 perf_event_nmi_handler(struct notifier_block
*self
,
1161 unsigned long cmd
, void *__args
)
1163 struct die_args
*args
= __args
;
1164 struct pt_regs
*regs
;
1166 if (!atomic_read(&active_events
))
1180 #ifdef CONFIG_X86_LOCAL_APIC
1181 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1184 * Can't rely on the handled return value to say it was our NMI, two
1185 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1187 * If the first NMI handles both, the latter will be empty and daze
1190 x86_pmu
.handle_irq(regs
);
1195 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1196 .notifier_call
= perf_event_nmi_handler
,
1201 static struct event_constraint unconstrained
;
1202 static struct event_constraint emptyconstraint
;
1204 static struct event_constraint
*
1205 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1207 struct event_constraint
*c
;
1209 if (x86_pmu
.event_constraints
) {
1210 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1211 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1216 return &unconstrained
;
1219 static int x86_event_sched_in(struct perf_event
*event
,
1220 struct perf_cpu_context
*cpuctx
)
1224 event
->state
= PERF_EVENT_STATE_ACTIVE
;
1225 event
->oncpu
= smp_processor_id();
1226 event
->tstamp_running
+= event
->ctx
->time
- event
->tstamp_stopped
;
1228 if (!is_x86_event(event
))
1229 ret
= event
->pmu
->enable(event
);
1231 if (!ret
&& !is_software_event(event
))
1232 cpuctx
->active_oncpu
++;
1234 if (!ret
&& event
->attr
.exclusive
)
1235 cpuctx
->exclusive
= 1;
1240 static void x86_event_sched_out(struct perf_event
*event
,
1241 struct perf_cpu_context
*cpuctx
)
1243 event
->state
= PERF_EVENT_STATE_INACTIVE
;
1246 if (!is_x86_event(event
))
1247 event
->pmu
->disable(event
);
1249 event
->tstamp_running
-= event
->ctx
->time
- event
->tstamp_stopped
;
1251 if (!is_software_event(event
))
1252 cpuctx
->active_oncpu
--;
1254 if (event
->attr
.exclusive
|| !cpuctx
->active_oncpu
)
1255 cpuctx
->exclusive
= 0;
1259 * Called to enable a whole group of events.
1260 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1261 * Assumes the caller has disabled interrupts and has
1262 * frozen the PMU with hw_perf_save_disable.
1264 * called with PMU disabled. If successful and return value 1,
1265 * then guaranteed to call perf_enable() and hw_perf_enable()
1267 int hw_perf_group_sched_in(struct perf_event
*leader
,
1268 struct perf_cpu_context
*cpuctx
,
1269 struct perf_event_context
*ctx
)
1271 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1272 struct perf_event
*sub
;
1273 int assign
[X86_PMC_IDX_MAX
];
1276 /* n0 = total number of events */
1277 n0
= collect_events(cpuc
, leader
, true);
1281 ret
= x86_schedule_events(cpuc
, n0
, assign
);
1285 ret
= x86_event_sched_in(leader
, cpuctx
);
1290 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1291 if (sub
->state
> PERF_EVENT_STATE_OFF
) {
1292 ret
= x86_event_sched_in(sub
, cpuctx
);
1299 * copy new assignment, now we know it is possible
1300 * will be used by hw_perf_enable()
1302 memcpy(cpuc
->assign
, assign
, n0
*sizeof(int));
1304 cpuc
->n_events
= n0
;
1305 cpuc
->n_added
+= n1
;
1306 ctx
->nr_active
+= n1
;
1309 * 1 means successful and events are active
1310 * This is not quite true because we defer
1311 * actual activation until hw_perf_enable() but
1312 * this way we* ensure caller won't try to enable
1317 x86_event_sched_out(leader
, cpuctx
);
1319 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1320 if (sub
->state
== PERF_EVENT_STATE_ACTIVE
) {
1321 x86_event_sched_out(sub
, cpuctx
);
1329 #include "perf_event_amd.c"
1330 #include "perf_event_p6.c"
1331 #include "perf_event_intel.c"
1333 static int __cpuinit
1334 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1336 unsigned int cpu
= (long)hcpu
;
1338 switch (action
& ~CPU_TASKS_FROZEN
) {
1339 case CPU_UP_PREPARE
:
1340 if (x86_pmu
.cpu_prepare
)
1341 x86_pmu
.cpu_prepare(cpu
);
1345 if (x86_pmu
.cpu_starting
)
1346 x86_pmu
.cpu_starting(cpu
);
1350 if (x86_pmu
.cpu_dying
)
1351 x86_pmu
.cpu_dying(cpu
);
1355 if (x86_pmu
.cpu_dead
)
1356 x86_pmu
.cpu_dead(cpu
);
1366 static void __init
pmu_check_apic(void)
1372 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1373 pr_info("no hardware sampling interrupt available.\n");
1376 void __init
init_hw_perf_events(void)
1378 struct event_constraint
*c
;
1381 pr_info("Performance Events: ");
1383 switch (boot_cpu_data
.x86_vendor
) {
1384 case X86_VENDOR_INTEL
:
1385 err
= intel_pmu_init();
1387 case X86_VENDOR_AMD
:
1388 err
= amd_pmu_init();
1394 pr_cont("no PMU driver, software events only.\n");
1400 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1402 if (x86_pmu
.num_events
> X86_PMC_MAX_GENERIC
) {
1403 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1404 x86_pmu
.num_events
, X86_PMC_MAX_GENERIC
);
1405 x86_pmu
.num_events
= X86_PMC_MAX_GENERIC
;
1407 perf_event_mask
= (1 << x86_pmu
.num_events
) - 1;
1408 perf_max_events
= x86_pmu
.num_events
;
1410 if (x86_pmu
.num_events_fixed
> X86_PMC_MAX_FIXED
) {
1411 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1412 x86_pmu
.num_events_fixed
, X86_PMC_MAX_FIXED
);
1413 x86_pmu
.num_events_fixed
= X86_PMC_MAX_FIXED
;
1417 ((1LL << x86_pmu
.num_events_fixed
)-1) << X86_PMC_IDX_FIXED
;
1418 x86_pmu
.intel_ctrl
= perf_event_mask
;
1420 perf_events_lapic_init();
1421 register_die_notifier(&perf_event_nmi_notifier
);
1423 unconstrained
= (struct event_constraint
)
1424 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_events
) - 1,
1425 0, x86_pmu
.num_events
);
1427 if (x86_pmu
.event_constraints
) {
1428 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1429 if (c
->cmask
!= INTEL_ARCH_FIXED_MASK
)
1432 c
->idxmsk64
|= (1ULL << x86_pmu
.num_events
) - 1;
1433 c
->weight
+= x86_pmu
.num_events
;
1437 pr_info("... version: %d\n", x86_pmu
.version
);
1438 pr_info("... bit width: %d\n", x86_pmu
.event_bits
);
1439 pr_info("... generic registers: %d\n", x86_pmu
.num_events
);
1440 pr_info("... value mask: %016Lx\n", x86_pmu
.event_mask
);
1441 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1442 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_events_fixed
);
1443 pr_info("... event mask: %016Lx\n", perf_event_mask
);
1445 perf_cpu_notifier(x86_pmu_notifier
);
1448 static inline void x86_pmu_read(struct perf_event
*event
)
1450 x86_perf_event_update(event
);
1453 static const struct pmu pmu
= {
1454 .enable
= x86_pmu_enable
,
1455 .disable
= x86_pmu_disable
,
1456 .start
= x86_pmu_start
,
1457 .stop
= x86_pmu_stop
,
1458 .read
= x86_pmu_read
,
1459 .unthrottle
= x86_pmu_unthrottle
,
1463 * validate a single event group
1465 * validation include:
1466 * - check events are compatible which each other
1467 * - events do not compete for the same counter
1468 * - number of events <= number of counters
1470 * validation ensures the group can be loaded onto the
1471 * PMU if it was the only group available.
1473 static int validate_group(struct perf_event
*event
)
1475 struct perf_event
*leader
= event
->group_leader
;
1476 struct cpu_hw_events
*fake_cpuc
;
1480 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1485 * the event is not yet connected with its
1486 * siblings therefore we must first collect
1487 * existing siblings, then add the new event
1488 * before we can simulate the scheduling
1491 n
= collect_events(fake_cpuc
, leader
, true);
1495 fake_cpuc
->n_events
= n
;
1496 n
= collect_events(fake_cpuc
, event
, false);
1500 fake_cpuc
->n_events
= n
;
1502 ret
= x86_schedule_events(fake_cpuc
, n
, NULL
);
1510 const struct pmu
*hw_perf_event_init(struct perf_event
*event
)
1512 const struct pmu
*tmp
;
1515 err
= __hw_perf_event_init(event
);
1518 * we temporarily connect event to its pmu
1519 * such that validate_group() can classify
1520 * it as an x86 event using is_x86_event()
1525 if (event
->group_leader
!= event
)
1526 err
= validate_group(event
);
1532 event
->destroy(event
);
1533 return ERR_PTR(err
);
1544 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1546 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1547 entry
->ip
[entry
->nr
++] = ip
;
1550 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_irq_entry
);
1551 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_nmi_entry
);
1555 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1557 /* Ignore warnings */
1560 static void backtrace_warning(void *data
, char *msg
)
1562 /* Ignore warnings */
1565 static int backtrace_stack(void *data
, char *name
)
1570 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1572 struct perf_callchain_entry
*entry
= data
;
1575 callchain_store(entry
, addr
);
1578 static const struct stacktrace_ops backtrace_ops
= {
1579 .warning
= backtrace_warning
,
1580 .warning_symbol
= backtrace_warning_symbol
,
1581 .stack
= backtrace_stack
,
1582 .address
= backtrace_address
,
1583 .walk_stack
= print_context_stack_bp
,
1586 #include "../dumpstack.h"
1589 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1591 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1592 callchain_store(entry
, regs
->ip
);
1594 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1598 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1600 static unsigned long
1601 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
1603 unsigned long offset
, addr
= (unsigned long)from
;
1604 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
1605 unsigned long size
, len
= 0;
1611 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
1615 offset
= addr
& (PAGE_SIZE
- 1);
1616 size
= min(PAGE_SIZE
- offset
, n
- len
);
1618 map
= kmap_atomic(page
, type
);
1619 memcpy(to
, map
+offset
, size
);
1620 kunmap_atomic(map
, type
);
1632 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1634 unsigned long bytes
;
1636 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1638 return bytes
== sizeof(*frame
);
1642 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1644 struct stack_frame frame
;
1645 const void __user
*fp
;
1647 if (!user_mode(regs
))
1648 regs
= task_pt_regs(current
);
1650 fp
= (void __user
*)regs
->bp
;
1652 callchain_store(entry
, PERF_CONTEXT_USER
);
1653 callchain_store(entry
, regs
->ip
);
1655 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1656 frame
.next_frame
= NULL
;
1657 frame
.return_address
= 0;
1659 if (!copy_stack_frame(fp
, &frame
))
1662 if ((unsigned long)fp
< regs
->sp
)
1665 callchain_store(entry
, frame
.return_address
);
1666 fp
= frame
.next_frame
;
1671 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1678 is_user
= user_mode(regs
);
1680 if (is_user
&& current
->state
!= TASK_RUNNING
)
1684 perf_callchain_kernel(regs
, entry
);
1687 perf_callchain_user(regs
, entry
);
1690 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1692 struct perf_callchain_entry
*entry
;
1695 entry
= &__get_cpu_var(pmc_nmi_entry
);
1697 entry
= &__get_cpu_var(pmc_irq_entry
);
1701 perf_do_callchain(regs
, entry
);
1706 #ifdef CONFIG_EVENT_TRACING
1707 void perf_arch_fetch_caller_regs(struct pt_regs
*regs
, unsigned long ip
, int skip
)
1711 * perf_arch_fetch_caller_regs adds another call, we need to increment
1714 regs
->bp
= rewind_frame_pointer(skip
+ 1);
1715 regs
->cs
= __KERNEL_CS
;
1716 local_save_flags(regs
->flags
);