1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
9 #include <asm/fpu/api.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/sched.h>
12 #include <asm/fpu/signal.h>
13 #include <asm/fpu/types.h>
14 #include <asm/traps.h>
15 #include <asm/irq_regs.h>
17 #include <uapi/asm/kvm.h>
19 #include <linux/hardirq.h>
20 #include <linux/pkeys.h>
21 #include <linux/vmalloc.h>
28 #define CREATE_TRACE_POINTS
29 #include <asm/trace/fpu.h>
32 DEFINE_STATIC_KEY_FALSE(__fpu_state_size_dynamic
);
33 DEFINE_PER_CPU(u64
, xfd_state
);
36 /* The FPU state configuration data for kernel and user space */
37 struct fpu_state_config fpu_kernel_cfg __ro_after_init
;
38 struct fpu_state_config fpu_user_cfg __ro_after_init
;
41 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
42 * depending on the FPU hardware format:
44 struct fpstate init_fpstate __ro_after_init
;
46 /* Track in-kernel FPU usage */
47 static DEFINE_PER_CPU(bool, in_kernel_fpu
);
50 * Track which context is using the FPU on the CPU:
52 DEFINE_PER_CPU(struct fpu
*, fpu_fpregs_owner_ctx
);
55 * Can we use the FPU in kernel mode with the
56 * whole "kernel_fpu_begin/end()" sequence?
58 bool irq_fpu_usable(void)
60 if (WARN_ON_ONCE(in_nmi()))
63 /* In kernel FPU usage already active? */
64 if (this_cpu_read(in_kernel_fpu
))
68 * When not in NMI or hard interrupt context, FPU can be used in:
70 * - Task context except from within fpregs_lock()'ed critical
73 * - Soft interrupt processing context which cannot happen
74 * while in a fpregs_lock()'ed critical region.
80 * In hard interrupt context it's safe when soft interrupts
81 * are enabled, which means the interrupt did not hit in
82 * a fpregs_lock()'ed critical region.
84 return !softirq_count();
86 EXPORT_SYMBOL(irq_fpu_usable
);
89 * Track AVX512 state use because it is known to slow the max clock
92 static void update_avx_timestamp(struct fpu
*fpu
)
95 #define AVX512_TRACKING_MASK (XFEATURE_MASK_ZMM_Hi256 | XFEATURE_MASK_Hi16_ZMM)
97 if (fpu
->fpstate
->regs
.xsave
.header
.xfeatures
& AVX512_TRACKING_MASK
)
98 fpu
->avx512_timestamp
= jiffies
;
102 * Save the FPU register state in fpu->fpstate->regs. The register state is
105 * Must be called with fpregs_lock() held.
107 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
108 * register state has to be reloaded. That might be a pointless exercise
109 * when the FPU is going to be used by another task right after that. But
110 * this only affects 20+ years old 32bit systems and avoids conditionals all
113 * FXSAVE and all XSAVE variants preserve the FPU register state.
115 void save_fpregs_to_fpstate(struct fpu
*fpu
)
117 if (likely(use_xsave())) {
118 os_xsave(fpu
->fpstate
);
119 update_avx_timestamp(fpu
);
123 if (likely(use_fxsr())) {
124 fxsave(&fpu
->fpstate
->regs
.fxsave
);
129 * Legacy FPU register saving, FNSAVE always clears FPU registers,
130 * so we have to reload them from the memory state.
132 asm volatile("fnsave %[fp]; fwait" : [fp
] "=m" (fpu
->fpstate
->regs
.fsave
));
133 frstor(&fpu
->fpstate
->regs
.fsave
);
136 void restore_fpregs_from_fpstate(struct fpstate
*fpstate
, u64 mask
)
139 * AMD K7/K8 and later CPUs up to Zen don't save/restore
140 * FDP/FIP/FOP unless an exception is pending. Clear the x87 state
141 * here by setting it to fixed values. "m" is a random variable
142 * that should be in L1.
144 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK
))) {
148 "fildl %P[addr]" /* set F?P to defined value */
149 : : [addr
] "m" (fpstate
));
154 * Dynamically enabled features are enabled in XCR0, but
155 * usage requires also that the corresponding bits in XFD
156 * are cleared. If the bits are set then using a related
157 * instruction will raise #NM. This allows to do the
158 * allocation of the larger FPU buffer lazy from #NM or if
159 * the task has no permission to kill it which would happen
160 * via #UD if the feature is disabled in XCR0.
162 * XFD state is following the same life time rules as
163 * XSTATE and to restore state correctly XFD has to be
164 * updated before XRSTORS otherwise the component would
165 * stay in or go into init state even if the bits are set
166 * in fpstate::regs::xsave::xfeatures.
168 xfd_update_state(fpstate
);
171 * Restoring state always needs to modify all features
172 * which are in @mask even if the current task cannot use
175 * So fpstate->xfeatures cannot be used here, because then
176 * a feature for which the task has no permission but was
177 * used by the previous task would not go into init state.
179 mask
= fpu_kernel_cfg
.max_features
& mask
;
181 os_xrstor(fpstate
, mask
);
184 fxrstor(&fpstate
->regs
.fxsave
);
186 frstor(&fpstate
->regs
.fsave
);
190 void fpu_reset_from_exception_fixup(void)
192 restore_fpregs_from_fpstate(&init_fpstate
, XFEATURE_MASK_FPSTATE
);
195 #if IS_ENABLED(CONFIG_KVM)
196 static void __fpstate_reset(struct fpstate
*fpstate
, u64 xfd
);
198 static void fpu_init_guest_permissions(struct fpu_guest
*gfpu
)
200 struct fpu_state_perm
*fpuperm
;
203 if (!IS_ENABLED(CONFIG_X86_64
))
206 spin_lock_irq(¤t
->sighand
->siglock
);
207 fpuperm
= ¤t
->group_leader
->thread
.fpu
.guest_perm
;
208 perm
= fpuperm
->__state_perm
;
210 /* First fpstate allocation locks down permissions. */
211 WRITE_ONCE(fpuperm
->__state_perm
, perm
| FPU_GUEST_PERM_LOCKED
);
213 spin_unlock_irq(¤t
->sighand
->siglock
);
215 gfpu
->perm
= perm
& ~FPU_GUEST_PERM_LOCKED
;
218 bool fpu_alloc_guest_fpstate(struct fpu_guest
*gfpu
)
220 struct fpstate
*fpstate
;
223 size
= fpu_user_cfg
.default_size
+ ALIGN(offsetof(struct fpstate
, regs
), 64);
224 fpstate
= vzalloc(size
);
228 /* Leave xfd to 0 (the reset value defined by spec) */
229 __fpstate_reset(fpstate
, 0);
230 fpstate_init_user(fpstate
);
231 fpstate
->is_valloc
= true;
232 fpstate
->is_guest
= true;
234 gfpu
->fpstate
= fpstate
;
235 gfpu
->xfeatures
= fpu_user_cfg
.default_features
;
236 gfpu
->perm
= fpu_user_cfg
.default_features
;
239 * KVM sets the FP+SSE bits in the XSAVE header when copying FPU state
240 * to userspace, even when XSAVE is unsupported, so that restoring FPU
241 * state on a different CPU that does support XSAVE can cleanly load
242 * the incoming state using its natural XSAVE. In other words, KVM's
243 * uABI size may be larger than this host's default size. Conversely,
244 * the default size should never be larger than KVM's base uABI size;
245 * all features that can expand the uABI size must be opt-in.
247 gfpu
->uabi_size
= sizeof(struct kvm_xsave
);
248 if (WARN_ON_ONCE(fpu_user_cfg
.default_size
> gfpu
->uabi_size
))
249 gfpu
->uabi_size
= fpu_user_cfg
.default_size
;
251 fpu_init_guest_permissions(gfpu
);
255 EXPORT_SYMBOL_GPL(fpu_alloc_guest_fpstate
);
257 void fpu_free_guest_fpstate(struct fpu_guest
*gfpu
)
259 struct fpstate
*fps
= gfpu
->fpstate
;
264 if (WARN_ON_ONCE(!fps
->is_valloc
|| !fps
->is_guest
|| fps
->in_use
))
267 gfpu
->fpstate
= NULL
;
270 EXPORT_SYMBOL_GPL(fpu_free_guest_fpstate
);
273 * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable
274 * @guest_fpu: Pointer to the guest FPU container
275 * @xfeatures: Features requested by guest CPUID
277 * Enable all dynamic xfeatures according to guest perm and requested CPUID.
279 * Return: 0 on success, error code otherwise
281 int fpu_enable_guest_xfd_features(struct fpu_guest
*guest_fpu
, u64 xfeatures
)
283 lockdep_assert_preemption_enabled();
285 /* Nothing to do if all requested features are already enabled. */
286 xfeatures
&= ~guest_fpu
->xfeatures
;
290 return __xfd_enable_feature(xfeatures
, guest_fpu
);
292 EXPORT_SYMBOL_GPL(fpu_enable_guest_xfd_features
);
295 void fpu_update_guest_xfd(struct fpu_guest
*guest_fpu
, u64 xfd
)
298 guest_fpu
->fpstate
->xfd
= xfd
;
299 if (guest_fpu
->fpstate
->in_use
)
300 xfd_update_state(guest_fpu
->fpstate
);
303 EXPORT_SYMBOL_GPL(fpu_update_guest_xfd
);
306 * fpu_sync_guest_vmexit_xfd_state - Synchronize XFD MSR and software state
308 * Must be invoked from KVM after a VMEXIT before enabling interrupts when
309 * XFD write emulation is disabled. This is required because the guest can
310 * freely modify XFD and the state at VMEXIT is not guaranteed to be the
311 * same as the state on VMENTER. So software state has to be udpated before
312 * any operation which depends on it can take place.
314 * Note: It can be invoked unconditionally even when write emulation is
315 * enabled for the price of a then pointless MSR read.
317 void fpu_sync_guest_vmexit_xfd_state(void)
319 struct fpstate
*fps
= current
->thread
.fpu
.fpstate
;
321 lockdep_assert_irqs_disabled();
322 if (fpu_state_size_dynamic()) {
323 rdmsrl(MSR_IA32_XFD
, fps
->xfd
);
324 __this_cpu_write(xfd_state
, fps
->xfd
);
327 EXPORT_SYMBOL_GPL(fpu_sync_guest_vmexit_xfd_state
);
328 #endif /* CONFIG_X86_64 */
330 int fpu_swap_kvm_fpstate(struct fpu_guest
*guest_fpu
, bool enter_guest
)
332 struct fpstate
*guest_fps
= guest_fpu
->fpstate
;
333 struct fpu
*fpu
= ¤t
->thread
.fpu
;
334 struct fpstate
*cur_fps
= fpu
->fpstate
;
337 if (!cur_fps
->is_confidential
&& !test_thread_flag(TIF_NEED_FPU_LOAD
))
338 save_fpregs_to_fpstate(fpu
);
342 fpu
->__task_fpstate
= cur_fps
;
343 fpu
->fpstate
= guest_fps
;
344 guest_fps
->in_use
= true;
346 guest_fps
->in_use
= false;
347 fpu
->fpstate
= fpu
->__task_fpstate
;
348 fpu
->__task_fpstate
= NULL
;
351 cur_fps
= fpu
->fpstate
;
353 if (!cur_fps
->is_confidential
) {
354 /* Includes XFD update */
355 restore_fpregs_from_fpstate(cur_fps
, XFEATURE_MASK_FPSTATE
);
358 * XSTATE is restored by firmware from encrypted
359 * memory. Make sure XFD state is correct while
360 * running with guest fpstate
362 xfd_update_state(cur_fps
);
365 fpregs_mark_activate();
369 EXPORT_SYMBOL_GPL(fpu_swap_kvm_fpstate
);
371 void fpu_copy_guest_fpstate_to_uabi(struct fpu_guest
*gfpu
, void *buf
,
372 unsigned int size
, u64 xfeatures
, u32 pkru
)
374 struct fpstate
*kstate
= gfpu
->fpstate
;
375 union fpregs_state
*ustate
= buf
;
376 struct membuf mb
= { .p
= buf
, .left
= size
};
378 if (cpu_feature_enabled(X86_FEATURE_XSAVE
)) {
379 __copy_xstate_to_uabi_buf(mb
, kstate
, xfeatures
, pkru
,
382 memcpy(&ustate
->fxsave
, &kstate
->regs
.fxsave
,
383 sizeof(ustate
->fxsave
));
384 /* Make it restorable on a XSAVE enabled host */
385 ustate
->xsave
.header
.xfeatures
= XFEATURE_MASK_FPSSE
;
388 EXPORT_SYMBOL_GPL(fpu_copy_guest_fpstate_to_uabi
);
390 int fpu_copy_uabi_to_guest_fpstate(struct fpu_guest
*gfpu
, const void *buf
,
391 u64 xcr0
, u32
*vpkru
)
393 struct fpstate
*kstate
= gfpu
->fpstate
;
394 const union fpregs_state
*ustate
= buf
;
396 if (!cpu_feature_enabled(X86_FEATURE_XSAVE
)) {
397 if (ustate
->xsave
.header
.xfeatures
& ~XFEATURE_MASK_FPSSE
)
399 if (ustate
->fxsave
.mxcsr
& ~mxcsr_feature_mask
)
401 memcpy(&kstate
->regs
.fxsave
, &ustate
->fxsave
, sizeof(ustate
->fxsave
));
405 if (ustate
->xsave
.header
.xfeatures
& ~xcr0
)
409 * Nullify @vpkru to preserve its current value if PKRU's bit isn't set
410 * in the header. KVM's odd ABI is to leave PKRU untouched in this
411 * case (all other components are eventually re-initialized).
413 if (!(ustate
->xsave
.header
.xfeatures
& XFEATURE_MASK_PKRU
))
416 return copy_uabi_from_kernel_to_xstate(kstate
, ustate
, vpkru
);
418 EXPORT_SYMBOL_GPL(fpu_copy_uabi_to_guest_fpstate
);
419 #endif /* CONFIG_KVM */
421 void kernel_fpu_begin_mask(unsigned int kfpu_mask
)
425 WARN_ON_FPU(!irq_fpu_usable());
426 WARN_ON_FPU(this_cpu_read(in_kernel_fpu
));
428 this_cpu_write(in_kernel_fpu
, true);
430 if (!(current
->flags
& (PF_KTHREAD
| PF_USER_WORKER
)) &&
431 !test_thread_flag(TIF_NEED_FPU_LOAD
)) {
432 set_thread_flag(TIF_NEED_FPU_LOAD
);
433 save_fpregs_to_fpstate(¤t
->thread
.fpu
);
435 __cpu_invalidate_fpregs_state();
437 /* Put sane initial values into the control registers. */
438 if (likely(kfpu_mask
& KFPU_MXCSR
) && boot_cpu_has(X86_FEATURE_XMM
))
439 ldmxcsr(MXCSR_DEFAULT
);
441 if (unlikely(kfpu_mask
& KFPU_387
) && boot_cpu_has(X86_FEATURE_FPU
))
442 asm volatile ("fninit");
444 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask
);
446 void kernel_fpu_end(void)
448 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu
));
450 this_cpu_write(in_kernel_fpu
, false);
453 EXPORT_SYMBOL_GPL(kernel_fpu_end
);
456 * Sync the FPU register state to current's memory register state when the
457 * current task owns the FPU. The hardware register state is preserved.
459 void fpu_sync_fpstate(struct fpu
*fpu
)
461 WARN_ON_FPU(fpu
!= ¤t
->thread
.fpu
);
464 trace_x86_fpu_before_save(fpu
);
466 if (!test_thread_flag(TIF_NEED_FPU_LOAD
))
467 save_fpregs_to_fpstate(fpu
);
469 trace_x86_fpu_after_save(fpu
);
473 static inline unsigned int init_fpstate_copy_size(void)
476 return fpu_kernel_cfg
.default_size
;
478 /* XSAVE(S) just needs the legacy and the xstate header part */
479 return sizeof(init_fpstate
.regs
.xsave
);
482 static inline void fpstate_init_fxstate(struct fpstate
*fpstate
)
484 fpstate
->regs
.fxsave
.cwd
= 0x37f;
485 fpstate
->regs
.fxsave
.mxcsr
= MXCSR_DEFAULT
;
489 * Legacy x87 fpstate state init:
491 static inline void fpstate_init_fstate(struct fpstate
*fpstate
)
493 fpstate
->regs
.fsave
.cwd
= 0xffff037fu
;
494 fpstate
->regs
.fsave
.swd
= 0xffff0000u
;
495 fpstate
->regs
.fsave
.twd
= 0xffffffffu
;
496 fpstate
->regs
.fsave
.fos
= 0xffff0000u
;
500 * Used in two places:
501 * 1) Early boot to setup init_fpstate for non XSAVE systems
502 * 2) fpu_init_fpstate_user() which is invoked from KVM
504 void fpstate_init_user(struct fpstate
*fpstate
)
506 if (!cpu_feature_enabled(X86_FEATURE_FPU
)) {
507 fpstate_init_soft(&fpstate
->regs
.soft
);
511 xstate_init_xcomp_bv(&fpstate
->regs
.xsave
, fpstate
->xfeatures
);
513 if (cpu_feature_enabled(X86_FEATURE_FXSR
))
514 fpstate_init_fxstate(fpstate
);
516 fpstate_init_fstate(fpstate
);
519 static void __fpstate_reset(struct fpstate
*fpstate
, u64 xfd
)
521 /* Initialize sizes and feature masks */
522 fpstate
->size
= fpu_kernel_cfg
.default_size
;
523 fpstate
->user_size
= fpu_user_cfg
.default_size
;
524 fpstate
->xfeatures
= fpu_kernel_cfg
.default_features
;
525 fpstate
->user_xfeatures
= fpu_user_cfg
.default_features
;
529 void fpstate_reset(struct fpu
*fpu
)
531 /* Set the fpstate pointer to the default fpstate */
532 fpu
->fpstate
= &fpu
->__fpstate
;
533 __fpstate_reset(fpu
->fpstate
, init_fpstate
.xfd
);
535 /* Initialize the permission related info in fpu */
536 fpu
->perm
.__state_perm
= fpu_kernel_cfg
.default_features
;
537 fpu
->perm
.__state_size
= fpu_kernel_cfg
.default_size
;
538 fpu
->perm
.__user_state_size
= fpu_user_cfg
.default_size
;
539 /* Same defaults for guests */
540 fpu
->guest_perm
= fpu
->perm
;
543 static inline void fpu_inherit_perms(struct fpu
*dst_fpu
)
545 if (fpu_state_size_dynamic()) {
546 struct fpu
*src_fpu
= ¤t
->group_leader
->thread
.fpu
;
548 spin_lock_irq(¤t
->sighand
->siglock
);
549 /* Fork also inherits the permissions of the parent */
550 dst_fpu
->perm
= src_fpu
->perm
;
551 dst_fpu
->guest_perm
= src_fpu
->guest_perm
;
552 spin_unlock_irq(¤t
->sighand
->siglock
);
556 /* A passed ssp of zero will not cause any update */
557 static int update_fpu_shstk(struct task_struct
*dst
, unsigned long ssp
)
559 #ifdef CONFIG_X86_USER_SHADOW_STACK
560 struct cet_user_state
*xstate
;
562 /* If ssp update is not needed. */
566 xstate
= get_xsave_addr(&dst
->thread
.fpu
.fpstate
->regs
.xsave
,
570 * If there is a non-zero ssp, then 'dst' must be configured with a shadow
571 * stack and the fpu state should be up to date since it was just copied
572 * from the parent in fpu_clone(). So there must be a valid non-init CET
573 * state location in the buffer.
575 if (WARN_ON_ONCE(!xstate
))
578 xstate
->user_ssp
= (u64
)ssp
;
583 /* Clone current's FPU state on fork */
584 int fpu_clone(struct task_struct
*dst
, unsigned long clone_flags
, bool minimal
,
587 struct fpu
*src_fpu
= ¤t
->thread
.fpu
;
588 struct fpu
*dst_fpu
= &dst
->thread
.fpu
;
590 /* The new task's FPU state cannot be valid in the hardware. */
591 dst_fpu
->last_cpu
= -1;
593 fpstate_reset(dst_fpu
);
595 if (!cpu_feature_enabled(X86_FEATURE_FPU
))
599 * Enforce reload for user space tasks and prevent kernel threads
600 * from trying to save the FPU registers on context switch.
602 set_tsk_thread_flag(dst
, TIF_NEED_FPU_LOAD
);
605 * No FPU state inheritance for kernel threads and IO
609 /* Clear out the minimal state */
610 memcpy(&dst_fpu
->fpstate
->regs
, &init_fpstate
.regs
,
611 init_fpstate_copy_size());
616 * If a new feature is added, ensure all dynamic features are
617 * caller-saved from here!
619 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC
!= XFEATURE_MASK_XTILE_DATA
);
622 * Save the default portion of the current FPU state into the
623 * clone. Assume all dynamic features to be defined as caller-
624 * saved, which enables skipping both the expansion of fpstate
625 * and the copying of any dynamic state.
627 * Do not use memcpy() when TIF_NEED_FPU_LOAD is set because
628 * copying is not valid when current uses non-default states.
631 if (test_thread_flag(TIF_NEED_FPU_LOAD
))
632 fpregs_restore_userregs();
633 save_fpregs_to_fpstate(dst_fpu
);
635 if (!(clone_flags
& CLONE_THREAD
))
636 fpu_inherit_perms(dst_fpu
);
639 * Children never inherit PASID state.
640 * Force it to have its init value:
643 dst_fpu
->fpstate
->regs
.xsave
.header
.xfeatures
&= ~XFEATURE_MASK_PASID
;
646 * Update shadow stack pointer, in case it changed during clone.
648 if (update_fpu_shstk(dst
, ssp
))
651 trace_x86_fpu_copy_src(src_fpu
);
652 trace_x86_fpu_copy_dst(dst_fpu
);
658 * Whitelist the FPU register state embedded into task_struct for hardened
661 void fpu_thread_struct_whitelist(unsigned long *offset
, unsigned long *size
)
663 *offset
= offsetof(struct thread_struct
, fpu
.__fpstate
.regs
);
664 *size
= fpu_kernel_cfg
.default_size
;
668 * Drops current FPU state: deactivates the fpregs and
669 * the fpstate. NOTE: it still leaves previous contents
670 * in the fpregs in the eager-FPU case.
672 * This function can be used in cases where we know that
673 * a state-restore is coming: either an explicit one,
676 void fpu__drop(struct fpu
*fpu
)
680 if (fpu
== ¤t
->thread
.fpu
) {
681 /* Ignore delayed exceptions from user space */
682 asm volatile("1: fwait\n"
684 _ASM_EXTABLE(1b
, 2b
));
685 fpregs_deactivate(fpu
);
688 trace_x86_fpu_dropped(fpu
);
694 * Clear FPU registers by setting them up from the init fpstate.
695 * Caller must do fpregs_[un]lock() around it.
697 static inline void restore_fpregs_from_init_fpstate(u64 features_mask
)
700 os_xrstor(&init_fpstate
, features_mask
);
702 fxrstor(&init_fpstate
.regs
.fxsave
);
704 frstor(&init_fpstate
.regs
.fsave
);
706 pkru_write_default();
710 * Reset current->fpu memory state to the init values.
712 static void fpu_reset_fpregs(void)
714 struct fpu
*fpu
= ¤t
->thread
.fpu
;
717 __fpu_invalidate_fpregs_state(fpu
);
719 * This does not change the actual hardware registers. It just
720 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
721 * subsequent return to usermode will reload the registers from the
722 * task's memory image.
724 * Do not use fpstate_init() here. Just copy init_fpstate which has
725 * the correct content already except for PKRU.
727 * PKRU handling does not rely on the xstate when restoring for
728 * user space as PKRU is eagerly written in switch_to() and
731 memcpy(&fpu
->fpstate
->regs
, &init_fpstate
.regs
, init_fpstate_copy_size());
732 set_thread_flag(TIF_NEED_FPU_LOAD
);
737 * Reset current's user FPU states to the init states. current's
738 * supervisor states, if any, are not modified by this function. The
739 * caller guarantees that the XSTATE header in memory is intact.
741 void fpu__clear_user_states(struct fpu
*fpu
)
743 WARN_ON_FPU(fpu
!= ¤t
->thread
.fpu
);
746 if (!cpu_feature_enabled(X86_FEATURE_FPU
)) {
753 * Ensure that current's supervisor states are loaded into their
754 * corresponding registers.
756 if (xfeatures_mask_supervisor() &&
757 !fpregs_state_valid(fpu
, smp_processor_id()))
758 os_xrstor_supervisor(fpu
->fpstate
);
760 /* Reset user states in registers. */
761 restore_fpregs_from_init_fpstate(XFEATURE_MASK_USER_RESTORE
);
764 * Now all FPU registers have their desired values. Inform the FPU
765 * state machine that current's FPU registers are in the hardware
766 * registers. The memory image does not need to be updated because
767 * any operation relying on it has to save the registers first when
768 * current's FPU is marked active.
770 fpregs_mark_activate();
774 void fpu_flush_thread(void)
776 fpstate_reset(¤t
->thread
.fpu
);
780 * Load FPU context before returning to userspace.
782 void switch_fpu_return(void)
784 if (!static_cpu_has(X86_FEATURE_FPU
))
787 fpregs_restore_userregs();
789 EXPORT_SYMBOL_GPL(switch_fpu_return
);
791 void fpregs_lock_and_load(void)
794 * fpregs_lock() only disables preemption (mostly). So modifying state
795 * in an interrupt could screw up some in progress fpregs operation.
798 WARN_ON_ONCE(!irq_fpu_usable());
799 WARN_ON_ONCE(current
->flags
& PF_KTHREAD
);
803 fpregs_assert_state_consistent();
805 if (test_thread_flag(TIF_NEED_FPU_LOAD
))
806 fpregs_restore_userregs();
809 #ifdef CONFIG_X86_DEBUG_FPU
811 * If current FPU state according to its tracking (loaded FPU context on this
812 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
813 * loaded on return to userland.
815 void fpregs_assert_state_consistent(void)
817 struct fpu
*fpu
= ¤t
->thread
.fpu
;
819 if (test_thread_flag(TIF_NEED_FPU_LOAD
))
822 WARN_ON_FPU(!fpregs_state_valid(fpu
, smp_processor_id()));
824 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent
);
827 void fpregs_mark_activate(void)
829 struct fpu
*fpu
= ¤t
->thread
.fpu
;
831 fpregs_activate(fpu
);
832 fpu
->last_cpu
= smp_processor_id();
833 clear_thread_flag(TIF_NEED_FPU_LOAD
);
837 * x87 math exception handling:
840 int fpu__exception_code(struct fpu
*fpu
, int trap_nr
)
844 if (trap_nr
== X86_TRAP_MF
) {
845 unsigned short cwd
, swd
;
847 * (~cwd & swd) will mask out exceptions that are not set to unmasked
848 * status. 0x3f is the exception bits in these regs, 0x200 is the
849 * C1 reg you need in case of a stack fault, 0x040 is the stack
850 * fault bit. We should only be taking one exception at a time,
851 * so if this combination doesn't produce any single exception,
852 * then we have a bad program that isn't synchronizing its FPU usage
853 * and it will suffer the consequences since we won't be able to
854 * fully reproduce the context of the exception.
856 if (boot_cpu_has(X86_FEATURE_FXSR
)) {
857 cwd
= fpu
->fpstate
->regs
.fxsave
.cwd
;
858 swd
= fpu
->fpstate
->regs
.fxsave
.swd
;
860 cwd
= (unsigned short)fpu
->fpstate
->regs
.fsave
.cwd
;
861 swd
= (unsigned short)fpu
->fpstate
->regs
.fsave
.swd
;
867 * The SIMD FPU exceptions are handled a little differently, as there
868 * is only a single status/control register. Thus, to determine which
869 * unmasked exception was caught we must mask the exception mask bits
870 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
872 unsigned short mxcsr
= MXCSR_DEFAULT
;
874 if (boot_cpu_has(X86_FEATURE_XMM
))
875 mxcsr
= fpu
->fpstate
->regs
.fxsave
.mxcsr
;
877 err
= ~(mxcsr
>> 7) & mxcsr
;
880 if (err
& 0x001) { /* Invalid op */
882 * swd & 0x240 == 0x040: Stack Underflow
883 * swd & 0x240 == 0x240: Stack Overflow
884 * User must clear the SF bit (0x40) if set
887 } else if (err
& 0x004) { /* Divide by Zero */
889 } else if (err
& 0x008) { /* Overflow */
891 } else if (err
& 0x012) { /* Denormal, Underflow */
893 } else if (err
& 0x020) { /* Precision */
898 * If we're using IRQ 13, or supposedly even some trap
899 * X86_TRAP_MF implementations, it's possible
900 * we get a spurious trap, which is not an error.
906 * Initialize register state that may prevent from entering low-power idle.
907 * This function will be invoked from the cpuidle driver only when needed.
909 noinstr
void fpu_idle_fpregs(void)
911 /* Note: AMX_TILE being enabled implies XGETBV1 support */
912 if (cpu_feature_enabled(X86_FEATURE_AMX_TILE
) &&
913 (xfeatures_in_use() & XFEATURE_MASK_XTILE
)) {
915 __this_cpu_write(fpu_fpregs_owner_ctx
, NULL
);