arch/x86/kernel/process_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *
   4  *  Pentium III FXSR, SSE support
   5  *      Gareth Hughes <gareth@valinux.com>, May 2000
   6  *
   7  *  X86-64 port
   8  *      Andi Kleen.
   9  *
  10  *      CPU hotplug support - ashok.raj@intel.com
  11  */
  12
  13 /*
  14  * This file handles the architecture-dependent parts of process handling..
  15  */
  16
  17 #include <linux/cpu.h>
  18 #include <linux/errno.h>
  19 #include <linux/sched.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/fs.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/elfcore.h>
  26 #include <linux/smp.h>
  27 #include <linux/slab.h>
  28 #include <linux/user.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/export.h>
  32 #include <linux/ptrace.h>
  33 #include <linux/notifier.h>
  34 #include <linux/kprobes.h>
  35 #include <linux/kdebug.h>
  36 #include <linux/prctl.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/io.h>
  39 #include <linux/ftrace.h>
  40 #include <linux/syscalls.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/processor.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/mmu_context.h>
  46 #include <asm/prctl.h>
  47 #include <asm/desc.h>
  48 #include <asm/proto.h>
  49 #include <asm/ia32.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/debugreg.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/xen/hypervisor.h>
  54 #include <asm/vdso.h>
  55 #include <asm/intel_rdt_sched.h>
  56 #include <asm/unistd.h>
  57 #ifdef CONFIG_IA32_EMULATION
  58 /* Not included via unistd.h */
  59 #include <asm/unistd_32_ia32.h>
  60 #endif
  61
  62 /* Prints also some state that isn't saved in the pt_regs */
  63 void __show_regs(struct pt_regs *regs, int all)
  64 {
  65         unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
  66         unsigned long d0, d1, d2, d3, d6, d7;
  67         unsigned int fsindex, gsindex;
  68         unsigned int ds, cs, es;
  69
  70         show_iret_regs(regs);
  71
  72         if (regs->orig_ax != -1)
  73                 pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax);
  74         else
  75                 pr_cont("\n");
  76
  77         printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
  78                regs->ax, regs->bx, regs->cx);
  79         printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
  80                regs->dx, regs->si, regs->di);
  81         printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
  82                regs->bp, regs->r8, regs->r9);
  83         printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
  84                regs->r10, regs->r11, regs->r12);
  85         printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
  86                regs->r13, regs->r14, regs->r15);
  87
  88         if (!all)
  89                 return;
  90
  91         asm("movl %%ds,%0" : "=r" (ds));
  92         asm("movl %%cs,%0" : "=r" (cs));
  93         asm("movl %%es,%0" : "=r" (es));
  94         asm("movl %%fs,%0" : "=r" (fsindex));
  95         asm("movl %%gs,%0" : "=r" (gsindex));
  96
  97         rdmsrl(MSR_FS_BASE, fs);
  98         rdmsrl(MSR_GS_BASE, gs);
  99         rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
 100
 101         cr0 = read_cr0();
 102         cr2 = read_cr2();
 103         cr3 = __read_cr3();
 104         cr4 = __read_cr4();
 105
 106         printk(KERN_DEFAULT "FS:  %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
 107                fs, fsindex, gs, gsindex, shadowgs);
 108         printk(KERN_DEFAULT "CS:  %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
 109                         es, cr0);
 110         printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
 111                         cr4);
 112
 113         get_debugreg(d0, 0);
 114         get_debugreg(d1, 1);
 115         get_debugreg(d2, 2);
 116         get_debugreg(d3, 3);
 117         get_debugreg(d6, 6);
 118         get_debugreg(d7, 7);
 119
 120         /* Only print out debug registers if they are in their non-default state. */
 121         if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
 122             (d6 == DR6_RESERVED) && (d7 == 0x400))) {
 123                 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n",
 124                        d0, d1, d2);
 125                 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n",
 126                        d3, d6, d7);
 127         }
 128
 129         if (boot_cpu_has(X86_FEATURE_OSPKE))
 130                 printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru());
 131 }
 132
 133 void release_thread(struct task_struct *dead_task)
 134 {
 135         if (dead_task->mm) {
 136 #ifdef CONFIG_MODIFY_LDT_SYSCALL
 137                 if (dead_task->mm->context.ldt) {
 138                         pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
 139                                 dead_task->comm,
 140                                 dead_task->mm->context.ldt->entries,
 141                                 dead_task->mm->context.ldt->nr_entries);
 142                         BUG();
 143                 }
 144 #endif
 145         }
 146 }
 147
 148 enum which_selector {
 149         FS,
 150         GS
 151 };
 152
 153 /*
 154  * Saves the FS or GS base for an outgoing thread if FSGSBASE extensions are
 155  * not available.  The goal is to be reasonably fast on non-FSGSBASE systems.
 156  * It's forcibly inlined because it'll generate better code and this function
 157  * is hot.
 158  */
 159 static __always_inline void save_base_legacy(struct task_struct *prev_p,
 160                                              unsigned short selector,
 161                                              enum which_selector which)
 162 {
 163         if (likely(selector == 0)) {
 164                 /*
 165                  * On Intel (without X86_BUG_NULL_SEG), the segment base could
 166                  * be the pre-existing saved base or it could be zero.  On AMD
 167                  * (with X86_BUG_NULL_SEG), the segment base could be almost
 168                  * anything.
 169                  *
 170                  * This branch is very hot (it's hit twice on almost every
 171                  * context switch between 64-bit programs), and avoiding
 172                  * the RDMSR helps a lot, so we just assume that whatever
 173                  * value is already saved is correct.  This matches historical
 174                  * Linux behavior, so it won't break existing applications.
 175                  *
 176                  * To avoid leaking state, on non-X86_BUG_NULL_SEG CPUs, if we
 177                  * report that the base is zero, it needs to actually be zero:
 178                  * see the corresponding logic in load_seg_legacy.
 179                  */
 180         } else {
 181                 /*
 182                  * If the selector is 1, 2, or 3, then the base is zero on
 183                  * !X86_BUG_NULL_SEG CPUs and could be anything on
 184                  * X86_BUG_NULL_SEG CPUs.  In the latter case, Linux
 185                  * has never attempted to preserve the base across context
 186                  * switches.
 187                  *
 188                  * If selector > 3, then it refers to a real segment, and
 189                  * saving the base isn't necessary.
 190                  */
 191                 if (which == FS)
 192                         prev_p->thread.fsbase = 0;
 193                 else
 194                         prev_p->thread.gsbase = 0;
 195         }
 196 }
 197
 198 static __always_inline void save_fsgs(struct task_struct *task)
 199 {
 200         savesegment(fs, task->thread.fsindex);
 201         savesegment(gs, task->thread.gsindex);
 202         save_base_legacy(task, task->thread.fsindex, FS);
 203         save_base_legacy(task, task->thread.gsindex, GS);
 204 }
 205
 206 #if IS_ENABLED(CONFIG_KVM)
 207 /*
 208  * While a process is running,current->thread.fsbase and current->thread.gsbase
 209  * may not match the corresponding CPU registers (see save_base_legacy()). KVM
 210  * wants an efficient way to save and restore FSBASE and GSBASE.
 211  * When FSGSBASE extensions are enabled, this will have to use RD{FS,GS}BASE.
 212  */
 213 void save_fsgs_for_kvm(void)
 214 {
 215         save_fsgs(current);
 216 }
 217 EXPORT_SYMBOL_GPL(save_fsgs_for_kvm);
 218 #endif
 219
 220 static __always_inline void loadseg(enum which_selector which,
 221                                     unsigned short sel)
 222 {
 223         if (which == FS)
 224                 loadsegment(fs, sel);
 225         else
 226                 load_gs_index(sel);
 227 }
 228
 229 static __always_inline void load_seg_legacy(unsigned short prev_index,
 230                                             unsigned long prev_base,
 231                                             unsigned short next_index,
 232                                             unsigned long next_base,
 233                                             enum which_selector which)
 234 {
 235         if (likely(next_index <= 3)) {
 236                 /*
 237                  * The next task is using 64-bit TLS, is not using this
 238                  * segment at all, or is having fun with arcane CPU features.
 239                  */
 240                 if (next_base == 0) {
 241                         /*
 242                          * Nasty case: on AMD CPUs, we need to forcibly zero
 243                          * the base.
 244                          */
 245                         if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
 246                                 loadseg(which, __USER_DS);
 247                                 loadseg(which, next_index);
 248                         } else {
 249                                 /*
 250                                  * We could try to exhaustively detect cases
 251                                  * under which we can skip the segment load,
 252                                  * but there's really only one case that matters
 253                                  * for performance: if both the previous and
 254                                  * next states are fully zeroed, we can skip
 255                                  * the load.
 256                                  *
 257                                  * (This assumes that prev_base == 0 has no
 258                                  * false positives.  This is the case on
 259                                  * Intel-style CPUs.)
 260                                  */
 261                                 if (likely(prev_index | next_index | prev_base))
 262                                         loadseg(which, next_index);
 263                         }
 264                 } else {
 265                         if (prev_index != next_index)
 266                                 loadseg(which, next_index);
 267                         wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,
 268                                next_base);
 269                 }
 270         } else {
 271                 /*
 272                  * The next task is using a real segment.  Loading the selector
 273                  * is sufficient.
 274                  */
 275                 loadseg(which, next_index);
 276         }
 277 }
 278
 279 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
 280                 unsigned long arg, struct task_struct *p, unsigned long tls)
 281 {
 282         int err;
 283         struct pt_regs *childregs;
 284         struct fork_frame *fork_frame;
 285         struct inactive_task_frame *frame;
 286         struct task_struct *me = current;
 287
 288         childregs = task_pt_regs(p);
 289         fork_frame = container_of(childregs, struct fork_frame, regs);
 290         frame = &fork_frame->frame;
 291         frame->bp = 0;
 292         frame->ret_addr = (unsigned long) ret_from_fork;
 293         p->thread.sp = (unsigned long) fork_frame;
 294         p->thread.io_bitmap_ptr = NULL;
 295
 296         savesegment(gs, p->thread.gsindex);
 297         p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
 298         savesegment(fs, p->thread.fsindex);
 299         p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
 300         savesegment(es, p->thread.es);
 301         savesegment(ds, p->thread.ds);
 302         memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
 303
 304         if (unlikely(p->flags & PF_KTHREAD)) {
 305                 /* kernel thread */
 306                 memset(childregs, 0, sizeof(struct pt_regs));
 307                 frame->bx = sp;         /* function */
 308                 frame->r12 = arg;
 309                 return 0;
 310         }
 311         frame->bx = 0;
 312         *childregs = *current_pt_regs();
 313
 314         childregs->ax = 0;
 315         if (sp)
 316                 childregs->sp = sp;
 317
 318         err = -ENOMEM;
 319         if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
 320                 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
 321                                                   IO_BITMAP_BYTES, GFP_KERNEL);
 322                 if (!p->thread.io_bitmap_ptr) {
 323                         p->thread.io_bitmap_max = 0;
 324                         return -ENOMEM;
 325                 }
 326                 set_tsk_thread_flag(p, TIF_IO_BITMAP);
 327         }
 328
 329         /*
 330          * Set a new TLS for the child thread?
 331          */
 332         if (clone_flags & CLONE_SETTLS) {
 333 #ifdef CONFIG_IA32_EMULATION
 334                 if (in_ia32_syscall())
 335                         err = do_set_thread_area(p, -1,
 336                                 (struct user_desc __user *)tls, 0);
 337                 else
 338 #endif
 339                         err = do_arch_prctl_64(p, ARCH_SET_FS, tls);
 340                 if (err)
 341                         goto out;
 342         }
 343         err = 0;
 344 out:
 345         if (err && p->thread.io_bitmap_ptr) {
 346                 kfree(p->thread.io_bitmap_ptr);
 347                 p->thread.io_bitmap_max = 0;
 348         }
 349
 350         return err;
 351 }
 352
 353 static void
 354 start_thread_common(struct pt_regs *regs, unsigned long new_ip,
 355                     unsigned long new_sp,
 356                     unsigned int _cs, unsigned int _ss, unsigned int _ds)
 357 {
 358         WARN_ON_ONCE(regs != current_pt_regs());
 359
 360         if (static_cpu_has(X86_BUG_NULL_SEG)) {
 361                 /* Loading zero below won't clear the base. */
 362                 loadsegment(fs, __USER_DS);
 363                 load_gs_index(__USER_DS);
 364         }
 365
 366         loadsegment(fs, 0);
 367         loadsegment(es, _ds);
 368         loadsegment(ds, _ds);
 369         load_gs_index(0);
 370
 371         regs->ip                = new_ip;
 372         regs->sp                = new_sp;
 373         regs->cs                = _cs;
 374         regs->ss                = _ss;
 375         regs->flags             = X86_EFLAGS_IF;
 376         force_iret();
 377 }
 378
 379 void
 380 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
 381 {
 382         start_thread_common(regs, new_ip, new_sp,
 383                             __USER_CS, __USER_DS, 0);
 384 }
 385 EXPORT_SYMBOL_GPL(start_thread);
 386
 387 #ifdef CONFIG_COMPAT
 388 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
 389 {
 390         start_thread_common(regs, new_ip, new_sp,
 391                             test_thread_flag(TIF_X32)
 392                             ? __USER_CS : __USER32_CS,
 393                             __USER_DS, __USER_DS);
 394 }
 395 #endif
 396
 397 /*
 398  *      switch_to(x,y) should switch tasks from x to y.
 399  *
 400  * This could still be optimized:
 401  * - fold all the options into a flag word and test it with a single test.
 402  * - could test fs/gs bitsliced
 403  *
 404  * Kprobes not supported here. Set the probe on schedule instead.
 405  * Function graph tracer not supported too.
 406  */
 407 __visible __notrace_funcgraph struct task_struct *
 408 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 409 {
 410         struct thread_struct *prev = &prev_p->thread;
 411         struct thread_struct *next = &next_p->thread;
 412         struct fpu *prev_fpu = &prev->fpu;
 413         struct fpu *next_fpu = &next->fpu;
 414         int cpu = smp_processor_id();
 415         struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu);
 416
 417         WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
 418                      this_cpu_read(irq_count) != -1);
 419
 420         switch_fpu_prepare(prev_fpu, cpu);
 421
 422         /* We must save %fs and %gs before load_TLS() because
 423          * %fs and %gs may be cleared by load_TLS().
 424          *
 425          * (e.g. xen_load_tls())
 426          */
 427         save_fsgs(prev_p);
 428
 429         /*
 430          * Load TLS before restoring any segments so that segment loads
 431          * reference the correct GDT entries.
 432          */
 433         load_TLS(next, cpu);
 434
 435         /*
 436          * Leave lazy mode, flushing any hypercalls made here.  This
 437          * must be done after loading TLS entries in the GDT but before
 438          * loading segments that might reference them, and and it must
 439          * be done before fpu__restore(), so the TS bit is up to
 440          * date.
 441          */
 442         arch_end_context_switch(next_p);
 443
 444         /* Switch DS and ES.
 445          *
 446          * Reading them only returns the selectors, but writing them (if
 447          * nonzero) loads the full descriptor from the GDT or LDT.  The
 448          * LDT for next is loaded in switch_mm, and the GDT is loaded
 449          * above.
 450          *
 451          * We therefore need to write new values to the segment
 452          * registers on every context switch unless both the new and old
 453          * values are zero.
 454          *
 455          * Note that we don't need to do anything for CS and SS, as
 456          * those are saved and restored as part of pt_regs.
 457          */
 458         savesegment(es, prev->es);
 459         if (unlikely(next->es | prev->es))
 460                 loadsegment(es, next->es);
 461
 462         savesegment(ds, prev->ds);
 463         if (unlikely(next->ds | prev->ds))
 464                 loadsegment(ds, next->ds);
 465
 466         load_seg_legacy(prev->fsindex, prev->fsbase,
 467                         next->fsindex, next->fsbase, FS);
 468         load_seg_legacy(prev->gsindex, prev->gsbase,
 469                         next->gsindex, next->gsbase, GS);
 470
 471         switch_fpu_finish(next_fpu, cpu);
 472
 473         /*
 474          * Switch the PDA and FPU contexts.
 475          */
 476         this_cpu_write(current_task, next_p);
 477         this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p));
 478
 479         /* Reload sp0. */
 480         update_task_stack(next_p);
 481
 482         /*
 483          * Now maybe reload the debug registers and handle I/O bitmaps
 484          */
 485         if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
 486                      task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
 487                 __switch_to_xtra(prev_p, next_p, tss);
 488
 489 #ifdef CONFIG_XEN_PV
 490         /*
 491          * On Xen PV, IOPL bits in pt_regs->flags have no effect, and
 492          * current_pt_regs()->flags may not match the current task's
 493          * intended IOPL.  We need to switch it manually.
 494          */
 495         if (unlikely(static_cpu_has(X86_FEATURE_XENPV) &&
 496                      prev->iopl != next->iopl))
 497                 xen_set_iopl_mask(next->iopl);
 498 #endif
 499
 500         if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
 501                 /*
 502                  * AMD CPUs have a misfeature: SYSRET sets the SS selector but
 503                  * does not update the cached descriptor.  As a result, if we
 504                  * do SYSRET while SS is NULL, we'll end up in user mode with
 505                  * SS apparently equal to __USER_DS but actually unusable.
 506                  *
 507                  * The straightforward workaround would be to fix it up just
 508                  * before SYSRET, but that would slow down the system call
 509                  * fast paths.  Instead, we ensure that SS is never NULL in
 510                  * system call context.  We do this by replacing NULL SS
 511                  * selectors at every context switch.  SYSCALL sets up a valid
 512                  * SS, so the only way to get NULL is to re-enter the kernel
 513                  * from CPL 3 through an interrupt.  Since that can't happen
 514                  * in the same task as a running syscall, we are guaranteed to
 515                  * context switch between every interrupt vector entry and a
 516                  * subsequent SYSRET.
 517                  *
 518                  * We read SS first because SS reads are much faster than
 519                  * writes.  Out of caution, we force SS to __KERNEL_DS even if
 520                  * it previously had a different non-NULL value.
 521                  */
 522                 unsigned short ss_sel;
 523                 savesegment(ss, ss_sel);
 524                 if (ss_sel != __KERNEL_DS)
 525                         loadsegment(ss, __KERNEL_DS);
 526         }
 527
 528         /* Load the Intel cache allocation PQR MSR. */
 529         intel_rdt_sched_in();
 530
 531         return prev_p;
 532 }
 533
 534 void set_personality_64bit(void)
 535 {
 536         /* inherit personality from parent */
 537
 538         /* Make sure to be in 64bit mode */
 539         clear_thread_flag(TIF_IA32);
 540         clear_thread_flag(TIF_ADDR32);
 541         clear_thread_flag(TIF_X32);
 542         /* Pretend that this comes from a 64bit execve */
 543         task_pt_regs(current)->orig_ax = __NR_execve;
 544         current_thread_info()->status &= ~TS_COMPAT;
 545
 546         /* Ensure the corresponding mm is not marked. */
 547         if (current->mm)
 548                 current->mm->context.ia32_compat = 0;
 549
 550         /* TBD: overwrites user setup. Should have two bits.
 551            But 64bit processes have always behaved this way,
 552            so it's not too bad. The main problem is just that
 553            32bit childs are affected again. */
 554         current->personality &= ~READ_IMPLIES_EXEC;
 555 }
 556
 557 static void __set_personality_x32(void)
 558 {
 559 #ifdef CONFIG_X86_X32
 560         clear_thread_flag(TIF_IA32);
 561         set_thread_flag(TIF_X32);
 562         if (current->mm)
 563                 current->mm->context.ia32_compat = TIF_X32;
 564         current->personality &= ~READ_IMPLIES_EXEC;
 565         /*
 566          * in_compat_syscall() uses the presence of the x32 syscall bit
 567          * flag to determine compat status.  The x86 mmap() code relies on
 568          * the syscall bitness so set x32 syscall bit right here to make
 569          * in_compat_syscall() work during exec().
 570          *
 571          * Pretend to come from a x32 execve.
 572          */
 573         task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT;
 574         current_thread_info()->status &= ~TS_COMPAT;
 575 #endif
 576 }
 577
 578 static void __set_personality_ia32(void)
 579 {
 580 #ifdef CONFIG_IA32_EMULATION
 581         set_thread_flag(TIF_IA32);
 582         clear_thread_flag(TIF_X32);
 583         if (current->mm)
 584                 current->mm->context.ia32_compat = TIF_IA32;
 585         current->personality |= force_personality32;
 586         /* Prepare the first "return" to user space */
 587         task_pt_regs(current)->orig_ax = __NR_ia32_execve;
 588         current_thread_info()->status |= TS_COMPAT;
 589 #endif
 590 }
 591
 592 void set_personality_ia32(bool x32)
 593 {
 594         /* Make sure to be in 32bit mode */
 595         set_thread_flag(TIF_ADDR32);
 596
 597         if (x32)
 598                 __set_personality_x32();
 599         else
 600                 __set_personality_ia32();
 601 }
 602 EXPORT_SYMBOL_GPL(set_personality_ia32);
 603
 604 #ifdef CONFIG_CHECKPOINT_RESTORE
 605 static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr)
 606 {
 607         int ret;
 608
 609         ret = map_vdso_once(image, addr);
 610         if (ret)
 611                 return ret;
 612
 613         return (long)image->size;
 614 }
 615 #endif
 616
 617 long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
 618 {
 619         int ret = 0;
 620         int doit = task == current;
 621         int cpu;
 622
 623         switch (option) {
 624         case ARCH_SET_GS:
 625                 if (arg2 >= TASK_SIZE_MAX)
 626                         return -EPERM;
 627                 cpu = get_cpu();
 628                 task->thread.gsindex = 0;
 629                 task->thread.gsbase = arg2;
 630                 if (doit) {
 631                         load_gs_index(0);
 632                         ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, arg2);
 633                 }
 634                 put_cpu();
 635                 break;
 636         case ARCH_SET_FS:
 637                 /* Not strictly needed for fs, but do it for symmetry
 638                    with gs */
 639                 if (arg2 >= TASK_SIZE_MAX)
 640                         return -EPERM;
 641                 cpu = get_cpu();
 642                 task->thread.fsindex = 0;
 643                 task->thread.fsbase = arg2;
 644                 if (doit) {
 645                         /* set the selector to 0 to not confuse __switch_to */
 646                         loadsegment(fs, 0);
 647                         ret = wrmsrl_safe(MSR_FS_BASE, arg2);
 648                 }
 649                 put_cpu();
 650                 break;
 651         case ARCH_GET_FS: {
 652                 unsigned long base;
 653
 654                 if (doit)
 655                         rdmsrl(MSR_FS_BASE, base);
 656                 else
 657                         base = task->thread.fsbase;
 658                 ret = put_user(base, (unsigned long __user *)arg2);
 659                 break;
 660         }
 661         case ARCH_GET_GS: {
 662                 unsigned long base;
 663
 664                 if (doit)
 665                         rdmsrl(MSR_KERNEL_GS_BASE, base);
 666                 else
 667                         base = task->thread.gsbase;
 668                 ret = put_user(base, (unsigned long __user *)arg2);
 669                 break;
 670         }
 671
 672 #ifdef CONFIG_CHECKPOINT_RESTORE
 673 # ifdef CONFIG_X86_X32_ABI
 674         case ARCH_MAP_VDSO_X32:
 675                 return prctl_map_vdso(&vdso_image_x32, arg2);
 676 # endif
 677 # if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
 678         case ARCH_MAP_VDSO_32:
 679                 return prctl_map_vdso(&vdso_image_32, arg2);
 680 # endif
 681         case ARCH_MAP_VDSO_64:
 682                 return prctl_map_vdso(&vdso_image_64, arg2);
 683 #endif
 684
 685         default:
 686                 ret = -EINVAL;
 687                 break;
 688         }
 689
 690         return ret;
 691 }
 692
 693 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
 694 {
 695         long ret;
 696
 697         ret = do_arch_prctl_64(current, option, arg2);
 698         if (ret == -EINVAL)
 699                 ret = do_arch_prctl_common(current, option, arg2);
 700
 701         return ret;
 702 }
 703
 704 #ifdef CONFIG_IA32_EMULATION
 705 COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
 706 {
 707         return do_arch_prctl_common(current, option, arg2);
 708 }
 709 #endif
 710
 711 unsigned long KSTK_ESP(struct task_struct *task)
 712 {
 713         return task_pt_regs(task)->sp;
 714 }