1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
59 #include <linux/stackprotector.h>
62 #include <asm/cacheinfo.h>
66 #include <asm/realmode.h>
69 #include <asm/tlbflush.h>
71 #include <asm/mwait.h>
73 #include <asm/io_apic.h>
74 #include <asm/fpu/api.h>
75 #include <asm/setup.h>
76 #include <asm/uv/uv.h>
77 #include <linux/mc146818rtc.h>
78 #include <asm/i8259.h>
80 #include <asm/qspinlock.h>
81 #include <asm/intel-family.h>
82 #include <asm/cpu_device_id.h>
83 #include <asm/spec-ctrl.h>
84 #include <asm/hw_irq.h>
85 #include <asm/stackprotector.h>
88 /* representing HT siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
92 /* representing HT and core siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
94 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
96 /* representing HT, core, and die siblings of each logical CPU */
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_die_map
);
98 EXPORT_PER_CPU_SYMBOL(cpu_die_map
);
100 /* Per CPU bogomips and other parameters */
101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
102 EXPORT_PER_CPU_SYMBOL(cpu_info
);
104 /* Logical package management. We might want to allocate that dynamically */
105 unsigned int __max_logical_packages __read_mostly
;
106 EXPORT_SYMBOL(__max_logical_packages
);
107 static unsigned int logical_packages __read_mostly
;
108 static unsigned int logical_die __read_mostly
;
110 /* Maximum number of SMT threads on any online core */
111 int __read_mostly __max_smt_threads
= 1;
113 /* Flag to indicate if a complete sched domain rebuild is required */
114 bool x86_topology_update
;
116 int arch_update_cpu_topology(void)
118 int retval
= x86_topology_update
;
120 x86_topology_update
= false;
124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
128 spin_lock_irqsave(&rtc_lock
, flags
);
129 CMOS_WRITE(0xa, 0xf);
130 spin_unlock_irqrestore(&rtc_lock
, flags
);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
137 static inline void smpboot_restore_warm_reset_vector(void)
142 * Paranoid: Set warm reset code and vector here back
145 spin_lock_irqsave(&rtc_lock
, flags
);
147 spin_unlock_irqrestore(&rtc_lock
, flags
);
149 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
153 * Report back to the Boot Processor during boot time or to the caller processor
156 static void smp_callin(void)
161 * If waken up by an INIT in an 82489DX configuration
162 * cpu_callout_mask guarantees we don't get here before
163 * an INIT_deassert IPI reaches our local APIC, so it is
164 * now safe to touch our local APIC.
166 cpuid
= smp_processor_id();
169 * the boot CPU has finished the init stage and is spinning
170 * on callin_map until we finish. We are free to set up this
171 * CPU, first the APIC. (this is probably redundant on most
177 * Save our processor parameters. Note: this information
178 * is needed for clock calibration.
180 smp_store_cpu_info(cpuid
);
183 * The topology information must be up to date before
184 * calibrate_delay() and notify_cpu_starting().
186 set_cpu_sibling_map(raw_smp_processor_id());
188 ap_init_aperfmperf();
192 * Update loops_per_jiffy in cpu_data. Previous call to
193 * smp_store_cpu_info() stored a value that is close but not as
194 * accurate as the value just calculated.
197 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
198 pr_debug("Stack at about %p\n", &cpuid
);
202 notify_cpu_starting(cpuid
);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
210 static int cpu0_logical_apicid
;
211 static int enable_start_cpu0
;
213 * Activate a secondary processor.
215 static void notrace
start_secondary(void *unused
)
218 * Don't put *anything* except direct CPU state initialization
219 * before cpu_init(), SMP booting is too fragile that we want to
220 * limit the things done here to the most necessary things.
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir
);
229 cpu_init_secondary();
230 rcu_cpu_starting(raw_smp_processor_id());
231 x86_cpuinit
.early_percpu_clock_init();
234 enable_start_cpu0
= 0;
236 /* otherwise gcc will move up smp_processor_id before the cpu_init */
239 * Check TSC synchronization with the boot CPU:
241 check_tsc_sync_target();
243 speculative_store_bypass_ht_init();
246 * Lock vector_lock, set CPU online and bring the vector
247 * allocator online. Online must be set with vector_lock held
248 * to prevent a concurrent irq setup/teardown from seeing a
249 * half valid vector space.
252 set_cpu_online(smp_processor_id(), true);
254 unlock_vector_lock();
255 cpu_set_state_online(smp_processor_id());
256 x86_platform
.nmi_init();
258 /* enable local interrupts */
261 x86_cpuinit
.setup_percpu_clockev();
264 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
268 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
271 bool topology_is_primary_thread(unsigned int cpu
)
273 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid
, cpu
));
277 * topology_smt_supported - Check whether SMT is supported by the CPUs
279 bool topology_smt_supported(void)
281 return smp_num_siblings
> 1;
285 * topology_phys_to_logical_pkg - Map a physical package id to a logical
287 * Returns logical package id or -1 if not found
289 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
293 for_each_possible_cpu(cpu
) {
294 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
296 if (c
->initialized
&& c
->phys_proc_id
== phys_pkg
)
297 return c
->logical_proc_id
;
301 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
303 * topology_phys_to_logical_die - Map a physical die id to logical
305 * Returns logical die id or -1 if not found
307 int topology_phys_to_logical_die(unsigned int die_id
, unsigned int cur_cpu
)
310 int proc_id
= cpu_data(cur_cpu
).phys_proc_id
;
312 for_each_possible_cpu(cpu
) {
313 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
315 if (c
->initialized
&& c
->cpu_die_id
== die_id
&&
316 c
->phys_proc_id
== proc_id
)
317 return c
->logical_die_id
;
321 EXPORT_SYMBOL(topology_phys_to_logical_die
);
324 * topology_update_package_map - Update the physical to logical package map
325 * @pkg: The physical package id as retrieved via CPUID
326 * @cpu: The cpu for which this is updated
328 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
332 /* Already available somewhere? */
333 new = topology_phys_to_logical_pkg(pkg
);
337 new = logical_packages
++;
339 pr_info("CPU %u Converting physical %u to logical package %u\n",
343 cpu_data(cpu
).logical_proc_id
= new;
347 * topology_update_die_map - Update the physical to logical die map
348 * @die: The die id as retrieved via CPUID
349 * @cpu: The cpu for which this is updated
351 int topology_update_die_map(unsigned int die
, unsigned int cpu
)
355 /* Already available somewhere? */
356 new = topology_phys_to_logical_die(die
, cpu
);
362 pr_info("CPU %u Converting physical %u to logical die %u\n",
366 cpu_data(cpu
).logical_die_id
= new;
370 void __init
smp_store_boot_cpu_info(void)
372 int id
= 0; /* CPU 0 */
373 struct cpuinfo_x86
*c
= &cpu_data(id
);
377 topology_update_package_map(c
->phys_proc_id
, id
);
378 topology_update_die_map(c
->cpu_die_id
, id
);
379 c
->initialized
= true;
383 * The bootstrap kernel entry code has set these up. Save them for
386 void smp_store_cpu_info(int id
)
388 struct cpuinfo_x86
*c
= &cpu_data(id
);
390 /* Copy boot_cpu_data only on the first bringup */
395 * During boot time, CPU0 has this setup already. Save the info when
396 * bringing up AP or offlined CPU0.
398 identify_secondary_cpu(c
);
399 c
->initialized
= true;
403 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
405 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
407 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
411 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
413 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
415 return !WARN_ONCE(!topology_same_node(c
, o
),
416 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
417 "[node: %d != %d]. Ignoring dependency.\n",
418 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
421 #define link_mask(mfunc, c1, c2) \
423 cpumask_set_cpu((c1), mfunc(c2)); \
424 cpumask_set_cpu((c2), mfunc(c1)); \
427 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
429 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
430 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
432 if (c
->phys_proc_id
== o
->phys_proc_id
&&
433 c
->cpu_die_id
== o
->cpu_die_id
&&
434 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
435 if (c
->cpu_core_id
== o
->cpu_core_id
)
436 return topology_sane(c
, o
, "smt");
438 if ((c
->cu_id
!= 0xff) &&
439 (o
->cu_id
!= 0xff) &&
440 (c
->cu_id
== o
->cu_id
))
441 return topology_sane(c
, o
, "smt");
444 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
445 c
->cpu_die_id
== o
->cpu_die_id
&&
446 c
->cpu_core_id
== o
->cpu_core_id
) {
447 return topology_sane(c
, o
, "smt");
453 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
455 if (c
->phys_proc_id
== o
->phys_proc_id
&&
456 c
->cpu_die_id
== o
->cpu_die_id
)
461 static bool match_l2c(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
463 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
465 /* If the arch didn't set up l2c_id, fall back to SMT */
466 if (per_cpu(cpu_l2c_id
, cpu1
) == BAD_APICID
)
467 return match_smt(c
, o
);
469 /* Do not match if L2 cache id does not match: */
470 if (per_cpu(cpu_l2c_id
, cpu1
) != per_cpu(cpu_l2c_id
, cpu2
))
473 return topology_sane(c
, o
, "l2c");
477 * Unlike the other levels, we do not enforce keeping a
478 * multicore group inside a NUMA node. If this happens, we will
479 * discard the MC level of the topology later.
481 static bool match_pkg(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
483 if (c
->phys_proc_id
== o
->phys_proc_id
)
489 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
491 * Any Intel CPU that has multiple nodes per package and does not
492 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
494 * When in SNC mode, these CPUs enumerate an LLC that is shared
495 * by multiple NUMA nodes. The LLC is shared for off-package data
496 * access but private to the NUMA node (half of the package) for
497 * on-package access. CPUID (the source of the information about
498 * the LLC) can only enumerate the cache as shared or unshared,
499 * but not this particular configuration.
502 static const struct x86_cpu_id intel_cod_cpu
[] = {
503 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X
, 0), /* COD */
504 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X
, 0), /* COD */
505 X86_MATCH_INTEL_FAM6_MODEL(ANY
, 1), /* SNC */
509 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
511 const struct x86_cpu_id
*id
= x86_match_cpu(intel_cod_cpu
);
512 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
513 bool intel_snc
= id
&& id
->driver_data
;
515 /* Do not match if we do not have a valid APICID for cpu: */
516 if (per_cpu(cpu_llc_id
, cpu1
) == BAD_APICID
)
519 /* Do not match if LLC id does not match: */
520 if (per_cpu(cpu_llc_id
, cpu1
) != per_cpu(cpu_llc_id
, cpu2
))
524 * Allow the SNC topology without warning. Return of false
525 * means 'c' does not share the LLC of 'o'. This will be
526 * reflected to userspace.
528 if (match_pkg(c
, o
) && !topology_same_node(c
, o
) && intel_snc
)
531 return topology_sane(c
, o
, "llc");
535 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC)
536 static inline int x86_sched_itmt_flags(void)
538 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
541 #ifdef CONFIG_SCHED_MC
542 static int x86_core_flags(void)
544 return cpu_core_flags() | x86_sched_itmt_flags();
547 #ifdef CONFIG_SCHED_SMT
548 static int x86_smt_flags(void)
550 return cpu_smt_flags() | x86_sched_itmt_flags();
553 #ifdef CONFIG_SCHED_CLUSTER
554 static int x86_cluster_flags(void)
556 return cpu_cluster_flags() | x86_sched_itmt_flags();
561 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
562 #ifdef CONFIG_SCHED_SMT
563 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
565 #ifdef CONFIG_SCHED_CLUSTER
566 { cpu_clustergroup_mask
, x86_cluster_flags
, SD_INIT_NAME(CLS
) },
568 #ifdef CONFIG_SCHED_MC
569 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
574 static struct sched_domain_topology_level x86_hybrid_topology
[] = {
575 #ifdef CONFIG_SCHED_SMT
576 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
578 #ifdef CONFIG_SCHED_MC
579 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
581 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
585 static struct sched_domain_topology_level x86_topology
[] = {
586 #ifdef CONFIG_SCHED_SMT
587 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
589 #ifdef CONFIG_SCHED_CLUSTER
590 { cpu_clustergroup_mask
, x86_cluster_flags
, SD_INIT_NAME(CLS
) },
592 #ifdef CONFIG_SCHED_MC
593 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
595 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
600 * Set if a package/die has multiple NUMA nodes inside.
601 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
602 * Sub-NUMA Clustering have this.
604 static bool x86_has_numa_in_package
;
606 void set_cpu_sibling_map(int cpu
)
608 bool has_smt
= smp_num_siblings
> 1;
609 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
610 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
611 struct cpuinfo_x86
*o
;
614 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
617 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
618 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
619 cpumask_set_cpu(cpu
, cpu_l2c_shared_mask(cpu
));
620 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
621 cpumask_set_cpu(cpu
, topology_die_cpumask(cpu
));
626 for_each_cpu(i
, cpu_sibling_setup_mask
) {
629 if (match_pkg(c
, o
) && !topology_same_node(c
, o
))
630 x86_has_numa_in_package
= true;
632 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
633 link_mask(topology_sibling_cpumask
, cpu
, i
);
635 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
636 link_mask(cpu_llc_shared_mask
, cpu
, i
);
638 if ((i
== cpu
) || (has_mp
&& match_l2c(c
, o
)))
639 link_mask(cpu_l2c_shared_mask
, cpu
, i
);
641 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
)))
642 link_mask(topology_die_cpumask
, cpu
, i
);
645 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
646 if (threads
> __max_smt_threads
)
647 __max_smt_threads
= threads
;
649 for_each_cpu(i
, topology_sibling_cpumask(cpu
))
650 cpu_data(i
).smt_active
= threads
> 1;
653 * This needs a separate iteration over the cpus because we rely on all
654 * topology_sibling_cpumask links to be set-up.
656 for_each_cpu(i
, cpu_sibling_setup_mask
) {
659 if ((i
== cpu
) || (has_mp
&& match_pkg(c
, o
))) {
660 link_mask(topology_core_cpumask
, cpu
, i
);
663 * Does this new cpu bringup a new core?
667 * for each core in package, increment
668 * the booted_cores for this new cpu
671 topology_sibling_cpumask(i
)) == i
)
674 * increment the core count for all
675 * the other cpus in this package
678 cpu_data(i
).booted_cores
++;
679 } else if (i
!= cpu
&& !c
->booted_cores
)
680 c
->booted_cores
= cpu_data(i
).booted_cores
;
685 /* maps the cpu to the sched domain representing multi-core */
686 const struct cpumask
*cpu_coregroup_mask(int cpu
)
688 return cpu_llc_shared_mask(cpu
);
691 const struct cpumask
*cpu_clustergroup_mask(int cpu
)
693 return cpu_l2c_shared_mask(cpu
);
696 static void impress_friends(void)
699 unsigned long bogosum
= 0;
701 * Allow the user to impress friends.
703 pr_debug("Before bogomips\n");
704 for_each_possible_cpu(cpu
)
705 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
706 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
707 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
710 (bogosum
/(5000/HZ
))%100);
712 pr_debug("Before bogocount - setting activated=1\n");
715 void __inquire_remote_apic(int apicid
)
717 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
718 const char * const names
[] = { "ID", "VERSION", "SPIV" };
722 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
724 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
725 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
730 status
= safe_apic_wait_icr_idle();
732 pr_cont("a previous APIC delivery may have failed\n");
734 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
739 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
740 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
743 case APIC_ICR_RR_VALID
:
744 status
= apic_read(APIC_RRR
);
745 pr_cont("%08x\n", status
);
754 * The Multiprocessor Specification 1.4 (1997) example code suggests
755 * that there should be a 10ms delay between the BSP asserting INIT
756 * and de-asserting INIT, when starting a remote processor.
757 * But that slows boot and resume on modern processors, which include
758 * many cores and don't require that delay.
760 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
761 * Modern processor families are quirked to remove the delay entirely.
763 #define UDELAY_10MS_DEFAULT 10000
765 static unsigned int init_udelay
= UINT_MAX
;
767 static int __init
cpu_init_udelay(char *str
)
769 get_option(&str
, &init_udelay
);
773 early_param("cpu_init_udelay", cpu_init_udelay
);
775 static void __init
smp_quirk_init_udelay(void)
777 /* if cmdline changed it from default, leave it alone */
778 if (init_udelay
!= UINT_MAX
)
781 /* if modern processor, use no delay */
782 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
783 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
) && (boot_cpu_data
.x86
>= 0x18)) ||
784 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
788 /* else, use legacy delay */
789 init_udelay
= UDELAY_10MS_DEFAULT
;
793 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
794 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
795 * won't ... remember to clear down the APIC, etc later.
798 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
800 u32 dm
= apic
->dest_mode_logical
? APIC_DEST_LOGICAL
: APIC_DEST_PHYSICAL
;
801 unsigned long send_status
, accept_status
= 0;
805 /* Boot on the stack */
806 /* Kick the second */
807 apic_icr_write(APIC_DM_NMI
| dm
, apicid
);
809 pr_debug("Waiting for send to finish...\n");
810 send_status
= safe_apic_wait_icr_idle();
813 * Give the other CPU some time to accept the IPI.
816 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
817 maxlvt
= lapic_get_maxlvt();
818 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
819 apic_write(APIC_ESR
, 0);
820 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
822 pr_debug("NMI sent\n");
825 pr_err("APIC never delivered???\n");
827 pr_err("APIC delivery error (%lx)\n", accept_status
);
829 return (send_status
| accept_status
);
833 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
835 unsigned long send_status
= 0, accept_status
= 0;
836 int maxlvt
, num_starts
, j
;
838 maxlvt
= lapic_get_maxlvt();
841 * Be paranoid about clearing APIC errors.
843 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
844 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
845 apic_write(APIC_ESR
, 0);
849 pr_debug("Asserting INIT\n");
852 * Turn INIT on target chip
857 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
860 pr_debug("Waiting for send to finish...\n");
861 send_status
= safe_apic_wait_icr_idle();
865 pr_debug("Deasserting INIT\n");
869 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
871 pr_debug("Waiting for send to finish...\n");
872 send_status
= safe_apic_wait_icr_idle();
877 * Should we send STARTUP IPIs ?
879 * Determine this based on the APIC version.
880 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
882 if (APIC_INTEGRATED(boot_cpu_apic_version
))
888 * Run STARTUP IPI loop.
890 pr_debug("#startup loops: %d\n", num_starts
);
892 for (j
= 1; j
<= num_starts
; j
++) {
893 pr_debug("Sending STARTUP #%d\n", j
);
894 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
895 apic_write(APIC_ESR
, 0);
897 pr_debug("After apic_write\n");
904 /* Boot on the stack */
905 /* Kick the second */
906 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
910 * Give the other CPU some time to accept the IPI.
912 if (init_udelay
== 0)
917 pr_debug("Startup point 1\n");
919 pr_debug("Waiting for send to finish...\n");
920 send_status
= safe_apic_wait_icr_idle();
923 * Give the other CPU some time to accept the IPI.
925 if (init_udelay
== 0)
930 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
931 apic_write(APIC_ESR
, 0);
932 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
933 if (send_status
|| accept_status
)
936 pr_debug("After Startup\n");
939 pr_err("APIC never delivered???\n");
941 pr_err("APIC delivery error (%lx)\n", accept_status
);
943 return (send_status
| accept_status
);
946 /* reduce the number of lines printed when booting a large cpu count system */
947 static void announce_cpu(int cpu
, int apicid
)
949 static int current_node
= NUMA_NO_NODE
;
950 int node
= early_cpu_to_node(cpu
);
951 static int width
, node_width
;
954 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
957 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
960 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
962 if (system_state
< SYSTEM_RUNNING
) {
963 if (node
!= current_node
) {
964 if (current_node
> (-1))
968 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
969 node_width
- num_digits(node
), " ", node
);
972 /* Add padding for the BSP */
974 pr_cont("%*s", width
+ 1, " ");
976 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
979 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
983 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
987 cpu
= smp_processor_id();
988 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
995 * Wake up AP by INIT, INIT, STARTUP sequence.
997 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
998 * boot-strap code which is not a desired behavior for waking up BSP. To
999 * void the boot-strap code, wake up CPU0 by NMI instead.
1001 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
1002 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
1003 * We'll change this code in the future to wake up hard offlined CPU0 if
1004 * real platform and request are available.
1007 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
1008 int *cpu0_nmi_registered
)
1016 * Wake up AP by INIT, INIT, STARTUP sequence.
1019 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
1024 * Wake up BSP by nmi.
1026 * Register a NMI handler to help wake up CPU0.
1028 boot_error
= register_nmi_handler(NMI_LOCAL
,
1029 wakeup_cpu0_nmi
, 0, "wake_cpu0");
1032 enable_start_cpu0
= 1;
1033 *cpu0_nmi_registered
= 1;
1034 id
= apic
->dest_mode_logical
? cpu0_logical_apicid
: apicid
;
1035 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
1044 int common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
1048 /* Just in case we booted with a single CPU. */
1049 alternatives_enable_smp();
1051 per_cpu(pcpu_hot
.current_task
, cpu
) = idle
;
1052 cpu_init_stack_canary(cpu
, idle
);
1054 /* Initialize the interrupt stack(s) */
1055 ret
= irq_init_percpu_irqstack(cpu
);
1059 #ifdef CONFIG_X86_32
1060 /* Stack for startup_32 can be just as for start_secondary onwards */
1061 per_cpu(pcpu_hot
.top_of_stack
, cpu
) = task_top_of_stack(idle
);
1063 initial_gs
= per_cpu_offset(cpu
);
1069 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1070 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1071 * Returns zero if CPU booted OK, else error code from
1072 * ->wakeup_secondary_cpu.
1074 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
1075 int *cpu0_nmi_registered
)
1077 /* start_ip had better be page-aligned! */
1078 unsigned long start_ip
= real_mode_header
->trampoline_start
;
1080 unsigned long boot_error
= 0;
1081 unsigned long timeout
;
1083 #ifdef CONFIG_X86_64
1084 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
1085 if (apic
->wakeup_secondary_cpu_64
)
1086 start_ip
= real_mode_header
->trampoline_start64
;
1088 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
1089 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
1090 initial_code
= (unsigned long)start_secondary
;
1091 initial_stack
= idle
->thread
.sp
;
1093 /* Enable the espfix hack for this CPU */
1094 init_espfix_ap(cpu
);
1096 /* So we see what's up */
1097 announce_cpu(cpu
, apicid
);
1100 * This grunge runs the startup process for
1101 * the targeted processor.
1104 if (x86_platform
.legacy
.warm_reset
) {
1106 pr_debug("Setting warm reset code and vector.\n");
1108 smpboot_setup_warm_reset_vector(start_ip
);
1110 * Be paranoid about clearing APIC errors.
1112 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1113 apic_write(APIC_ESR
, 0);
1114 apic_read(APIC_ESR
);
1119 * AP might wait on cpu_callout_mask in cpu_init() with
1120 * cpu_initialized_mask set if previous attempt to online
1121 * it timed-out. Clear cpu_initialized_mask so that after
1122 * INIT/SIPI it could start with a clean state.
1124 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1128 * Wake up a CPU in difference cases:
1129 * - Use a method from the APIC driver if one defined, with wakeup
1130 * straight to 64-bit mode preferred over wakeup to RM.
1132 * - Use an INIT boot APIC message for APs or NMI for BSP.
1134 if (apic
->wakeup_secondary_cpu_64
)
1135 boot_error
= apic
->wakeup_secondary_cpu_64(apicid
, start_ip
);
1136 else if (apic
->wakeup_secondary_cpu
)
1137 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1139 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1140 cpu0_nmi_registered
);
1144 * Wait 10s total for first sign of life from AP
1147 timeout
= jiffies
+ 10*HZ
;
1148 while (time_before(jiffies
, timeout
)) {
1149 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1151 * Tell AP to proceed with initialization
1153 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1163 * Wait till AP completes initial initialization
1165 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1167 * Allow other tasks to run while we wait for the
1168 * AP to come online. This also gives a chance
1169 * for the MTRR work(triggered by the AP coming online)
1170 * to be completed in the stop machine context.
1176 if (x86_platform
.legacy
.warm_reset
) {
1178 * Cleanup possible dangling ends...
1180 smpboot_restore_warm_reset_vector();
1186 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1188 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1189 int cpu0_nmi_registered
= 0;
1190 unsigned long flags
;
1193 lockdep_assert_irqs_enabled();
1195 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1197 if (apicid
== BAD_APICID
||
1198 !physid_isset(apicid
, phys_cpu_present_map
) ||
1199 !apic
->apic_id_valid(apicid
)) {
1200 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1205 * Already booted CPU?
1207 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1208 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1213 * Save current MTRR state in case it was changed since early boot
1214 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1218 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1219 err
= cpu_check_up_prepare(cpu
);
1220 if (err
&& err
!= -EBUSY
)
1223 /* the FPU context is blank, nobody can own it */
1224 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1226 err
= common_cpu_up(cpu
, tidle
);
1230 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1232 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1238 * Check TSC synchronization with the AP (keep irqs disabled
1241 local_irq_save(flags
);
1242 check_tsc_sync_source(cpu
);
1243 local_irq_restore(flags
);
1245 while (!cpu_online(cpu
)) {
1247 touch_nmi_watchdog();
1252 * Clean up the nmi handler. Do this after the callin and callout sync
1253 * to avoid impact of possible long unregister time.
1255 if (cpu0_nmi_registered
)
1256 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1262 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1264 void arch_disable_smp_support(void)
1266 disable_ioapic_support();
1270 * Fall back to non SMP mode after errors.
1272 * RED-PEN audit/test this more. I bet there is more state messed up here.
1274 static __init
void disable_smp(void)
1276 pr_info("SMP disabled\n");
1278 disable_ioapic_support();
1280 init_cpu_present(cpumask_of(0));
1281 init_cpu_possible(cpumask_of(0));
1283 if (smp_found_config
)
1284 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1286 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1287 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1288 cpumask_set_cpu(0, topology_core_cpumask(0));
1289 cpumask_set_cpu(0, topology_die_cpumask(0));
1293 * Various sanity checks.
1295 static void __init
smp_sanity_check(void)
1299 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1300 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1304 pr_warn("More than 8 CPUs detected - skipping them\n"
1305 "Use CONFIG_X86_BIGSMP\n");
1308 for_each_present_cpu(cpu
) {
1310 set_cpu_present(cpu
, false);
1315 for_each_possible_cpu(cpu
) {
1317 set_cpu_possible(cpu
, false);
1325 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1326 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1327 hard_smp_processor_id());
1329 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1333 * Should not be necessary because the MP table should list the boot
1334 * CPU too, but we do it for the sake of robustness anyway.
1336 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1337 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1338 boot_cpu_physical_apicid
);
1339 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1344 static void __init
smp_cpu_index_default(void)
1347 struct cpuinfo_x86
*c
;
1349 for_each_possible_cpu(i
) {
1351 /* mark all to hotplug */
1352 c
->cpu_index
= nr_cpu_ids
;
1356 static void __init
smp_get_logical_apicid(void)
1359 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1361 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1364 void __init
smp_prepare_cpus_common(void)
1368 smp_cpu_index_default();
1371 * Setup boot CPU information
1373 smp_store_boot_cpu_info(); /* Final full version of the data */
1374 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1377 for_each_possible_cpu(i
) {
1378 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1379 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1380 zalloc_cpumask_var(&per_cpu(cpu_die_map
, i
), GFP_KERNEL
);
1381 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1382 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map
, i
), GFP_KERNEL
);
1386 * Set 'default' x86 topology, this matches default_topology() in that
1387 * it has NUMA nodes as a topology level. See also
1388 * native_smp_cpus_done().
1390 * Must be done before set_cpus_sibling_map() is ran.
1392 set_sched_topology(x86_topology
);
1394 set_cpu_sibling_map(0);
1398 * Prepare for SMP bootup.
1399 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1400 * for common interface support.
1402 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1404 smp_prepare_cpus_common();
1408 switch (apic_intr_mode
) {
1410 case APIC_VIRTUAL_WIRE_NO_CONFIG
:
1413 case APIC_SYMMETRIC_IO_NO_ROUTING
:
1415 /* Setup local timer */
1416 x86_init
.timers
.setup_percpu_clockev();
1418 case APIC_VIRTUAL_WIRE
:
1419 case APIC_SYMMETRIC_IO
:
1423 /* Setup local timer */
1424 x86_init
.timers
.setup_percpu_clockev();
1426 smp_get_logical_apicid();
1429 print_cpu_info(&cpu_data(0));
1433 smp_quirk_init_udelay();
1435 speculative_store_bypass_ht_init();
1437 snp_set_wakeup_secondary_cpu();
1440 void arch_thaw_secondary_cpus_begin(void)
1442 set_cache_aps_delayed_init(true);
1445 void arch_thaw_secondary_cpus_end(void)
1451 * Early setup to make printk work.
1453 void __init
native_smp_prepare_boot_cpu(void)
1455 int me
= smp_processor_id();
1457 /* SMP handles this from setup_per_cpu_areas() */
1458 if (!IS_ENABLED(CONFIG_SMP
))
1459 switch_gdt_and_percpu_base(me
);
1461 /* already set me in cpu_online_mask in boot_cpu_init() */
1462 cpumask_set_cpu(me
, cpu_callout_mask
);
1463 cpu_set_state_online(me
);
1464 native_pv_lock_init();
1467 void __init
calculate_max_logical_packages(void)
1472 * Today neither Intel nor AMD support heterogeneous systems so
1473 * extrapolate the boot cpu's data to all packages.
1475 ncpus
= cpu_data(0).booted_cores
* topology_max_smt_threads();
1476 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
1477 pr_info("Max logical packages: %u\n", __max_logical_packages
);
1480 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1482 pr_debug("Boot done\n");
1484 calculate_max_logical_packages();
1486 /* XXX for now assume numa-in-package and hybrid don't overlap */
1487 if (x86_has_numa_in_package
)
1488 set_sched_topology(x86_numa_in_package_topology
);
1489 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU
))
1490 set_sched_topology(x86_hybrid_topology
);
1497 static int __initdata setup_possible_cpus
= -1;
1498 static int __init
_setup_possible_cpus(char *str
)
1500 get_option(&str
, &setup_possible_cpus
);
1503 early_param("possible_cpus", _setup_possible_cpus
);
1507 * cpu_possible_mask should be static, it cannot change as cpu's
1508 * are onlined, or offlined. The reason is per-cpu data-structures
1509 * are allocated by some modules at init time, and don't expect to
1510 * do this dynamically on cpu arrival/departure.
1511 * cpu_present_mask on the other hand can change dynamically.
1512 * In case when cpu_hotplug is not compiled, then we resort to current
1513 * behaviour, which is cpu_possible == cpu_present.
1516 * Three ways to find out the number of additional hotplug CPUs:
1517 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1518 * - The user can overwrite it with possible_cpus=NUM
1519 * - Otherwise don't reserve additional CPUs.
1520 * We do this because additional CPUs waste a lot of memory.
1523 __init
void prefill_possible_map(void)
1527 /* No boot processor was found in mptable or ACPI MADT */
1528 if (!num_processors
) {
1529 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1530 int apicid
= boot_cpu_physical_apicid
;
1531 int cpu
= hard_smp_processor_id();
1533 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1535 /* Make sure boot cpu is enumerated */
1536 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1537 apic
->apic_id_valid(apicid
))
1538 generic_processor_info(apicid
, boot_cpu_apic_version
);
1541 if (!num_processors
)
1545 i
= setup_max_cpus
?: 1;
1546 if (setup_possible_cpus
== -1) {
1547 possible
= num_processors
;
1548 #ifdef CONFIG_HOTPLUG_CPU
1550 possible
+= disabled_cpus
;
1556 possible
= setup_possible_cpus
;
1558 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1560 /* nr_cpu_ids could be reduced via nr_cpus= */
1561 if (possible
> nr_cpu_ids
) {
1562 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1563 possible
, nr_cpu_ids
);
1564 possible
= nr_cpu_ids
;
1567 #ifdef CONFIG_HOTPLUG_CPU
1568 if (!setup_max_cpus
)
1571 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1572 possible
, setup_max_cpus
);
1576 set_nr_cpu_ids(possible
);
1578 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1579 possible
, max_t(int, possible
- num_processors
, 0));
1581 reset_cpu_possible_mask();
1583 for (i
= 0; i
< possible
; i
++)
1584 set_cpu_possible(i
, true);
1587 #ifdef CONFIG_HOTPLUG_CPU
1589 /* Recompute SMT state for all CPUs on offline */
1590 static void recompute_smt_state(void)
1592 int max_threads
, cpu
;
1595 for_each_online_cpu (cpu
) {
1596 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1598 if (threads
> max_threads
)
1599 max_threads
= threads
;
1601 __max_smt_threads
= max_threads
;
1604 static void remove_siblinginfo(int cpu
)
1607 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1609 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1610 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1612 * last thread sibling in this cpu core going down
1614 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1615 cpu_data(sibling
).booted_cores
--;
1618 for_each_cpu(sibling
, topology_die_cpumask(cpu
))
1619 cpumask_clear_cpu(cpu
, topology_die_cpumask(sibling
));
1621 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
)) {
1622 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1623 if (cpumask_weight(topology_sibling_cpumask(sibling
)) == 1)
1624 cpu_data(sibling
).smt_active
= false;
1627 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1628 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1629 for_each_cpu(sibling
, cpu_l2c_shared_mask(cpu
))
1630 cpumask_clear_cpu(cpu
, cpu_l2c_shared_mask(sibling
));
1631 cpumask_clear(cpu_llc_shared_mask(cpu
));
1632 cpumask_clear(cpu_l2c_shared_mask(cpu
));
1633 cpumask_clear(topology_sibling_cpumask(cpu
));
1634 cpumask_clear(topology_core_cpumask(cpu
));
1635 cpumask_clear(topology_die_cpumask(cpu
));
1637 c
->booted_cores
= 0;
1638 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1639 recompute_smt_state();
1642 static void remove_cpu_from_maps(int cpu
)
1644 set_cpu_online(cpu
, false);
1645 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1646 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1647 /* was set by cpu_init() */
1648 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1649 numa_remove_cpu(cpu
);
1652 void cpu_disable_common(void)
1654 int cpu
= smp_processor_id();
1656 remove_siblinginfo(cpu
);
1658 /* It's now safe to remove this processor from the online map */
1660 remove_cpu_from_maps(cpu
);
1661 unlock_vector_lock();
1666 int native_cpu_disable(void)
1670 ret
= lapic_can_unplug_cpu();
1674 cpu_disable_common();
1677 * Disable the local APIC. Otherwise IPI broadcasts will reach
1678 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1681 * Disabling the APIC must happen after cpu_disable_common()
1682 * which invokes fixup_irqs().
1684 * Disabling the APIC preserves already set bits in IRR, but
1685 * an interrupt arriving after disabling the local APIC does not
1686 * set the corresponding IRR bit.
1688 * fixup_irqs() scans IRR for set bits so it can raise a not
1689 * yet handled interrupt on the new destination CPU via an IPI
1690 * but obviously it can't do so for IRR bits which are not set.
1691 * IOW, interrupts arriving after disabling the local APIC will
1694 apic_soft_disable();
1699 int common_cpu_die(unsigned int cpu
)
1703 /* We don't do anything here: idle task is faking death itself. */
1705 /* They ack this in play_dead() by setting CPU_DEAD */
1706 if (cpu_wait_death(cpu
, 5)) {
1707 if (system_state
== SYSTEM_RUNNING
)
1708 pr_info("CPU %u is now offline\n", cpu
);
1710 pr_err("CPU %u didn't die...\n", cpu
);
1717 void native_cpu_die(unsigned int cpu
)
1719 common_cpu_die(cpu
);
1722 void play_dead_common(void)
1727 (void)cpu_report_death();
1730 * With physical CPU hotplug, we should halt the cpu
1732 local_irq_disable();
1736 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1738 * If NMI wants to wake up CPU0, start CPU0.
1740 void cond_wakeup_cpu0(void)
1742 if (smp_processor_id() == 0 && enable_start_cpu0
)
1745 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0
);
1748 * We need to flush the caches before going to sleep, lest we have
1749 * dirty data in our caches when we come back up.
1751 static inline void mwait_play_dead(void)
1753 unsigned int eax
, ebx
, ecx
, edx
;
1754 unsigned int highest_cstate
= 0;
1755 unsigned int highest_subcstate
= 0;
1759 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
||
1760 boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
)
1762 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1764 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1766 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1769 eax
= CPUID_MWAIT_LEAF
;
1771 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1774 * eax will be 0 if EDX enumeration is not valid.
1775 * Initialized below to cstate, sub_cstate value when EDX is valid.
1777 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1780 edx
>>= MWAIT_SUBSTATE_SIZE
;
1781 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1782 if (edx
& MWAIT_SUBSTATE_MASK
) {
1784 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1787 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1788 (highest_subcstate
- 1);
1792 * This should be a memory location in a cache line which is
1793 * unlikely to be touched by other processors. The actual
1794 * content is immaterial as it is not actually modified in any way.
1796 mwait_ptr
= ¤t_thread_info()->flags
;
1802 * The CLFLUSH is a workaround for erratum AAI65 for
1803 * the Xeon 7400 series. It's not clear it is actually
1804 * needed, but it should be harmless in either case.
1805 * The WBINVD is insufficient due to the spurious-wakeup
1806 * case where we return around the loop.
1811 __monitor(mwait_ptr
, 0, 0);
1819 void hlt_play_dead(void)
1821 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1831 void native_play_dead(void)
1834 tboot_shutdown(TB_SHUTDOWN_WFS
);
1837 if (cpuidle_play_dead())
1841 #else /* ... !CONFIG_HOTPLUG_CPU */
1842 int native_cpu_disable(void)
1847 void native_cpu_die(unsigned int cpu
)
1849 /* We said "no" in __cpu_disable */
1853 void native_play_dead(void)