2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/qspinlock.h>
82 /* Number of siblings per CPU package */
83 int smp_num_siblings
= 1;
84 EXPORT_SYMBOL(smp_num_siblings
);
86 /* Last level cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
101 EXPORT_PER_CPU_SYMBOL(cpu_info
);
103 /* Logical package management. We might want to allocate that dynamically */
104 unsigned int __max_logical_packages __read_mostly
;
105 EXPORT_SYMBOL(__max_logical_packages
);
106 static unsigned int logical_packages __read_mostly
;
108 /* Maximum number of SMT threads on any online core */
109 int __read_mostly __max_smt_threads
= 1;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update
;
114 int arch_update_cpu_topology(void)
116 int retval
= x86_topology_update
;
118 x86_topology_update
= false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
126 spin_lock_irqsave(&rtc_lock
, flags
);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock
, flags
);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
139 static inline void smpboot_restore_warm_reset_vector(void)
144 * Install writable page 0 entry to set BIOS data area.
149 * Paranoid: Set warm reset code and vector here back
152 spin_lock_irqsave(&rtc_lock
, flags
);
154 spin_unlock_irqrestore(&rtc_lock
, flags
);
156 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
160 * Report back to the Boot Processor during boot time or to the caller processor
163 static void smp_callin(void)
168 * If waken up by an INIT in an 82489DX configuration
169 * cpu_callout_mask guarantees we don't get here before
170 * an INIT_deassert IPI reaches our local APIC, so it is
171 * now safe to touch our local APIC.
173 cpuid
= smp_processor_id();
176 * (This works even if the APIC is not enabled.)
178 phys_id
= read_apic_id();
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
189 * Save our processor parameters. Note: this information
190 * is needed for clock calibration.
192 smp_store_cpu_info(cpuid
);
195 * The topology information must be up to date before
196 * calibrate_delay() and notify_cpu_starting().
198 set_cpu_sibling_map(raw_smp_processor_id());
202 * Update loops_per_jiffy in cpu_data. Previous call to
203 * smp_store_cpu_info() stored a value that is close but not as
204 * accurate as the value just calculated.
207 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
208 pr_debug("Stack at about %p\n", &cpuid
);
212 notify_cpu_starting(cpuid
);
215 * Allow the master to continue.
217 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
220 static int cpu0_logical_apicid
;
221 static int enable_start_cpu0
;
223 * Activate a secondary processor.
225 static void notrace
start_secondary(void *unused
)
228 * Don't put *anything* except direct CPU state initialization
229 * before cpu_init(), SMP booting is too fragile that we want to
230 * limit the things done here to the most necessary things.
232 if (boot_cpu_has(X86_FEATURE_PCID
))
233 __write_cr4(__read_cr4() | X86_CR4_PCIDE
);
236 /* switch away from the initial page table */
237 load_cr3(swapper_pg_dir
);
242 x86_cpuinit
.early_percpu_clock_init();
246 enable_start_cpu0
= 0;
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the boot CPU:
253 check_tsc_sync_target();
256 * Lock vector_lock, set CPU online and bring the vector
257 * allocator online. Online must be set with vector_lock held
258 * to prevent a concurrent irq setup/teardown from seeing a
259 * half valid vector space.
262 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform
.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit
.setup_percpu_clockev();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
281 * topology_phys_to_logical_pkg - Map a physical package id to a logical
283 * Returns logical package id or -1 if not found
285 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
289 for_each_possible_cpu(cpu
) {
290 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
292 if (c
->initialized
&& c
->phys_proc_id
== phys_pkg
)
293 return c
->logical_proc_id
;
297 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
300 * topology_update_package_map - Update the physical to logical package map
301 * @pkg: The physical package id as retrieved via CPUID
302 * @cpu: The cpu for which this is updated
304 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
308 /* Already available somewhere? */
309 new = topology_phys_to_logical_pkg(pkg
);
313 new = logical_packages
++;
315 pr_info("CPU %u Converting physical %u to logical package %u\n",
319 cpu_data(cpu
).logical_proc_id
= new;
323 void __init
smp_store_boot_cpu_info(void)
325 int id
= 0; /* CPU 0 */
326 struct cpuinfo_x86
*c
= &cpu_data(id
);
330 topology_update_package_map(c
->phys_proc_id
, id
);
331 c
->initialized
= true;
335 * The bootstrap kernel entry code has set these up. Save them for
338 void smp_store_cpu_info(int id
)
340 struct cpuinfo_x86
*c
= &cpu_data(id
);
342 /* Copy boot_cpu_data only on the first bringup */
347 * During boot time, CPU0 has this setup already. Save the info when
348 * bringing up AP or offlined CPU0.
350 identify_secondary_cpu(c
);
351 c
->initialized
= true;
355 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
357 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
359 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
363 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
365 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
367 return !WARN_ONCE(!topology_same_node(c
, o
),
368 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
369 "[node: %d != %d]. Ignoring dependency.\n",
370 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
373 #define link_mask(mfunc, c1, c2) \
375 cpumask_set_cpu((c1), mfunc(c2)); \
376 cpumask_set_cpu((c2), mfunc(c1)); \
379 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
381 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
382 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
384 if (c
->phys_proc_id
== o
->phys_proc_id
&&
385 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
386 if (c
->cpu_core_id
== o
->cpu_core_id
)
387 return topology_sane(c
, o
, "smt");
389 if ((c
->cu_id
!= 0xff) &&
390 (o
->cu_id
!= 0xff) &&
391 (c
->cu_id
== o
->cu_id
))
392 return topology_sane(c
, o
, "smt");
395 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
396 c
->cpu_core_id
== o
->cpu_core_id
) {
397 return topology_sane(c
, o
, "smt");
403 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
405 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
407 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
408 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
409 return topology_sane(c
, o
, "llc");
415 * Unlike the other levels, we do not enforce keeping a
416 * multicore group inside a NUMA node. If this happens, we will
417 * discard the MC level of the topology later.
419 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
421 if (c
->phys_proc_id
== o
->phys_proc_id
)
426 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
427 static inline int x86_sched_itmt_flags(void)
429 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
432 #ifdef CONFIG_SCHED_MC
433 static int x86_core_flags(void)
435 return cpu_core_flags() | x86_sched_itmt_flags();
438 #ifdef CONFIG_SCHED_SMT
439 static int x86_smt_flags(void)
441 return cpu_smt_flags() | x86_sched_itmt_flags();
446 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
447 #ifdef CONFIG_SCHED_SMT
448 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
450 #ifdef CONFIG_SCHED_MC
451 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
456 static struct sched_domain_topology_level x86_topology
[] = {
457 #ifdef CONFIG_SCHED_SMT
458 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
460 #ifdef CONFIG_SCHED_MC
461 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
463 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
468 * Set if a package/die has multiple NUMA nodes inside.
469 * AMD Magny-Cours and Intel Cluster-on-Die have this.
471 static bool x86_has_numa_in_package
;
473 void set_cpu_sibling_map(int cpu
)
475 bool has_smt
= smp_num_siblings
> 1;
476 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
477 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
478 struct cpuinfo_x86
*o
;
481 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
484 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
485 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
486 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
491 for_each_cpu(i
, cpu_sibling_setup_mask
) {
494 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
495 link_mask(topology_sibling_cpumask
, cpu
, i
);
497 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
498 link_mask(cpu_llc_shared_mask
, cpu
, i
);
503 * This needs a separate iteration over the cpus because we rely on all
504 * topology_sibling_cpumask links to be set-up.
506 for_each_cpu(i
, cpu_sibling_setup_mask
) {
509 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
510 link_mask(topology_core_cpumask
, cpu
, i
);
513 * Does this new cpu bringup a new core?
516 topology_sibling_cpumask(cpu
)) == 1) {
518 * for each core in package, increment
519 * the booted_cores for this new cpu
522 topology_sibling_cpumask(i
)) == i
)
525 * increment the core count for all
526 * the other cpus in this package
529 cpu_data(i
).booted_cores
++;
530 } else if (i
!= cpu
&& !c
->booted_cores
)
531 c
->booted_cores
= cpu_data(i
).booted_cores
;
533 if (match_die(c
, o
) && !topology_same_node(c
, o
))
534 x86_has_numa_in_package
= true;
537 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
538 if (threads
> __max_smt_threads
)
539 __max_smt_threads
= threads
;
542 /* maps the cpu to the sched domain representing multi-core */
543 const struct cpumask
*cpu_coregroup_mask(int cpu
)
545 return cpu_llc_shared_mask(cpu
);
548 static void impress_friends(void)
551 unsigned long bogosum
= 0;
553 * Allow the user to impress friends.
555 pr_debug("Before bogomips\n");
556 for_each_possible_cpu(cpu
)
557 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
558 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
559 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
562 (bogosum
/(5000/HZ
))%100);
564 pr_debug("Before bogocount - setting activated=1\n");
567 void __inquire_remote_apic(int apicid
)
569 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
570 const char * const names
[] = { "ID", "VERSION", "SPIV" };
574 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
576 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
577 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
582 status
= safe_apic_wait_icr_idle();
584 pr_cont("a previous APIC delivery may have failed\n");
586 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
591 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
592 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
595 case APIC_ICR_RR_VALID
:
596 status
= apic_read(APIC_RRR
);
597 pr_cont("%08x\n", status
);
606 * The Multiprocessor Specification 1.4 (1997) example code suggests
607 * that there should be a 10ms delay between the BSP asserting INIT
608 * and de-asserting INIT, when starting a remote processor.
609 * But that slows boot and resume on modern processors, which include
610 * many cores and don't require that delay.
612 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
613 * Modern processor families are quirked to remove the delay entirely.
615 #define UDELAY_10MS_DEFAULT 10000
617 static unsigned int init_udelay
= UINT_MAX
;
619 static int __init
cpu_init_udelay(char *str
)
621 get_option(&str
, &init_udelay
);
625 early_param("cpu_init_udelay", cpu_init_udelay
);
627 static void __init
smp_quirk_init_udelay(void)
629 /* if cmdline changed it from default, leave it alone */
630 if (init_udelay
!= UINT_MAX
)
633 /* if modern processor, use no delay */
634 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
635 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
639 /* else, use legacy delay */
640 init_udelay
= UDELAY_10MS_DEFAULT
;
644 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
645 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
646 * won't ... remember to clear down the APIC, etc later.
649 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
651 unsigned long send_status
, accept_status
= 0;
655 /* Boot on the stack */
656 /* Kick the second */
657 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
659 pr_debug("Waiting for send to finish...\n");
660 send_status
= safe_apic_wait_icr_idle();
663 * Give the other CPU some time to accept the IPI.
666 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
667 maxlvt
= lapic_get_maxlvt();
668 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
669 apic_write(APIC_ESR
, 0);
670 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
672 pr_debug("NMI sent\n");
675 pr_err("APIC never delivered???\n");
677 pr_err("APIC delivery error (%lx)\n", accept_status
);
679 return (send_status
| accept_status
);
683 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
685 unsigned long send_status
= 0, accept_status
= 0;
686 int maxlvt
, num_starts
, j
;
688 maxlvt
= lapic_get_maxlvt();
691 * Be paranoid about clearing APIC errors.
693 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
694 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
695 apic_write(APIC_ESR
, 0);
699 pr_debug("Asserting INIT\n");
702 * Turn INIT on target chip
707 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
710 pr_debug("Waiting for send to finish...\n");
711 send_status
= safe_apic_wait_icr_idle();
715 pr_debug("Deasserting INIT\n");
719 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
721 pr_debug("Waiting for send to finish...\n");
722 send_status
= safe_apic_wait_icr_idle();
727 * Should we send STARTUP IPIs ?
729 * Determine this based on the APIC version.
730 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
732 if (APIC_INTEGRATED(boot_cpu_apic_version
))
738 * Run STARTUP IPI loop.
740 pr_debug("#startup loops: %d\n", num_starts
);
742 for (j
= 1; j
<= num_starts
; j
++) {
743 pr_debug("Sending STARTUP #%d\n", j
);
744 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
745 apic_write(APIC_ESR
, 0);
747 pr_debug("After apic_write\n");
754 /* Boot on the stack */
755 /* Kick the second */
756 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
760 * Give the other CPU some time to accept the IPI.
762 if (init_udelay
== 0)
767 pr_debug("Startup point 1\n");
769 pr_debug("Waiting for send to finish...\n");
770 send_status
= safe_apic_wait_icr_idle();
773 * Give the other CPU some time to accept the IPI.
775 if (init_udelay
== 0)
780 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
781 apic_write(APIC_ESR
, 0);
782 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
783 if (send_status
|| accept_status
)
786 pr_debug("After Startup\n");
789 pr_err("APIC never delivered???\n");
791 pr_err("APIC delivery error (%lx)\n", accept_status
);
793 return (send_status
| accept_status
);
796 /* reduce the number of lines printed when booting a large cpu count system */
797 static void announce_cpu(int cpu
, int apicid
)
799 static int current_node
= -1;
800 int node
= early_cpu_to_node(cpu
);
801 static int width
, node_width
;
804 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
807 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
810 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
812 if (system_state
< SYSTEM_RUNNING
) {
813 if (node
!= current_node
) {
814 if (current_node
> (-1))
818 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
819 node_width
- num_digits(node
), " ", node
);
822 /* Add padding for the BSP */
824 pr_cont("%*s", width
+ 1, " ");
826 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
829 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
833 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
837 cpu
= smp_processor_id();
838 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
845 * Wake up AP by INIT, INIT, STARTUP sequence.
847 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
848 * boot-strap code which is not a desired behavior for waking up BSP. To
849 * void the boot-strap code, wake up CPU0 by NMI instead.
851 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
852 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
853 * We'll change this code in the future to wake up hard offlined CPU0 if
854 * real platform and request are available.
857 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
858 int *cpu0_nmi_registered
)
866 * Wake up AP by INIT, INIT, STARTUP sequence.
869 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
874 * Wake up BSP by nmi.
876 * Register a NMI handler to help wake up CPU0.
878 boot_error
= register_nmi_handler(NMI_LOCAL
,
879 wakeup_cpu0_nmi
, 0, "wake_cpu0");
882 enable_start_cpu0
= 1;
883 *cpu0_nmi_registered
= 1;
884 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
885 id
= cpu0_logical_apicid
;
888 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
897 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
899 /* Just in case we booted with a single CPU. */
900 alternatives_enable_smp();
902 per_cpu(current_task
, cpu
) = idle
;
905 /* Stack for startup_32 can be just as for start_secondary onwards */
907 per_cpu(cpu_current_top_of_stack
, cpu
) = task_top_of_stack(idle
);
909 initial_gs
= per_cpu_offset(cpu
);
914 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
915 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
916 * Returns zero if CPU booted OK, else error code from
917 * ->wakeup_secondary_cpu.
919 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
920 int *cpu0_nmi_registered
)
922 volatile u32
*trampoline_status
=
923 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
924 /* start_ip had better be page-aligned! */
925 unsigned long start_ip
= real_mode_header
->trampoline_start
;
927 unsigned long boot_error
= 0;
928 unsigned long timeout
;
930 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
931 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
932 initial_code
= (unsigned long)start_secondary
;
933 initial_stack
= idle
->thread
.sp
;
935 /* Enable the espfix hack for this CPU */
938 /* So we see what's up */
939 announce_cpu(cpu
, apicid
);
942 * This grunge runs the startup process for
943 * the targeted processor.
946 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
948 pr_debug("Setting warm reset code and vector.\n");
950 smpboot_setup_warm_reset_vector(start_ip
);
952 * Be paranoid about clearing APIC errors.
954 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
955 apic_write(APIC_ESR
, 0);
961 * AP might wait on cpu_callout_mask in cpu_init() with
962 * cpu_initialized_mask set if previous attempt to online
963 * it timed-out. Clear cpu_initialized_mask so that after
964 * INIT/SIPI it could start with a clean state.
966 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
970 * Wake up a CPU in difference cases:
971 * - Use the method in the APIC driver if it's defined
973 * - Use an INIT boot APIC message for APs or NMI for BSP.
975 if (apic
->wakeup_secondary_cpu
)
976 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
978 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
979 cpu0_nmi_registered
);
983 * Wait 10s total for first sign of life from AP
986 timeout
= jiffies
+ 10*HZ
;
987 while (time_before(jiffies
, timeout
)) {
988 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
990 * Tell AP to proceed with initialization
992 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1002 * Wait till AP completes initial initialization
1004 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1006 * Allow other tasks to run while we wait for the
1007 * AP to come online. This also gives a chance
1008 * for the MTRR work(triggered by the AP coming online)
1009 * to be completed in the stop machine context.
1015 /* mark "stuck" area as not stuck */
1016 *trampoline_status
= 0;
1018 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1020 * Cleanup possible dangling ends...
1022 smpboot_restore_warm_reset_vector();
1028 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1030 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1031 int cpu0_nmi_registered
= 0;
1032 unsigned long flags
;
1035 lockdep_assert_irqs_enabled();
1037 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1039 if (apicid
== BAD_APICID
||
1040 !physid_isset(apicid
, phys_cpu_present_map
) ||
1041 !apic
->apic_id_valid(apicid
)) {
1042 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1047 * Already booted CPU?
1049 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1050 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1055 * Save current MTRR state in case it was changed since early boot
1056 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1060 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1061 err
= cpu_check_up_prepare(cpu
);
1062 if (err
&& err
!= -EBUSY
)
1065 /* the FPU context is blank, nobody can own it */
1066 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1068 common_cpu_up(cpu
, tidle
);
1070 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1072 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1078 * Check TSC synchronization with the AP (keep irqs disabled
1081 local_irq_save(flags
);
1082 check_tsc_sync_source(cpu
);
1083 local_irq_restore(flags
);
1085 while (!cpu_online(cpu
)) {
1087 touch_nmi_watchdog();
1092 * Clean up the nmi handler. Do this after the callin and callout sync
1093 * to avoid impact of possible long unregister time.
1095 if (cpu0_nmi_registered
)
1096 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1102 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1104 void arch_disable_smp_support(void)
1106 disable_ioapic_support();
1110 * Fall back to non SMP mode after errors.
1112 * RED-PEN audit/test this more. I bet there is more state messed up here.
1114 static __init
void disable_smp(void)
1116 pr_info("SMP disabled\n");
1118 disable_ioapic_support();
1120 init_cpu_present(cpumask_of(0));
1121 init_cpu_possible(cpumask_of(0));
1123 if (smp_found_config
)
1124 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1126 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1127 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1128 cpumask_set_cpu(0, topology_core_cpumask(0));
1132 * Various sanity checks.
1134 static void __init
smp_sanity_check(void)
1138 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1139 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1143 pr_warn("More than 8 CPUs detected - skipping them\n"
1144 "Use CONFIG_X86_BIGSMP\n");
1147 for_each_present_cpu(cpu
) {
1149 set_cpu_present(cpu
, false);
1154 for_each_possible_cpu(cpu
) {
1156 set_cpu_possible(cpu
, false);
1164 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1165 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1166 hard_smp_processor_id());
1168 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1172 * Should not be necessary because the MP table should list the boot
1173 * CPU too, but we do it for the sake of robustness anyway.
1175 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1176 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1177 boot_cpu_physical_apicid
);
1178 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1183 static void __init
smp_cpu_index_default(void)
1186 struct cpuinfo_x86
*c
;
1188 for_each_possible_cpu(i
) {
1190 /* mark all to hotplug */
1191 c
->cpu_index
= nr_cpu_ids
;
1195 static void __init
smp_get_logical_apicid(void)
1198 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1200 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1204 * Prepare for SMP bootup.
1205 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1206 * for common interface support.
1208 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1212 smp_cpu_index_default();
1215 * Setup boot CPU information
1217 smp_store_boot_cpu_info(); /* Final full version of the data */
1218 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1221 for_each_possible_cpu(i
) {
1222 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1223 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1224 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1228 * Set 'default' x86 topology, this matches default_topology() in that
1229 * it has NUMA nodes as a topology level. See also
1230 * native_smp_cpus_done().
1232 * Must be done before set_cpus_sibling_map() is ran.
1234 set_sched_topology(x86_topology
);
1236 set_cpu_sibling_map(0);
1240 switch (apic_intr_mode
) {
1242 case APIC_VIRTUAL_WIRE_NO_CONFIG
:
1245 case APIC_SYMMETRIC_IO_NO_ROUTING
:
1247 /* Setup local timer */
1248 x86_init
.timers
.setup_percpu_clockev();
1250 case APIC_VIRTUAL_WIRE
:
1251 case APIC_SYMMETRIC_IO
:
1255 /* Setup local timer */
1256 x86_init
.timers
.setup_percpu_clockev();
1258 smp_get_logical_apicid();
1261 print_cpu_info(&cpu_data(0));
1263 native_pv_lock_init();
1267 set_mtrr_aps_delayed_init();
1269 smp_quirk_init_udelay();
1272 void arch_enable_nonboot_cpus_begin(void)
1274 set_mtrr_aps_delayed_init();
1277 void arch_enable_nonboot_cpus_end(void)
1283 * Early setup to make printk work.
1285 void __init
native_smp_prepare_boot_cpu(void)
1287 int me
= smp_processor_id();
1288 switch_to_new_gdt(me
);
1289 /* already set me in cpu_online_mask in boot_cpu_init() */
1290 cpumask_set_cpu(me
, cpu_callout_mask
);
1291 cpu_set_state_online(me
);
1294 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1298 pr_debug("Boot done\n");
1300 * Today neither Intel nor AMD support heterogenous systems so
1301 * extrapolate the boot cpu's data to all packages.
1303 ncpus
= cpu_data(0).booted_cores
* topology_max_smt_threads();
1304 __max_logical_packages
= DIV_ROUND_UP(nr_cpu_ids
, ncpus
);
1305 pr_info("Max logical packages: %u\n", __max_logical_packages
);
1307 if (x86_has_numa_in_package
)
1308 set_sched_topology(x86_numa_in_package_topology
);
1315 static int __initdata setup_possible_cpus
= -1;
1316 static int __init
_setup_possible_cpus(char *str
)
1318 get_option(&str
, &setup_possible_cpus
);
1321 early_param("possible_cpus", _setup_possible_cpus
);
1325 * cpu_possible_mask should be static, it cannot change as cpu's
1326 * are onlined, or offlined. The reason is per-cpu data-structures
1327 * are allocated by some modules at init time, and dont expect to
1328 * do this dynamically on cpu arrival/departure.
1329 * cpu_present_mask on the other hand can change dynamically.
1330 * In case when cpu_hotplug is not compiled, then we resort to current
1331 * behaviour, which is cpu_possible == cpu_present.
1334 * Three ways to find out the number of additional hotplug CPUs:
1335 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1336 * - The user can overwrite it with possible_cpus=NUM
1337 * - Otherwise don't reserve additional CPUs.
1338 * We do this because additional CPUs waste a lot of memory.
1341 __init
void prefill_possible_map(void)
1345 /* No boot processor was found in mptable or ACPI MADT */
1346 if (!num_processors
) {
1347 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1348 int apicid
= boot_cpu_physical_apicid
;
1349 int cpu
= hard_smp_processor_id();
1351 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1353 /* Make sure boot cpu is enumerated */
1354 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1355 apic
->apic_id_valid(apicid
))
1356 generic_processor_info(apicid
, boot_cpu_apic_version
);
1359 if (!num_processors
)
1363 i
= setup_max_cpus
?: 1;
1364 if (setup_possible_cpus
== -1) {
1365 possible
= num_processors
;
1366 #ifdef CONFIG_HOTPLUG_CPU
1368 possible
+= disabled_cpus
;
1374 possible
= setup_possible_cpus
;
1376 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1378 /* nr_cpu_ids could be reduced via nr_cpus= */
1379 if (possible
> nr_cpu_ids
) {
1380 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1381 possible
, nr_cpu_ids
);
1382 possible
= nr_cpu_ids
;
1385 #ifdef CONFIG_HOTPLUG_CPU
1386 if (!setup_max_cpus
)
1389 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1390 possible
, setup_max_cpus
);
1394 nr_cpu_ids
= possible
;
1396 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1397 possible
, max_t(int, possible
- num_processors
, 0));
1399 reset_cpu_possible_mask();
1401 for (i
= 0; i
< possible
; i
++)
1402 set_cpu_possible(i
, true);
1405 #ifdef CONFIG_HOTPLUG_CPU
1407 /* Recompute SMT state for all CPUs on offline */
1408 static void recompute_smt_state(void)
1410 int max_threads
, cpu
;
1413 for_each_online_cpu (cpu
) {
1414 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1416 if (threads
> max_threads
)
1417 max_threads
= threads
;
1419 __max_smt_threads
= max_threads
;
1422 static void remove_siblinginfo(int cpu
)
1425 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1427 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1428 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1430 * last thread sibling in this cpu core going down
1432 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1433 cpu_data(sibling
).booted_cores
--;
1436 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1437 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1438 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1439 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1440 cpumask_clear(cpu_llc_shared_mask(cpu
));
1441 cpumask_clear(topology_sibling_cpumask(cpu
));
1442 cpumask_clear(topology_core_cpumask(cpu
));
1443 c
->phys_proc_id
= 0;
1445 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1446 recompute_smt_state();
1449 static void remove_cpu_from_maps(int cpu
)
1451 set_cpu_online(cpu
, false);
1452 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1453 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1454 /* was set by cpu_init() */
1455 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1456 numa_remove_cpu(cpu
);
1459 void cpu_disable_common(void)
1461 int cpu
= smp_processor_id();
1463 remove_siblinginfo(cpu
);
1465 /* It's now safe to remove this processor from the online map */
1467 remove_cpu_from_maps(cpu
);
1468 unlock_vector_lock();
1473 int native_cpu_disable(void)
1477 ret
= lapic_can_unplug_cpu();
1482 cpu_disable_common();
1487 int common_cpu_die(unsigned int cpu
)
1491 /* We don't do anything here: idle task is faking death itself. */
1493 /* They ack this in play_dead() by setting CPU_DEAD */
1494 if (cpu_wait_death(cpu
, 5)) {
1495 if (system_state
== SYSTEM_RUNNING
)
1496 pr_info("CPU %u is now offline\n", cpu
);
1498 pr_err("CPU %u didn't die...\n", cpu
);
1505 void native_cpu_die(unsigned int cpu
)
1507 common_cpu_die(cpu
);
1510 void play_dead_common(void)
1515 (void)cpu_report_death();
1518 * With physical CPU hotplug, we should halt the cpu
1520 local_irq_disable();
1523 static bool wakeup_cpu0(void)
1525 if (smp_processor_id() == 0 && enable_start_cpu0
)
1532 * We need to flush the caches before going to sleep, lest we have
1533 * dirty data in our caches when we come back up.
1535 static inline void mwait_play_dead(void)
1537 unsigned int eax
, ebx
, ecx
, edx
;
1538 unsigned int highest_cstate
= 0;
1539 unsigned int highest_subcstate
= 0;
1543 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1545 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1547 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1550 eax
= CPUID_MWAIT_LEAF
;
1552 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1555 * eax will be 0 if EDX enumeration is not valid.
1556 * Initialized below to cstate, sub_cstate value when EDX is valid.
1558 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1561 edx
>>= MWAIT_SUBSTATE_SIZE
;
1562 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1563 if (edx
& MWAIT_SUBSTATE_MASK
) {
1565 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1568 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1569 (highest_subcstate
- 1);
1573 * This should be a memory location in a cache line which is
1574 * unlikely to be touched by other processors. The actual
1575 * content is immaterial as it is not actually modified in any way.
1577 mwait_ptr
= ¤t_thread_info()->flags
;
1583 * The CLFLUSH is a workaround for erratum AAI65 for
1584 * the Xeon 7400 series. It's not clear it is actually
1585 * needed, but it should be harmless in either case.
1586 * The WBINVD is insufficient due to the spurious-wakeup
1587 * case where we return around the loop.
1592 __monitor(mwait_ptr
, 0, 0);
1596 * If NMI wants to wake up CPU0, start CPU0.
1603 void hlt_play_dead(void)
1605 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1611 * If NMI wants to wake up CPU0, start CPU0.
1618 void native_play_dead(void)
1621 tboot_shutdown(TB_SHUTDOWN_WFS
);
1623 mwait_play_dead(); /* Only returns on failure */
1624 if (cpuidle_play_dead())
1628 #else /* ... !CONFIG_HOTPLUG_CPU */
1629 int native_cpu_disable(void)
1634 void native_cpu_die(unsigned int cpu
)
1636 /* We said "no" in __cpu_disable */
1640 void native_play_dead(void)