1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/stackprotector.h>
55 #include <linux/gfp.h>
56 #include <linux/cpuidle.h>
57 #include <linux/numa.h>
63 #include <asm/realmode.h>
66 #include <asm/pgtable.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
92 /* representing HT, core, and die siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_die_map
);
94 EXPORT_PER_CPU_SYMBOL(cpu_die_map
);
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
100 EXPORT_PER_CPU_SYMBOL(cpu_info
);
102 /* Logical package management. We might want to allocate that dynamically */
103 unsigned int __max_logical_packages __read_mostly
;
104 EXPORT_SYMBOL(__max_logical_packages
);
105 static unsigned int logical_packages __read_mostly
;
106 static unsigned int logical_die __read_mostly
;
108 /* Maximum number of SMT threads on any online core */
109 int __read_mostly __max_smt_threads
= 1;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update
;
114 int arch_update_cpu_topology(void)
116 int retval
= x86_topology_update
;
118 x86_topology_update
= false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
126 spin_lock_irqsave(&rtc_lock
, flags
);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock
, flags
);
129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
135 static inline void smpboot_restore_warm_reset_vector(void)
140 * Paranoid: Set warm reset code and vector here back
143 spin_lock_irqsave(&rtc_lock
, flags
);
145 spin_unlock_irqrestore(&rtc_lock
, flags
);
147 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
150 static void init_freq_invariance(void);
153 * Report back to the Boot Processor during boot time or to the caller processor
156 static void smp_callin(void)
161 * If waken up by an INIT in an 82489DX configuration
162 * cpu_callout_mask guarantees we don't get here before
163 * an INIT_deassert IPI reaches our local APIC, so it is
164 * now safe to touch our local APIC.
166 cpuid
= smp_processor_id();
169 * the boot CPU has finished the init stage and is spinning
170 * on callin_map until we finish. We are free to set up this
171 * CPU, first the APIC. (this is probably redundant on most
177 * Save our processor parameters. Note: this information
178 * is needed for clock calibration.
180 smp_store_cpu_info(cpuid
);
183 * The topology information must be up to date before
184 * calibrate_delay() and notify_cpu_starting().
186 set_cpu_sibling_map(raw_smp_processor_id());
188 init_freq_invariance();
192 * Update loops_per_jiffy in cpu_data. Previous call to
193 * smp_store_cpu_info() stored a value that is close but not as
194 * accurate as the value just calculated.
197 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
198 pr_debug("Stack at about %p\n", &cpuid
);
202 notify_cpu_starting(cpuid
);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
210 static int cpu0_logical_apicid
;
211 static int enable_start_cpu0
;
213 * Activate a secondary processor.
215 static void notrace
start_secondary(void *unused
)
218 * Don't put *anything* except direct CPU state initialization
219 * before cpu_init(), SMP booting is too fragile that we want to
220 * limit the things done here to the most necessary things.
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir
);
231 x86_cpuinit
.early_percpu_clock_init();
235 enable_start_cpu0
= 0;
237 /* otherwise gcc will move up smp_processor_id before the cpu_init */
240 * Check TSC synchronization with the boot CPU:
242 check_tsc_sync_target();
244 speculative_store_bypass_ht_init();
247 * Lock vector_lock, set CPU online and bring the vector
248 * allocator online. Online must be set with vector_lock held
249 * to prevent a concurrent irq setup/teardown from seeing a
250 * half valid vector space.
253 set_cpu_online(smp_processor_id(), true);
255 unlock_vector_lock();
256 cpu_set_state_online(smp_processor_id());
257 x86_platform
.nmi_init();
259 /* enable local interrupts */
262 /* to prevent fake stack check failure in clock setup */
263 boot_init_stack_canary();
265 x86_cpuinit
.setup_percpu_clockev();
268 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
272 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
275 bool topology_is_primary_thread(unsigned int cpu
)
277 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid
, cpu
));
281 * topology_smt_supported - Check whether SMT is supported by the CPUs
283 bool topology_smt_supported(void)
285 return smp_num_siblings
> 1;
289 * topology_phys_to_logical_pkg - Map a physical package id to a logical
291 * Returns logical package id or -1 if not found
293 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
297 for_each_possible_cpu(cpu
) {
298 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
300 if (c
->initialized
&& c
->phys_proc_id
== phys_pkg
)
301 return c
->logical_proc_id
;
305 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
307 * topology_phys_to_logical_die - Map a physical die id to logical
309 * Returns logical die id or -1 if not found
311 int topology_phys_to_logical_die(unsigned int die_id
, unsigned int cur_cpu
)
314 int proc_id
= cpu_data(cur_cpu
).phys_proc_id
;
316 for_each_possible_cpu(cpu
) {
317 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
319 if (c
->initialized
&& c
->cpu_die_id
== die_id
&&
320 c
->phys_proc_id
== proc_id
)
321 return c
->logical_die_id
;
325 EXPORT_SYMBOL(topology_phys_to_logical_die
);
328 * topology_update_package_map - Update the physical to logical package map
329 * @pkg: The physical package id as retrieved via CPUID
330 * @cpu: The cpu for which this is updated
332 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
336 /* Already available somewhere? */
337 new = topology_phys_to_logical_pkg(pkg
);
341 new = logical_packages
++;
343 pr_info("CPU %u Converting physical %u to logical package %u\n",
347 cpu_data(cpu
).logical_proc_id
= new;
351 * topology_update_die_map - Update the physical to logical die map
352 * @die: The die id as retrieved via CPUID
353 * @cpu: The cpu for which this is updated
355 int topology_update_die_map(unsigned int die
, unsigned int cpu
)
359 /* Already available somewhere? */
360 new = topology_phys_to_logical_die(die
, cpu
);
366 pr_info("CPU %u Converting physical %u to logical die %u\n",
370 cpu_data(cpu
).logical_die_id
= new;
374 void __init
smp_store_boot_cpu_info(void)
376 int id
= 0; /* CPU 0 */
377 struct cpuinfo_x86
*c
= &cpu_data(id
);
381 topology_update_package_map(c
->phys_proc_id
, id
);
382 topology_update_die_map(c
->cpu_die_id
, id
);
383 c
->initialized
= true;
387 * The bootstrap kernel entry code has set these up. Save them for
390 void smp_store_cpu_info(int id
)
392 struct cpuinfo_x86
*c
= &cpu_data(id
);
394 /* Copy boot_cpu_data only on the first bringup */
399 * During boot time, CPU0 has this setup already. Save the info when
400 * bringing up AP or offlined CPU0.
402 identify_secondary_cpu(c
);
403 c
->initialized
= true;
407 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
409 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
411 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
415 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
417 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
419 return !WARN_ONCE(!topology_same_node(c
, o
),
420 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
421 "[node: %d != %d]. Ignoring dependency.\n",
422 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
425 #define link_mask(mfunc, c1, c2) \
427 cpumask_set_cpu((c1), mfunc(c2)); \
428 cpumask_set_cpu((c2), mfunc(c1)); \
431 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
433 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
434 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
436 if (c
->phys_proc_id
== o
->phys_proc_id
&&
437 c
->cpu_die_id
== o
->cpu_die_id
&&
438 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
439 if (c
->cpu_core_id
== o
->cpu_core_id
)
440 return topology_sane(c
, o
, "smt");
442 if ((c
->cu_id
!= 0xff) &&
443 (o
->cu_id
!= 0xff) &&
444 (c
->cu_id
== o
->cu_id
))
445 return topology_sane(c
, o
, "smt");
448 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
449 c
->cpu_die_id
== o
->cpu_die_id
&&
450 c
->cpu_core_id
== o
->cpu_core_id
) {
451 return topology_sane(c
, o
, "smt");
458 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
460 * These are Intel CPUs that enumerate an LLC that is shared by
461 * multiple NUMA nodes. The LLC on these systems is shared for
462 * off-package data access but private to the NUMA node (half
463 * of the package) for on-package access.
465 * CPUID (the source of the information about the LLC) can only
466 * enumerate the cache as being shared *or* unshared, but not
467 * this particular configuration. The CPU in this case enumerates
468 * the cache to be shared across the entire package (spanning both
472 static const struct x86_cpu_id snc_cpu
[] = {
473 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X
, NULL
),
477 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
479 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
481 /* Do not match if we do not have a valid APICID for cpu: */
482 if (per_cpu(cpu_llc_id
, cpu1
) == BAD_APICID
)
485 /* Do not match if LLC id does not match: */
486 if (per_cpu(cpu_llc_id
, cpu1
) != per_cpu(cpu_llc_id
, cpu2
))
490 * Allow the SNC topology without warning. Return of false
491 * means 'c' does not share the LLC of 'o'. This will be
492 * reflected to userspace.
494 if (!topology_same_node(c
, o
) && x86_match_cpu(snc_cpu
))
497 return topology_sane(c
, o
, "llc");
501 * Unlike the other levels, we do not enforce keeping a
502 * multicore group inside a NUMA node. If this happens, we will
503 * discard the MC level of the topology later.
505 static bool match_pkg(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
507 if (c
->phys_proc_id
== o
->phys_proc_id
)
512 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
514 if ((c
->phys_proc_id
== o
->phys_proc_id
) &&
515 (c
->cpu_die_id
== o
->cpu_die_id
))
521 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
522 static inline int x86_sched_itmt_flags(void)
524 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
527 #ifdef CONFIG_SCHED_MC
528 static int x86_core_flags(void)
530 return cpu_core_flags() | x86_sched_itmt_flags();
533 #ifdef CONFIG_SCHED_SMT
534 static int x86_smt_flags(void)
536 return cpu_smt_flags() | x86_sched_itmt_flags();
541 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
542 #ifdef CONFIG_SCHED_SMT
543 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
545 #ifdef CONFIG_SCHED_MC
546 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
551 static struct sched_domain_topology_level x86_topology
[] = {
552 #ifdef CONFIG_SCHED_SMT
553 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
555 #ifdef CONFIG_SCHED_MC
556 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
558 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
563 * Set if a package/die has multiple NUMA nodes inside.
564 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
565 * Sub-NUMA Clustering have this.
567 static bool x86_has_numa_in_package
;
569 void set_cpu_sibling_map(int cpu
)
571 bool has_smt
= smp_num_siblings
> 1;
572 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
573 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
574 struct cpuinfo_x86
*o
;
577 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
580 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
581 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
582 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
583 cpumask_set_cpu(cpu
, topology_die_cpumask(cpu
));
588 for_each_cpu(i
, cpu_sibling_setup_mask
) {
591 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
592 link_mask(topology_sibling_cpumask
, cpu
, i
);
594 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
595 link_mask(cpu_llc_shared_mask
, cpu
, i
);
600 * This needs a separate iteration over the cpus because we rely on all
601 * topology_sibling_cpumask links to be set-up.
603 for_each_cpu(i
, cpu_sibling_setup_mask
) {
606 if ((i
== cpu
) || (has_mp
&& match_pkg(c
, o
))) {
607 link_mask(topology_core_cpumask
, cpu
, i
);
610 * Does this new cpu bringup a new core?
613 topology_sibling_cpumask(cpu
)) == 1) {
615 * for each core in package, increment
616 * the booted_cores for this new cpu
619 topology_sibling_cpumask(i
)) == i
)
622 * increment the core count for all
623 * the other cpus in this package
626 cpu_data(i
).booted_cores
++;
627 } else if (i
!= cpu
&& !c
->booted_cores
)
628 c
->booted_cores
= cpu_data(i
).booted_cores
;
630 if (match_pkg(c
, o
) && !topology_same_node(c
, o
))
631 x86_has_numa_in_package
= true;
633 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
)))
634 link_mask(topology_die_cpumask
, cpu
, i
);
637 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
638 if (threads
> __max_smt_threads
)
639 __max_smt_threads
= threads
;
642 /* maps the cpu to the sched domain representing multi-core */
643 const struct cpumask
*cpu_coregroup_mask(int cpu
)
645 return cpu_llc_shared_mask(cpu
);
648 static void impress_friends(void)
651 unsigned long bogosum
= 0;
653 * Allow the user to impress friends.
655 pr_debug("Before bogomips\n");
656 for_each_possible_cpu(cpu
)
657 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
658 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
659 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
662 (bogosum
/(5000/HZ
))%100);
664 pr_debug("Before bogocount - setting activated=1\n");
667 void __inquire_remote_apic(int apicid
)
669 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
670 const char * const names
[] = { "ID", "VERSION", "SPIV" };
674 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
676 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
677 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
682 status
= safe_apic_wait_icr_idle();
684 pr_cont("a previous APIC delivery may have failed\n");
686 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
691 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
692 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
695 case APIC_ICR_RR_VALID
:
696 status
= apic_read(APIC_RRR
);
697 pr_cont("%08x\n", status
);
706 * The Multiprocessor Specification 1.4 (1997) example code suggests
707 * that there should be a 10ms delay between the BSP asserting INIT
708 * and de-asserting INIT, when starting a remote processor.
709 * But that slows boot and resume on modern processors, which include
710 * many cores and don't require that delay.
712 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
713 * Modern processor families are quirked to remove the delay entirely.
715 #define UDELAY_10MS_DEFAULT 10000
717 static unsigned int init_udelay
= UINT_MAX
;
719 static int __init
cpu_init_udelay(char *str
)
721 get_option(&str
, &init_udelay
);
725 early_param("cpu_init_udelay", cpu_init_udelay
);
727 static void __init
smp_quirk_init_udelay(void)
729 /* if cmdline changed it from default, leave it alone */
730 if (init_udelay
!= UINT_MAX
)
733 /* if modern processor, use no delay */
734 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
735 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
) && (boot_cpu_data
.x86
>= 0x18)) ||
736 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
740 /* else, use legacy delay */
741 init_udelay
= UDELAY_10MS_DEFAULT
;
745 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
746 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
747 * won't ... remember to clear down the APIC, etc later.
750 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
752 unsigned long send_status
, accept_status
= 0;
756 /* Boot on the stack */
757 /* Kick the second */
758 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
760 pr_debug("Waiting for send to finish...\n");
761 send_status
= safe_apic_wait_icr_idle();
764 * Give the other CPU some time to accept the IPI.
767 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
768 maxlvt
= lapic_get_maxlvt();
769 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
770 apic_write(APIC_ESR
, 0);
771 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
773 pr_debug("NMI sent\n");
776 pr_err("APIC never delivered???\n");
778 pr_err("APIC delivery error (%lx)\n", accept_status
);
780 return (send_status
| accept_status
);
784 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
786 unsigned long send_status
= 0, accept_status
= 0;
787 int maxlvt
, num_starts
, j
;
789 maxlvt
= lapic_get_maxlvt();
792 * Be paranoid about clearing APIC errors.
794 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
795 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
796 apic_write(APIC_ESR
, 0);
800 pr_debug("Asserting INIT\n");
803 * Turn INIT on target chip
808 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
811 pr_debug("Waiting for send to finish...\n");
812 send_status
= safe_apic_wait_icr_idle();
816 pr_debug("Deasserting INIT\n");
820 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
822 pr_debug("Waiting for send to finish...\n");
823 send_status
= safe_apic_wait_icr_idle();
828 * Should we send STARTUP IPIs ?
830 * Determine this based on the APIC version.
831 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
833 if (APIC_INTEGRATED(boot_cpu_apic_version
))
839 * Run STARTUP IPI loop.
841 pr_debug("#startup loops: %d\n", num_starts
);
843 for (j
= 1; j
<= num_starts
; j
++) {
844 pr_debug("Sending STARTUP #%d\n", j
);
845 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
846 apic_write(APIC_ESR
, 0);
848 pr_debug("After apic_write\n");
855 /* Boot on the stack */
856 /* Kick the second */
857 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
861 * Give the other CPU some time to accept the IPI.
863 if (init_udelay
== 0)
868 pr_debug("Startup point 1\n");
870 pr_debug("Waiting for send to finish...\n");
871 send_status
= safe_apic_wait_icr_idle();
874 * Give the other CPU some time to accept the IPI.
876 if (init_udelay
== 0)
881 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
882 apic_write(APIC_ESR
, 0);
883 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
884 if (send_status
|| accept_status
)
887 pr_debug("After Startup\n");
890 pr_err("APIC never delivered???\n");
892 pr_err("APIC delivery error (%lx)\n", accept_status
);
894 return (send_status
| accept_status
);
897 /* reduce the number of lines printed when booting a large cpu count system */
898 static void announce_cpu(int cpu
, int apicid
)
900 static int current_node
= NUMA_NO_NODE
;
901 int node
= early_cpu_to_node(cpu
);
902 static int width
, node_width
;
905 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
908 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
911 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
913 if (system_state
< SYSTEM_RUNNING
) {
914 if (node
!= current_node
) {
915 if (current_node
> (-1))
919 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
920 node_width
- num_digits(node
), " ", node
);
923 /* Add padding for the BSP */
925 pr_cont("%*s", width
+ 1, " ");
927 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
930 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
934 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
938 cpu
= smp_processor_id();
939 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
946 * Wake up AP by INIT, INIT, STARTUP sequence.
948 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
949 * boot-strap code which is not a desired behavior for waking up BSP. To
950 * void the boot-strap code, wake up CPU0 by NMI instead.
952 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
953 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
954 * We'll change this code in the future to wake up hard offlined CPU0 if
955 * real platform and request are available.
958 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
959 int *cpu0_nmi_registered
)
967 * Wake up AP by INIT, INIT, STARTUP sequence.
970 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
975 * Wake up BSP by nmi.
977 * Register a NMI handler to help wake up CPU0.
979 boot_error
= register_nmi_handler(NMI_LOCAL
,
980 wakeup_cpu0_nmi
, 0, "wake_cpu0");
983 enable_start_cpu0
= 1;
984 *cpu0_nmi_registered
= 1;
985 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
986 id
= cpu0_logical_apicid
;
989 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
998 int common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
1002 /* Just in case we booted with a single CPU. */
1003 alternatives_enable_smp();
1005 per_cpu(current_task
, cpu
) = idle
;
1007 /* Initialize the interrupt stack(s) */
1008 ret
= irq_init_percpu_irqstack(cpu
);
1012 #ifdef CONFIG_X86_32
1013 /* Stack for startup_32 can be just as for start_secondary onwards */
1014 per_cpu(cpu_current_top_of_stack
, cpu
) = task_top_of_stack(idle
);
1016 initial_gs
= per_cpu_offset(cpu
);
1022 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1023 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1024 * Returns zero if CPU booted OK, else error code from
1025 * ->wakeup_secondary_cpu.
1027 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
1028 int *cpu0_nmi_registered
)
1030 /* start_ip had better be page-aligned! */
1031 unsigned long start_ip
= real_mode_header
->trampoline_start
;
1033 unsigned long boot_error
= 0;
1034 unsigned long timeout
;
1036 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
1037 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
1038 initial_code
= (unsigned long)start_secondary
;
1039 initial_stack
= idle
->thread
.sp
;
1041 /* Enable the espfix hack for this CPU */
1042 init_espfix_ap(cpu
);
1044 /* So we see what's up */
1045 announce_cpu(cpu
, apicid
);
1048 * This grunge runs the startup process for
1049 * the targeted processor.
1052 if (x86_platform
.legacy
.warm_reset
) {
1054 pr_debug("Setting warm reset code and vector.\n");
1056 smpboot_setup_warm_reset_vector(start_ip
);
1058 * Be paranoid about clearing APIC errors.
1060 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1061 apic_write(APIC_ESR
, 0);
1062 apic_read(APIC_ESR
);
1067 * AP might wait on cpu_callout_mask in cpu_init() with
1068 * cpu_initialized_mask set if previous attempt to online
1069 * it timed-out. Clear cpu_initialized_mask so that after
1070 * INIT/SIPI it could start with a clean state.
1072 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1076 * Wake up a CPU in difference cases:
1077 * - Use the method in the APIC driver if it's defined
1079 * - Use an INIT boot APIC message for APs or NMI for BSP.
1081 if (apic
->wakeup_secondary_cpu
)
1082 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1084 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1085 cpu0_nmi_registered
);
1089 * Wait 10s total for first sign of life from AP
1092 timeout
= jiffies
+ 10*HZ
;
1093 while (time_before(jiffies
, timeout
)) {
1094 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1096 * Tell AP to proceed with initialization
1098 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1108 * Wait till AP completes initial initialization
1110 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1112 * Allow other tasks to run while we wait for the
1113 * AP to come online. This also gives a chance
1114 * for the MTRR work(triggered by the AP coming online)
1115 * to be completed in the stop machine context.
1121 if (x86_platform
.legacy
.warm_reset
) {
1123 * Cleanup possible dangling ends...
1125 smpboot_restore_warm_reset_vector();
1131 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1133 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1134 int cpu0_nmi_registered
= 0;
1135 unsigned long flags
;
1138 lockdep_assert_irqs_enabled();
1140 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1142 if (apicid
== BAD_APICID
||
1143 !physid_isset(apicid
, phys_cpu_present_map
) ||
1144 !apic
->apic_id_valid(apicid
)) {
1145 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1150 * Already booted CPU?
1152 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1153 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1158 * Save current MTRR state in case it was changed since early boot
1159 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1163 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1164 err
= cpu_check_up_prepare(cpu
);
1165 if (err
&& err
!= -EBUSY
)
1168 /* the FPU context is blank, nobody can own it */
1169 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1171 err
= common_cpu_up(cpu
, tidle
);
1175 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1177 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1183 * Check TSC synchronization with the AP (keep irqs disabled
1186 local_irq_save(flags
);
1187 check_tsc_sync_source(cpu
);
1188 local_irq_restore(flags
);
1190 while (!cpu_online(cpu
)) {
1192 touch_nmi_watchdog();
1197 * Clean up the nmi handler. Do this after the callin and callout sync
1198 * to avoid impact of possible long unregister time.
1200 if (cpu0_nmi_registered
)
1201 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1207 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1209 void arch_disable_smp_support(void)
1211 disable_ioapic_support();
1215 * Fall back to non SMP mode after errors.
1217 * RED-PEN audit/test this more. I bet there is more state messed up here.
1219 static __init
void disable_smp(void)
1221 pr_info("SMP disabled\n");
1223 disable_ioapic_support();
1225 init_cpu_present(cpumask_of(0));
1226 init_cpu_possible(cpumask_of(0));
1228 if (smp_found_config
)
1229 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1231 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1232 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1233 cpumask_set_cpu(0, topology_core_cpumask(0));
1234 cpumask_set_cpu(0, topology_die_cpumask(0));
1238 * Various sanity checks.
1240 static void __init
smp_sanity_check(void)
1244 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1245 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1249 pr_warn("More than 8 CPUs detected - skipping them\n"
1250 "Use CONFIG_X86_BIGSMP\n");
1253 for_each_present_cpu(cpu
) {
1255 set_cpu_present(cpu
, false);
1260 for_each_possible_cpu(cpu
) {
1262 set_cpu_possible(cpu
, false);
1270 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1271 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1272 hard_smp_processor_id());
1274 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1278 * Should not be necessary because the MP table should list the boot
1279 * CPU too, but we do it for the sake of robustness anyway.
1281 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1282 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1283 boot_cpu_physical_apicid
);
1284 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1289 static void __init
smp_cpu_index_default(void)
1292 struct cpuinfo_x86
*c
;
1294 for_each_possible_cpu(i
) {
1296 /* mark all to hotplug */
1297 c
->cpu_index
= nr_cpu_ids
;
1301 static void __init
smp_get_logical_apicid(void)
1304 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1306 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1310 * Prepare for SMP bootup.
1311 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1312 * for common interface support.
1314 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1318 smp_cpu_index_default();
1321 * Setup boot CPU information
1323 smp_store_boot_cpu_info(); /* Final full version of the data */
1324 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1327 for_each_possible_cpu(i
) {
1328 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1329 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1330 zalloc_cpumask_var(&per_cpu(cpu_die_map
, i
), GFP_KERNEL
);
1331 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1335 * Set 'default' x86 topology, this matches default_topology() in that
1336 * it has NUMA nodes as a topology level. See also
1337 * native_smp_cpus_done().
1339 * Must be done before set_cpus_sibling_map() is ran.
1341 set_sched_topology(x86_topology
);
1343 set_cpu_sibling_map(0);
1344 init_freq_invariance();
1347 switch (apic_intr_mode
) {
1349 case APIC_VIRTUAL_WIRE_NO_CONFIG
:
1352 case APIC_SYMMETRIC_IO_NO_ROUTING
:
1354 /* Setup local timer */
1355 x86_init
.timers
.setup_percpu_clockev();
1357 case APIC_VIRTUAL_WIRE
:
1358 case APIC_SYMMETRIC_IO
:
1362 /* Setup local timer */
1363 x86_init
.timers
.setup_percpu_clockev();
1365 smp_get_logical_apicid();
1368 print_cpu_info(&cpu_data(0));
1372 set_mtrr_aps_delayed_init();
1374 smp_quirk_init_udelay();
1376 speculative_store_bypass_ht_init();
1379 void arch_enable_nonboot_cpus_begin(void)
1381 set_mtrr_aps_delayed_init();
1384 void arch_enable_nonboot_cpus_end(void)
1390 * Early setup to make printk work.
1392 void __init
native_smp_prepare_boot_cpu(void)
1394 int me
= smp_processor_id();
1395 switch_to_new_gdt(me
);
1396 /* already set me in cpu_online_mask in boot_cpu_init() */
1397 cpumask_set_cpu(me
, cpu_callout_mask
);
1398 cpu_set_state_online(me
);
1399 native_pv_lock_init();
1402 void __init
calculate_max_logical_packages(void)
1407 * Today neither Intel nor AMD support heterogenous systems so
1408 * extrapolate the boot cpu's data to all packages.
1410 ncpus
= cpu_data(0).booted_cores
* topology_max_smt_threads();
1411 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
1412 pr_info("Max logical packages: %u\n", __max_logical_packages
);
1415 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1417 pr_debug("Boot done\n");
1419 calculate_max_logical_packages();
1421 if (x86_has_numa_in_package
)
1422 set_sched_topology(x86_numa_in_package_topology
);
1429 static int __initdata setup_possible_cpus
= -1;
1430 static int __init
_setup_possible_cpus(char *str
)
1432 get_option(&str
, &setup_possible_cpus
);
1435 early_param("possible_cpus", _setup_possible_cpus
);
1439 * cpu_possible_mask should be static, it cannot change as cpu's
1440 * are onlined, or offlined. The reason is per-cpu data-structures
1441 * are allocated by some modules at init time, and don't expect to
1442 * do this dynamically on cpu arrival/departure.
1443 * cpu_present_mask on the other hand can change dynamically.
1444 * In case when cpu_hotplug is not compiled, then we resort to current
1445 * behaviour, which is cpu_possible == cpu_present.
1448 * Three ways to find out the number of additional hotplug CPUs:
1449 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1450 * - The user can overwrite it with possible_cpus=NUM
1451 * - Otherwise don't reserve additional CPUs.
1452 * We do this because additional CPUs waste a lot of memory.
1455 __init
void prefill_possible_map(void)
1459 /* No boot processor was found in mptable or ACPI MADT */
1460 if (!num_processors
) {
1461 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1462 int apicid
= boot_cpu_physical_apicid
;
1463 int cpu
= hard_smp_processor_id();
1465 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1467 /* Make sure boot cpu is enumerated */
1468 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1469 apic
->apic_id_valid(apicid
))
1470 generic_processor_info(apicid
, boot_cpu_apic_version
);
1473 if (!num_processors
)
1477 i
= setup_max_cpus
?: 1;
1478 if (setup_possible_cpus
== -1) {
1479 possible
= num_processors
;
1480 #ifdef CONFIG_HOTPLUG_CPU
1482 possible
+= disabled_cpus
;
1488 possible
= setup_possible_cpus
;
1490 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1492 /* nr_cpu_ids could be reduced via nr_cpus= */
1493 if (possible
> nr_cpu_ids
) {
1494 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1495 possible
, nr_cpu_ids
);
1496 possible
= nr_cpu_ids
;
1499 #ifdef CONFIG_HOTPLUG_CPU
1500 if (!setup_max_cpus
)
1503 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1504 possible
, setup_max_cpus
);
1508 nr_cpu_ids
= possible
;
1510 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1511 possible
, max_t(int, possible
- num_processors
, 0));
1513 reset_cpu_possible_mask();
1515 for (i
= 0; i
< possible
; i
++)
1516 set_cpu_possible(i
, true);
1519 #ifdef CONFIG_HOTPLUG_CPU
1521 /* Recompute SMT state for all CPUs on offline */
1522 static void recompute_smt_state(void)
1524 int max_threads
, cpu
;
1527 for_each_online_cpu (cpu
) {
1528 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1530 if (threads
> max_threads
)
1531 max_threads
= threads
;
1533 __max_smt_threads
= max_threads
;
1536 static void remove_siblinginfo(int cpu
)
1539 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1541 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1542 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1544 * last thread sibling in this cpu core going down
1546 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1547 cpu_data(sibling
).booted_cores
--;
1550 for_each_cpu(sibling
, topology_die_cpumask(cpu
))
1551 cpumask_clear_cpu(cpu
, topology_die_cpumask(sibling
));
1552 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1553 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1554 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1555 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1556 cpumask_clear(cpu_llc_shared_mask(cpu
));
1557 cpumask_clear(topology_sibling_cpumask(cpu
));
1558 cpumask_clear(topology_core_cpumask(cpu
));
1559 cpumask_clear(topology_die_cpumask(cpu
));
1561 c
->booted_cores
= 0;
1562 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1563 recompute_smt_state();
1566 static void remove_cpu_from_maps(int cpu
)
1568 set_cpu_online(cpu
, false);
1569 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1570 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1571 /* was set by cpu_init() */
1572 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1573 numa_remove_cpu(cpu
);
1576 void cpu_disable_common(void)
1578 int cpu
= smp_processor_id();
1580 remove_siblinginfo(cpu
);
1582 /* It's now safe to remove this processor from the online map */
1584 remove_cpu_from_maps(cpu
);
1585 unlock_vector_lock();
1590 int native_cpu_disable(void)
1594 ret
= lapic_can_unplug_cpu();
1599 * Disable the local APIC. Otherwise IPI broadcasts will reach
1600 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1603 apic_soft_disable();
1604 cpu_disable_common();
1609 int common_cpu_die(unsigned int cpu
)
1613 /* We don't do anything here: idle task is faking death itself. */
1615 /* They ack this in play_dead() by setting CPU_DEAD */
1616 if (cpu_wait_death(cpu
, 5)) {
1617 if (system_state
== SYSTEM_RUNNING
)
1618 pr_info("CPU %u is now offline\n", cpu
);
1620 pr_err("CPU %u didn't die...\n", cpu
);
1627 void native_cpu_die(unsigned int cpu
)
1629 common_cpu_die(cpu
);
1632 void play_dead_common(void)
1637 (void)cpu_report_death();
1640 * With physical CPU hotplug, we should halt the cpu
1642 local_irq_disable();
1645 static bool wakeup_cpu0(void)
1647 if (smp_processor_id() == 0 && enable_start_cpu0
)
1654 * We need to flush the caches before going to sleep, lest we have
1655 * dirty data in our caches when we come back up.
1657 static inline void mwait_play_dead(void)
1659 unsigned int eax
, ebx
, ecx
, edx
;
1660 unsigned int highest_cstate
= 0;
1661 unsigned int highest_subcstate
= 0;
1665 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
||
1666 boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
)
1668 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1670 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1672 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1675 eax
= CPUID_MWAIT_LEAF
;
1677 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1680 * eax will be 0 if EDX enumeration is not valid.
1681 * Initialized below to cstate, sub_cstate value when EDX is valid.
1683 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1686 edx
>>= MWAIT_SUBSTATE_SIZE
;
1687 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1688 if (edx
& MWAIT_SUBSTATE_MASK
) {
1690 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1693 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1694 (highest_subcstate
- 1);
1698 * This should be a memory location in a cache line which is
1699 * unlikely to be touched by other processors. The actual
1700 * content is immaterial as it is not actually modified in any way.
1702 mwait_ptr
= ¤t_thread_info()->flags
;
1708 * The CLFLUSH is a workaround for erratum AAI65 for
1709 * the Xeon 7400 series. It's not clear it is actually
1710 * needed, but it should be harmless in either case.
1711 * The WBINVD is insufficient due to the spurious-wakeup
1712 * case where we return around the loop.
1717 __monitor(mwait_ptr
, 0, 0);
1721 * If NMI wants to wake up CPU0, start CPU0.
1728 void hlt_play_dead(void)
1730 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1736 * If NMI wants to wake up CPU0, start CPU0.
1743 void native_play_dead(void)
1746 tboot_shutdown(TB_SHUTDOWN_WFS
);
1748 mwait_play_dead(); /* Only returns on failure */
1749 if (cpuidle_play_dead())
1753 #else /* ... !CONFIG_HOTPLUG_CPU */
1754 int native_cpu_disable(void)
1759 void native_cpu_die(unsigned int cpu
)
1761 /* We said "no" in __cpu_disable */
1765 void native_play_dead(void)
1773 * APERF/MPERF frequency ratio computation.
1775 * The scheduler wants to do frequency invariant accounting and needs a <1
1776 * ratio to account for the 'current' frequency, corresponding to
1777 * freq_curr / freq_max.
1779 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1780 * our P-state setting is little more than a request/hint, we need to observe
1781 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1782 * interval after discarding idle time. This is given by:
1784 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1786 * where freq_base is the max non-turbo P-state.
1788 * The freq_max term has to be set to a somewhat arbitrary value, because we
1789 * can't know which turbo states will be available at a given point in time:
1790 * it all depends on the thermal headroom of the entire package. We set it to
1791 * the turbo level with 4 cores active.
1793 * Benchmarks show that's a good compromise between the 1C turbo ratio
1794 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1795 * which would ignore the entire turbo range (a conspicuous part, making
1796 * freq_curr/freq_max always maxed out).
1798 * An exception to the heuristic above is the Atom uarch, where we choose the
1799 * highest turbo level for freq_max since Atom's are generally oriented towards
1802 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1803 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1806 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key
);
1808 static DEFINE_PER_CPU(u64
, arch_prev_aperf
);
1809 static DEFINE_PER_CPU(u64
, arch_prev_mperf
);
1810 static u64 arch_turbo_freq_ratio
= SCHED_CAPACITY_SCALE
;
1811 static u64 arch_max_freq_ratio
= SCHED_CAPACITY_SCALE
;
1813 void arch_set_max_freq_ratio(bool turbo_disabled
)
1815 arch_max_freq_ratio
= turbo_disabled
? SCHED_CAPACITY_SCALE
:
1816 arch_turbo_freq_ratio
;
1819 static bool turbo_disabled(void)
1824 err
= rdmsrl_safe(MSR_IA32_MISC_ENABLE
, &misc_en
);
1828 return (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
);
1831 static bool slv_set_max_freq_ratio(u64
*base_freq
, u64
*turbo_freq
)
1835 err
= rdmsrl_safe(MSR_ATOM_CORE_RATIOS
, base_freq
);
1839 err
= rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS
, turbo_freq
);
1843 *base_freq
= (*base_freq
>> 16) & 0x3F; /* max P state */
1844 *turbo_freq
= *turbo_freq
& 0x3F; /* 1C turbo */
1849 #include <asm/cpu_device_id.h>
1850 #include <asm/intel-family.h>
1852 #define ICPU(model) \
1853 {X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF, 0}
1855 static const struct x86_cpu_id has_knl_turbo_ratio_limits
[] = {
1856 ICPU(INTEL_FAM6_XEON_PHI_KNL
),
1857 ICPU(INTEL_FAM6_XEON_PHI_KNM
),
1861 static const struct x86_cpu_id has_skx_turbo_ratio_limits
[] = {
1862 ICPU(INTEL_FAM6_SKYLAKE_X
),
1866 static const struct x86_cpu_id has_glm_turbo_ratio_limits
[] = {
1867 ICPU(INTEL_FAM6_ATOM_GOLDMONT
),
1868 ICPU(INTEL_FAM6_ATOM_GOLDMONT_D
),
1869 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS
),
1873 static bool knl_set_max_freq_ratio(u64
*base_freq
, u64
*turbo_freq
,
1874 int num_delta_fratio
)
1876 int fratio
, delta_fratio
, found
;
1880 if (!x86_match_cpu(has_knl_turbo_ratio_limits
))
1883 err
= rdmsrl_safe(MSR_PLATFORM_INFO
, base_freq
);
1887 *base_freq
= (*base_freq
>> 8) & 0xFF; /* max P state */
1889 err
= rdmsrl_safe(MSR_TURBO_RATIO_LIMIT
, &msr
);
1893 fratio
= (msr
>> 8) & 0xFF;
1897 if (found
>= num_delta_fratio
) {
1898 *turbo_freq
= fratio
;
1902 delta_fratio
= (msr
>> (i
+ 5)) & 0x7;
1906 fratio
-= delta_fratio
;
1915 static bool skx_set_max_freq_ratio(u64
*base_freq
, u64
*turbo_freq
, int size
)
1921 err
= rdmsrl_safe(MSR_PLATFORM_INFO
, base_freq
);
1925 *base_freq
= (*base_freq
>> 8) & 0xFF; /* max P state */
1927 err
= rdmsrl_safe(MSR_TURBO_RATIO_LIMIT
, &ratios
);
1931 err
= rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1
, &counts
);
1935 for (i
= 0; i
< 64; i
+= 8) {
1936 group_size
= (counts
>> i
) & 0xFF;
1937 if (group_size
>= size
) {
1938 *turbo_freq
= (ratios
>> i
) & 0xFF;
1946 static bool core_set_max_freq_ratio(u64
*base_freq
, u64
*turbo_freq
)
1950 err
= rdmsrl_safe(MSR_PLATFORM_INFO
, base_freq
);
1954 err
= rdmsrl_safe(MSR_TURBO_RATIO_LIMIT
, turbo_freq
);
1958 *base_freq
= (*base_freq
>> 8) & 0xFF; /* max P state */
1959 *turbo_freq
= (*turbo_freq
>> 24) & 0xFF; /* 4C turbo */
1964 static bool intel_set_max_freq_ratio(void)
1966 u64 base_freq
, turbo_freq
;
1968 if (slv_set_max_freq_ratio(&base_freq
, &turbo_freq
))
1971 if (x86_match_cpu(has_glm_turbo_ratio_limits
) &&
1972 skx_set_max_freq_ratio(&base_freq
, &turbo_freq
, 1))
1975 if (knl_set_max_freq_ratio(&base_freq
, &turbo_freq
, 1))
1978 if (x86_match_cpu(has_skx_turbo_ratio_limits
) &&
1979 skx_set_max_freq_ratio(&base_freq
, &turbo_freq
, 4))
1982 if (core_set_max_freq_ratio(&base_freq
, &turbo_freq
))
1988 arch_turbo_freq_ratio
= div_u64(turbo_freq
* SCHED_CAPACITY_SCALE
,
1990 arch_set_max_freq_ratio(turbo_disabled());
1994 static void init_counter_refs(void *arg
)
1998 rdmsrl(MSR_IA32_APERF
, aperf
);
1999 rdmsrl(MSR_IA32_MPERF
, mperf
);
2001 this_cpu_write(arch_prev_aperf
, aperf
);
2002 this_cpu_write(arch_prev_mperf
, mperf
);
2005 static void init_freq_invariance(void)
2009 if (smp_processor_id() != 0 || !boot_cpu_has(X86_FEATURE_APERFMPERF
))
2012 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2013 ret
= intel_set_max_freq_ratio();
2016 on_each_cpu(init_counter_refs
, NULL
, 1);
2017 static_branch_enable(&arch_scale_freq_key
);
2019 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2023 DEFINE_PER_CPU(unsigned long, arch_freq_scale
) = SCHED_CAPACITY_SCALE
;
2025 void arch_scale_freq_tick(void)
2031 if (!arch_scale_freq_invariant())
2034 rdmsrl(MSR_IA32_APERF
, aperf
);
2035 rdmsrl(MSR_IA32_MPERF
, mperf
);
2037 acnt
= aperf
- this_cpu_read(arch_prev_aperf
);
2038 mcnt
= mperf
- this_cpu_read(arch_prev_mperf
);
2042 this_cpu_write(arch_prev_aperf
, aperf
);
2043 this_cpu_write(arch_prev_mperf
, mperf
);
2045 acnt
<<= 2*SCHED_CAPACITY_SHIFT
;
2046 mcnt
*= arch_max_freq_ratio
;
2048 freq_scale
= div64_u64(acnt
, mcnt
);
2050 if (freq_scale
> SCHED_CAPACITY_SCALE
)
2051 freq_scale
= SCHED_CAPACITY_SCALE
;
2053 this_cpu_write(arch_freq_scale
, freq_scale
);