1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ld script for the x86 kernel
5 * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
7 * Modernisation, unification and other changes and fixes:
8 * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org>
11 * Don't define absolute symbols until and unless you know that symbol
12 * value is should remain constant even if kernel image is relocated
13 * at run time. Absolute symbols are not relocated. If symbol value should
14 * change if kernel is relocated, make the symbol section relative and
15 * put it inside the section definition.
19 #define LOAD_OFFSET __PAGE_OFFSET
21 #define LOAD_OFFSET __START_KERNEL_map
24 #define RUNTIME_DISCARD_EXIT
26 #define RO_EXCEPTION_TABLE_ALIGN 16
28 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/thread_info.h>
31 #include <asm/page_types.h>
32 #include <asm/orc_lookup.h>
33 #include <asm/cache.h>
36 #undef i386 /* in case the preprocessor is a 32bit one */
38 OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT)
42 ENTRY(phys_startup_32)
44 OUTPUT_ARCH(i386:x86-64)
45 ENTRY(phys_startup_64)
49 const_pcpu_hot = pcpu_hot;
51 #if defined(CONFIG_X86_64)
53 * On 64-bit, align RODATA to 2MB so we retain large page mappings for
54 * boundaries spanning kernel text, rodata and data sections.
56 * However, kernel identity mappings will have different RWX permissions
57 * to the pages mapping to text and to the pages padding (which are freed) the
58 * text section. Hence kernel identity mappings will be broken to smaller
59 * pages. For 64-bit, kernel text and kernel identity mappings are different,
60 * so we can enable protection checks as well as retain 2MB large page
61 * mappings for kernel text.
63 #define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE);
65 #define X86_ALIGN_RODATA_END \
66 . = ALIGN(HPAGE_SIZE); \
67 __end_rodata_hpage_align = .; \
68 __end_rodata_aligned = .;
70 #define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE);
71 #define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE);
74 * This section contains data which will be mapped as decrypted. Memory
75 * encryption operates on a page basis. Make this section PMD-aligned
76 * to avoid splitting the pages while mapping the section early.
78 * Note: We use a separate section so that only this section gets
79 * decrypted to avoid exposing more than we wish.
81 #define BSS_DECRYPTED \
82 . = ALIGN(PMD_SIZE); \
83 __start_bss_decrypted = .; \
85 . = ALIGN(PAGE_SIZE); \
86 __start_bss_decrypted_unused = .; \
87 . = ALIGN(PMD_SIZE); \
88 __end_bss_decrypted = .; \
92 #define X86_ALIGN_RODATA_BEGIN
93 #define X86_ALIGN_RODATA_END \
94 . = ALIGN(PAGE_SIZE); \
95 __end_rodata_aligned = .;
97 #define ALIGN_ENTRY_TEXT_BEGIN
98 #define ALIGN_ENTRY_TEXT_END
104 text PT_LOAD FLAGS(5); /* R_E */
105 data PT_LOAD FLAGS(6); /* RW_ */
108 percpu PT_LOAD FLAGS(6); /* RW_ */
110 init PT_LOAD FLAGS(7); /* RWE */
112 note PT_NOTE FLAGS(0); /* ___ */
118 . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR;
119 phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET);
122 phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET);
125 /* Text and read-only data */
126 .text : AT(ADDR(.text) - LOAD_OFFSET) {
129 /* bootstrapping code */
136 #ifdef CONFIG_MITIGATION_RETPOLINE
137 *(.text..__x86.indirect_thunk)
138 *(.text..__x86.return_thunk)
142 ALIGN_ENTRY_TEXT_BEGIN
143 *(.text..__x86.rethunk_untrain)
146 #ifdef CONFIG_MITIGATION_SRSO
148 * See the comment above srso_alias_untrain_ret()'s
151 . = srso_alias_untrain_ret | (1 << 2) | (1 << 8) | (1 << 14) | (1 << 20);
152 *(.text..__x86.rethunk_safe)
159 /* End of text section, which should occupy whole number of pages */
161 . = ALIGN(PAGE_SIZE);
163 X86_ALIGN_RODATA_BEGIN
168 .data : AT(ADDR(.data) - LOAD_OFFSET) {
169 /* Start of data section */
173 INIT_TASK_DATA(THREAD_SIZE)
176 /* 32 bit has nosave before _edata */
180 PAGE_ALIGNED_DATA(PAGE_SIZE)
182 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
187 /* rarely changed data like cpu maps */
188 READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES)
190 /* End of data section */
198 . = ALIGN(PAGE_SIZE);
201 .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) {
202 /* work around gold bug 13023 */
203 __vvar_beginning_hack = .;
205 /* Place all vvars at the offsets in asm/vvar.h. */
206 #define EMIT_VVAR(name, offset) \
207 . = __vvar_beginning_hack + offset; \
209 #include <asm/vvar.h>
213 * Pad the rest of the page with zeros. Otherwise the loader
214 * can leave garbage here.
216 . = __vvar_beginning_hack + PAGE_SIZE;
219 . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
221 /* Init code and data - will be freed after init */
222 . = ALIGN(PAGE_SIZE);
223 .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
224 __init_begin = .; /* paired with __init_end */
227 #if defined(CONFIG_X86_64) && defined(CONFIG_SMP)
229 * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the
230 * output PHDR, so the next output section - .init.text - should
231 * start another segment - init.
233 PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu)
234 ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START,
235 "per-CPU data too large - increase CONFIG_PHYSICAL_START")
238 INIT_TEXT_SECTION(PAGE_SIZE)
244 * Section for code used exclusively before alternatives are run. All
245 * references to such code must be patched out by alternatives, normally
246 * by using X86_FEATURE_ALWAYS CPU feature bit.
248 * See static_cpu_has() for an example.
250 .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) {
254 INIT_DATA_SECTION(16)
256 .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
257 __x86_cpu_dev_start = .;
259 __x86_cpu_dev_end = .;
262 #ifdef CONFIG_X86_INTEL_MID
263 .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \
265 __x86_intel_mid_dev_start = .;
266 *(.x86_intel_mid_dev.init)
267 __x86_intel_mid_dev_end = .;
271 #ifdef CONFIG_MITIGATION_RETPOLINE
273 * List of instructions that call/jmp/jcc to retpoline thunks
274 * __x86_indirect_thunk_*(). These instructions can be patched along
275 * with alternatives, after which the section can be freed.
278 .retpoline_sites : AT(ADDR(.retpoline_sites) - LOAD_OFFSET) {
279 __retpoline_sites = .;
281 __retpoline_sites_end = .;
285 .return_sites : AT(ADDR(.return_sites) - LOAD_OFFSET) {
288 __return_sites_end = .;
292 .call_sites : AT(ADDR(.call_sites) - LOAD_OFFSET) {
295 __call_sites_end = .;
299 #ifdef CONFIG_X86_KERNEL_IBT
301 .ibt_endbr_seal : AT(ADDR(.ibt_endbr_seal) - LOAD_OFFSET) {
302 __ibt_endbr_seal = .;
304 __ibt_endbr_seal_end = .;
308 #ifdef CONFIG_FINEIBT
310 .cfi_sites : AT(ADDR(.cfi_sites) - LOAD_OFFSET) {
318 * struct alt_inst entries. From the header (alternative.h):
319 * "Alternative instructions for different CPU types or capabilities"
320 * Think locking instructions on spinlocks.
323 .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
324 __alt_instructions = .;
326 __alt_instructions_end = .;
330 * And here are the replacement instructions. The linker sticks
331 * them as binary blobs. The .altinstructions has enough data to
332 * get the address and the length of them to patch the kernel safely.
334 .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
335 *(.altinstr_replacement)
339 .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) {
342 __apicdrivers_end = .;
347 * .exit.text is discarded at runtime, not link time, to deal with
348 * references from .altinstructions
350 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
354 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
358 #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP)
359 PERCPU_SECTION(INTERNODE_CACHE_BYTES)
362 . = ALIGN(PAGE_SIZE);
364 /* freed after init ends here */
365 .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) {
370 * smp_locks might be freed after init
371 * start/end must be page aligned
373 . = ALIGN(PAGE_SIZE);
374 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
377 . = ALIGN(PAGE_SIZE);
382 .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
388 . = ALIGN(PAGE_SIZE);
389 .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
391 *(.bss..page_aligned)
392 . = ALIGN(PAGE_SIZE);
395 . = ALIGN(PAGE_SIZE);
400 * The memory occupied from _text to here, __end_of_kernel_reserve, is
401 * automatically reserved in setup_arch(). Anything after here must be
402 * explicitly reserved using memblock_reserve() or it will be discarded
403 * and treated as available memory.
405 __end_of_kernel_reserve = .;
407 . = ALIGN(PAGE_SIZE);
408 .brk : AT(ADDR(.brk) - LOAD_OFFSET) {
410 . += 64 * 1024; /* 64k alignment slop space */
411 *(.bss..brk) /* areas brk users have reserved */
415 . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */
418 #ifdef CONFIG_AMD_MEM_ENCRYPT
420 * Early scratch/workarea section: Lives outside of the kernel proper
423 * Resides after _end because even though the .brk section is after
424 * __end_of_kernel_reserve, the .brk section is later reserved as a
425 * part of the kernel. Since it is located after __end_of_kernel_reserve
426 * it will be discarded and become part of the available memory. As
427 * such, it can only be used by very early boot code and must not be
430 * Currently used by SME for performing in-place encryption of the
431 * kernel during boot. Resides on a 2MB boundary to simplify the
432 * pagetable setup used for SME in-place encryption.
434 . = ALIGN(HPAGE_SIZE);
435 .init.scratch : AT(ADDR(.init.scratch) - LOAD_OFFSET) {
436 __init_scratch_begin = .;
438 . = ALIGN(HPAGE_SIZE);
439 __init_scratch_end = .;
450 * Make sure that the .got.plt is either completely empty or it
451 * contains only the lazy dispatch entries.
453 .got.plt (INFO) : { *(.got.plt) }
454 ASSERT(SIZEOF(.got.plt) == 0 ||
456 SIZEOF(.got.plt) == 0x18,
458 SIZEOF(.got.plt) == 0xc,
460 "Unexpected GOT/PLT entries detected!")
463 * Sections that should stay zero sized, which is safer to
464 * explicitly check instead of blindly discarding.
469 ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!")
472 *(.plt) *(.plt.*) *(.iplt)
474 ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!")
479 ASSERT(SIZEOF(.rel.dyn) == 0, "Unexpected run-time relocations (.rel) detected!")
482 *(.rela.*) *(.rela_*)
484 ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!")
488 * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility:
490 . = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE),
491 "kernel image bigger than KERNEL_IMAGE_SIZE");
495 * Per-cpu symbols which need to be offset from __per_cpu_load
496 * for the boot processor.
498 #define INIT_PER_CPU(x) init_per_cpu__##x = ABSOLUTE(x) + __per_cpu_load
499 INIT_PER_CPU(gdt_page);
500 INIT_PER_CPU(fixed_percpu_data);
501 INIT_PER_CPU(irq_stack_backing_store);
504 . = ASSERT((fixed_percpu_data == 0),
505 "fixed_percpu_data is not at start of per-cpu area");
508 #ifdef CONFIG_MITIGATION_UNRET_ENTRY
509 . = ASSERT((retbleed_return_thunk & 0x3f) == 0, "retbleed_return_thunk not cacheline-aligned");
512 #ifdef CONFIG_MITIGATION_SRSO
513 . = ASSERT((srso_safe_ret & 0x3f) == 0, "srso_safe_ret not cacheline-aligned");
515 * GNU ld cannot do XOR until 2.41.
516 * https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f6f78318fca803c4907fb8d7f6ded8295f1947b1
518 * LLVM lld cannot do XOR until lld-17.
519 * https://github.com/llvm/llvm-project/commit/fae96104d4378166cbe5c875ef8ed808a356f3fb
521 * Instead do: (A | B) - (A & B) in order to compute the XOR
522 * of the two function addresses:
524 . = ASSERT(((ABSOLUTE(srso_alias_untrain_ret) | srso_alias_safe_ret) -
525 (ABSOLUTE(srso_alias_untrain_ret) & srso_alias_safe_ret)) == ((1 << 2) | (1 << 8) | (1 << 14) | (1 << 20)),
526 "SRSO function pair won't alias");
529 #endif /* CONFIG_X86_64 */