2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
33 #include <linux/kvm_host.h>
36 static void pic_clear_isr(struct kvm_kpic_state
*s
, int irq
)
38 s
->isr
&= ~(1 << irq
);
39 s
->isr_ack
|= (1 << irq
);
40 if (s
!= &s
->pics_state
->pics
[0])
43 * We are dropping lock while calling ack notifiers since ack
44 * notifier callbacks for assigned devices call into PIC recursively.
45 * Other interrupt may be delivered to PIC while lock is dropped but
46 * it should be safe since PIC state is already updated at this stage.
48 raw_spin_unlock(&s
->pics_state
->lock
);
49 kvm_notify_acked_irq(s
->pics_state
->kvm
, SELECT_PIC(irq
), irq
);
50 raw_spin_lock(&s
->pics_state
->lock
);
53 void kvm_pic_clear_isr_ack(struct kvm
*kvm
)
55 struct kvm_pic
*s
= pic_irqchip(kvm
);
57 raw_spin_lock(&s
->lock
);
58 s
->pics
[0].isr_ack
= 0xff;
59 s
->pics
[1].isr_ack
= 0xff;
60 raw_spin_unlock(&s
->lock
);
64 * set irq level. If an edge is detected, then the IRR is set to 1
66 static inline int pic_set_irq1(struct kvm_kpic_state
*s
, int irq
, int level
)
70 if (s
->elcr
& mask
) /* level triggered */
72 ret
= !(s
->irr
& mask
);
79 else /* edge triggered */
81 if ((s
->last_irr
& mask
) == 0) {
82 ret
= !(s
->irr
& mask
);
89 return (s
->imr
& mask
) ? -1 : ret
;
93 * return the highest priority found in mask (highest = smallest
94 * number). Return 8 if no irq
96 static inline int get_priority(struct kvm_kpic_state
*s
, int mask
)
102 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
108 * return the pic wanted interrupt. return -1 if none
110 static int pic_get_irq(struct kvm_kpic_state
*s
)
112 int mask
, cur_priority
, priority
;
114 mask
= s
->irr
& ~s
->imr
;
115 priority
= get_priority(s
, mask
);
119 * compute current priority. If special fully nested mode on the
120 * master, the IRQ coming from the slave is not taken into account
121 * for the priority computation.
124 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
126 cur_priority
= get_priority(s
, mask
);
127 if (priority
< cur_priority
)
129 * higher priority found: an irq should be generated
131 return (priority
+ s
->priority_add
) & 7;
137 * raise irq to CPU if necessary. must be called every time the active
140 static void pic_update_irq(struct kvm_pic
*s
)
144 irq2
= pic_get_irq(&s
->pics
[1]);
147 * if irq request by slave pic, signal master PIC
149 pic_set_irq1(&s
->pics
[0], 2, 1);
150 pic_set_irq1(&s
->pics
[0], 2, 0);
152 irq
= pic_get_irq(&s
->pics
[0]);
154 s
->irq_request(s
->irq_request_opaque
, 1);
156 s
->irq_request(s
->irq_request_opaque
, 0);
159 void kvm_pic_update_irq(struct kvm_pic
*s
)
161 raw_spin_lock(&s
->lock
);
163 raw_spin_unlock(&s
->lock
);
166 int kvm_pic_set_irq(void *opaque
, int irq
, int level
)
168 struct kvm_pic
*s
= opaque
;
171 raw_spin_lock(&s
->lock
);
172 if (irq
>= 0 && irq
< PIC_NUM_PINS
) {
173 ret
= pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
175 trace_kvm_pic_set_irq(irq
>> 3, irq
& 7, s
->pics
[irq
>> 3].elcr
,
176 s
->pics
[irq
>> 3].imr
, ret
== 0);
178 raw_spin_unlock(&s
->lock
);
184 * acknowledge interrupt 'irq'
186 static inline void pic_intack(struct kvm_kpic_state
*s
, int irq
)
190 * We don't clear a level sensitive interrupt here
192 if (!(s
->elcr
& (1 << irq
)))
193 s
->irr
&= ~(1 << irq
);
196 if (s
->rotate_on_auto_eoi
)
197 s
->priority_add
= (irq
+ 1) & 7;
198 pic_clear_isr(s
, irq
);
203 int kvm_pic_read_irq(struct kvm
*kvm
)
205 int irq
, irq2
, intno
;
206 struct kvm_pic
*s
= pic_irqchip(kvm
);
208 raw_spin_lock(&s
->lock
);
209 irq
= pic_get_irq(&s
->pics
[0]);
211 pic_intack(&s
->pics
[0], irq
);
213 irq2
= pic_get_irq(&s
->pics
[1]);
215 pic_intack(&s
->pics
[1], irq2
);
218 * spurious IRQ on slave controller
221 intno
= s
->pics
[1].irq_base
+ irq2
;
224 intno
= s
->pics
[0].irq_base
+ irq
;
227 * spurious IRQ on host controller
230 intno
= s
->pics
[0].irq_base
+ irq
;
233 raw_spin_unlock(&s
->lock
);
238 void kvm_pic_reset(struct kvm_kpic_state
*s
)
241 struct kvm
*kvm
= s
->pics_state
->irq_request_opaque
;
242 struct kvm_vcpu
*vcpu0
= kvm
->bsp_vcpu
;
243 u8 irr
= s
->irr
, isr
= s
->imr
;
252 s
->read_reg_select
= 0;
257 s
->rotate_on_auto_eoi
= 0;
258 s
->special_fully_nested_mode
= 0;
261 for (irq
= 0; irq
< PIC_NUM_PINS
/2; irq
++) {
262 if (vcpu0
&& kvm_apic_accept_pic_intr(vcpu0
))
263 if (irr
& (1 << irq
) || isr
& (1 << irq
)) {
264 pic_clear_isr(s
, irq
);
269 static void pic_ioport_write(void *opaque
, u32 addr
, u32 val
)
271 struct kvm_kpic_state
*s
= opaque
;
272 int priority
, cmd
, irq
;
277 kvm_pic_reset(s
); /* init */
279 * deassert a pending interrupt
281 s
->pics_state
->irq_request(s
->pics_state
->
282 irq_request_opaque
, 0);
286 printk(KERN_ERR
"single mode not supported");
289 "level sensitive irq not supported");
290 } else if (val
& 0x08) {
294 s
->read_reg_select
= val
& 1;
296 s
->special_mask
= (val
>> 5) & 1;
302 s
->rotate_on_auto_eoi
= cmd
>> 2;
304 case 1: /* end of interrupt */
306 priority
= get_priority(s
, s
->isr
);
308 irq
= (priority
+ s
->priority_add
) & 7;
310 s
->priority_add
= (irq
+ 1) & 7;
311 pic_clear_isr(s
, irq
);
312 pic_update_irq(s
->pics_state
);
317 pic_clear_isr(s
, irq
);
318 pic_update_irq(s
->pics_state
);
321 s
->priority_add
= (val
+ 1) & 7;
322 pic_update_irq(s
->pics_state
);
326 s
->priority_add
= (irq
+ 1) & 7;
327 pic_clear_isr(s
, irq
);
328 pic_update_irq(s
->pics_state
);
331 break; /* no operation */
335 switch (s
->init_state
) {
336 case 0: /* normal mode */
338 pic_update_irq(s
->pics_state
);
341 s
->irq_base
= val
& 0xf8;
351 s
->special_fully_nested_mode
= (val
>> 4) & 1;
352 s
->auto_eoi
= (val
>> 1) & 1;
358 static u32
pic_poll_read(struct kvm_kpic_state
*s
, u32 addr1
)
362 ret
= pic_get_irq(s
);
365 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
366 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
368 s
->irr
&= ~(1 << ret
);
369 pic_clear_isr(s
, ret
);
370 if (addr1
>> 7 || ret
!= 2)
371 pic_update_irq(s
->pics_state
);
374 pic_update_irq(s
->pics_state
);
380 static u32
pic_ioport_read(void *opaque
, u32 addr1
)
382 struct kvm_kpic_state
*s
= opaque
;
389 ret
= pic_poll_read(s
, addr1
);
393 if (s
->read_reg_select
)
402 static void elcr_ioport_write(void *opaque
, u32 addr
, u32 val
)
404 struct kvm_kpic_state
*s
= opaque
;
405 s
->elcr
= val
& s
->elcr_mask
;
408 static u32
elcr_ioport_read(void *opaque
, u32 addr1
)
410 struct kvm_kpic_state
*s
= opaque
;
414 static int picdev_in_range(gpa_t addr
)
429 static inline struct kvm_pic
*to_pic(struct kvm_io_device
*dev
)
431 return container_of(dev
, struct kvm_pic
, dev
);
434 static int picdev_write(struct kvm_io_device
*this,
435 gpa_t addr
, int len
, const void *val
)
437 struct kvm_pic
*s
= to_pic(this);
438 unsigned char data
= *(unsigned char *)val
;
439 if (!picdev_in_range(addr
))
443 if (printk_ratelimit())
444 printk(KERN_ERR
"PIC: non byte write\n");
447 raw_spin_lock(&s
->lock
);
453 pic_ioport_write(&s
->pics
[addr
>> 7], addr
, data
);
457 elcr_ioport_write(&s
->pics
[addr
& 1], addr
, data
);
460 raw_spin_unlock(&s
->lock
);
464 static int picdev_read(struct kvm_io_device
*this,
465 gpa_t addr
, int len
, void *val
)
467 struct kvm_pic
*s
= to_pic(this);
468 unsigned char data
= 0;
469 if (!picdev_in_range(addr
))
473 if (printk_ratelimit())
474 printk(KERN_ERR
"PIC: non byte read\n");
477 raw_spin_lock(&s
->lock
);
483 data
= pic_ioport_read(&s
->pics
[addr
>> 7], addr
);
487 data
= elcr_ioport_read(&s
->pics
[addr
& 1], addr
);
490 *(unsigned char *)val
= data
;
491 raw_spin_unlock(&s
->lock
);
496 * callback when PIC0 irq status changed
498 static void pic_irq_request(void *opaque
, int level
)
500 struct kvm
*kvm
= opaque
;
501 struct kvm_vcpu
*vcpu
= kvm
->bsp_vcpu
;
502 struct kvm_pic
*s
= pic_irqchip(kvm
);
503 int irq
= pic_get_irq(&s
->pics
[0]);
506 if (vcpu
&& level
&& (s
->pics
[0].isr_ack
& (1 << irq
))) {
507 s
->pics
[0].isr_ack
&= ~(1 << irq
);
512 static const struct kvm_io_device_ops picdev_ops
= {
514 .write
= picdev_write
,
517 struct kvm_pic
*kvm_create_pic(struct kvm
*kvm
)
522 s
= kzalloc(sizeof(struct kvm_pic
), GFP_KERNEL
);
525 raw_spin_lock_init(&s
->lock
);
527 s
->pics
[0].elcr_mask
= 0xf8;
528 s
->pics
[1].elcr_mask
= 0xde;
529 s
->irq_request
= pic_irq_request
;
530 s
->irq_request_opaque
= kvm
;
531 s
->pics
[0].pics_state
= s
;
532 s
->pics
[1].pics_state
= s
;
535 * Initialize PIO device
537 kvm_iodevice_init(&s
->dev
, &picdev_ops
);
538 mutex_lock(&kvm
->slots_lock
);
539 ret
= kvm_io_bus_register_dev(kvm
, KVM_PIO_BUS
, &s
->dev
);
540 mutex_unlock(&kvm
->slots_lock
);
549 void kvm_destroy_pic(struct kvm
*kvm
)
551 struct kvm_pic
*vpic
= kvm
->arch
.vpic
;
554 kvm_io_bus_unregister_dev(kvm
, KVM_PIO_BUS
, &vpic
->dev
);
555 kvm
->arch
.vpic
= NULL
;