2 * Copyright (C) 2001 MandrakeSoft S.A.
3 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 * http://www.linux-mandrake.com/
9 * http://www.mandrakesoft.com/
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Yunhong Jiang <yunhong.jiang@intel.com>
26 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
27 * Based on Xen 3.1 code.
30 #include <linux/kvm_host.h>
31 #include <linux/kvm.h>
33 #include <linux/highmem.h>
34 #include <linux/smp.h>
35 #include <linux/hrtimer.h>
37 #include <linux/slab.h>
38 #include <linux/export.h>
39 #include <linux/nospec.h>
40 #include <asm/processor.h>
42 #include <asm/current.h>
43 #include <trace/events/kvm.h>
49 static int ioapic_service(struct kvm_ioapic
*vioapic
, int irq
,
52 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu
*vcpu
,
53 struct kvm_ioapic
*ioapic
,
57 static unsigned long ioapic_read_indirect(struct kvm_ioapic
*ioapic
,
61 unsigned long result
= 0;
63 switch (ioapic
->ioregsel
) {
64 case IOAPIC_REG_VERSION
:
65 result
= ((((IOAPIC_NUM_PINS
- 1) & 0xff) << 16)
66 | (IOAPIC_VERSION_ID
& 0xff));
69 case IOAPIC_REG_APIC_ID
:
70 case IOAPIC_REG_ARB_ID
:
71 result
= ((ioapic
->id
& 0xf) << 24);
76 u32 redir_index
= (ioapic
->ioregsel
- 0x10) >> 1;
77 u64 redir_content
= ~0ULL;
79 if (redir_index
< IOAPIC_NUM_PINS
) {
80 u32 index
= array_index_nospec(
81 redir_index
, IOAPIC_NUM_PINS
);
83 redir_content
= ioapic
->redirtbl
[index
].bits
;
86 result
= (ioapic
->ioregsel
& 0x1) ?
87 (redir_content
>> 32) & 0xffffffff :
88 redir_content
& 0xffffffff;
96 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic
*ioapic
)
98 ioapic
->rtc_status
.pending_eoi
= 0;
99 bitmap_zero(ioapic
->rtc_status
.dest_map
.map
, KVM_MAX_VCPU_ID
);
102 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic
*ioapic
);
104 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic
*ioapic
)
106 if (WARN_ON(ioapic
->rtc_status
.pending_eoi
< 0))
107 kvm_rtc_eoi_tracking_restore_all(ioapic
);
110 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu
*vcpu
)
112 bool new_val
, old_val
;
113 struct kvm_ioapic
*ioapic
= vcpu
->kvm
->arch
.vioapic
;
114 struct dest_map
*dest_map
= &ioapic
->rtc_status
.dest_map
;
115 union kvm_ioapic_redirect_entry
*e
;
117 e
= &ioapic
->redirtbl
[RTC_GSI
];
118 if (!kvm_apic_match_dest(vcpu
, NULL
, APIC_DEST_NOSHORT
,
120 kvm_lapic_irq_dest_mode(!!e
->fields
.dest_mode
)))
123 new_val
= kvm_apic_pending_eoi(vcpu
, e
->fields
.vector
);
124 old_val
= test_bit(vcpu
->vcpu_id
, dest_map
->map
);
126 if (new_val
== old_val
)
130 __set_bit(vcpu
->vcpu_id
, dest_map
->map
);
131 dest_map
->vectors
[vcpu
->vcpu_id
] = e
->fields
.vector
;
132 ioapic
->rtc_status
.pending_eoi
++;
134 __clear_bit(vcpu
->vcpu_id
, dest_map
->map
);
135 ioapic
->rtc_status
.pending_eoi
--;
136 rtc_status_pending_eoi_check_valid(ioapic
);
140 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu
*vcpu
)
142 struct kvm_ioapic
*ioapic
= vcpu
->kvm
->arch
.vioapic
;
144 spin_lock(&ioapic
->lock
);
145 __rtc_irq_eoi_tracking_restore_one(vcpu
);
146 spin_unlock(&ioapic
->lock
);
149 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic
*ioapic
)
151 struct kvm_vcpu
*vcpu
;
154 if (RTC_GSI
>= IOAPIC_NUM_PINS
)
157 rtc_irq_eoi_tracking_reset(ioapic
);
158 kvm_for_each_vcpu(i
, vcpu
, ioapic
->kvm
)
159 __rtc_irq_eoi_tracking_restore_one(vcpu
);
162 static void rtc_irq_eoi(struct kvm_ioapic
*ioapic
, struct kvm_vcpu
*vcpu
,
165 struct dest_map
*dest_map
= &ioapic
->rtc_status
.dest_map
;
167 /* RTC special handling */
168 if (test_bit(vcpu
->vcpu_id
, dest_map
->map
) &&
169 (vector
== dest_map
->vectors
[vcpu
->vcpu_id
]) &&
170 (test_and_clear_bit(vcpu
->vcpu_id
,
171 ioapic
->rtc_status
.dest_map
.map
))) {
172 --ioapic
->rtc_status
.pending_eoi
;
173 rtc_status_pending_eoi_check_valid(ioapic
);
177 static bool rtc_irq_check_coalesced(struct kvm_ioapic
*ioapic
)
179 if (ioapic
->rtc_status
.pending_eoi
> 0)
180 return true; /* coalesced */
185 static void ioapic_lazy_update_eoi(struct kvm_ioapic
*ioapic
, int irq
)
188 struct kvm_vcpu
*vcpu
;
189 union kvm_ioapic_redirect_entry
*entry
= &ioapic
->redirtbl
[irq
];
191 kvm_for_each_vcpu(i
, vcpu
, ioapic
->kvm
) {
192 if (!kvm_apic_match_dest(vcpu
, NULL
, APIC_DEST_NOSHORT
,
193 entry
->fields
.dest_id
,
194 entry
->fields
.dest_mode
) ||
195 kvm_apic_pending_eoi(vcpu
, entry
->fields
.vector
))
199 * If no longer has pending EOI in LAPICs, update
200 * EOI for this vetor.
202 rtc_irq_eoi(ioapic
, vcpu
, entry
->fields
.vector
);
203 kvm_ioapic_update_eoi_one(vcpu
, ioapic
,
204 entry
->fields
.trig_mode
,
210 static int ioapic_set_irq(struct kvm_ioapic
*ioapic
, unsigned int irq
,
211 int irq_level
, bool line_status
)
213 union kvm_ioapic_redirect_entry entry
;
218 entry
= ioapic
->redirtbl
[irq
];
219 edge
= (entry
.fields
.trig_mode
== IOAPIC_EDGE_TRIG
);
222 ioapic
->irr
&= ~mask
;
228 * AMD SVM AVIC accelerate EOI write and do not trap,
229 * in-kernel IOAPIC will not be able to receive the EOI.
230 * In this case, we do lazy update of the pending EOI when
231 * trying to set IOAPIC irq.
233 if (kvm_apicv_activated(ioapic
->kvm
))
234 ioapic_lazy_update_eoi(ioapic
, irq
);
237 * Return 0 for coalesced interrupts; for edge-triggered interrupts,
238 * this only happens if a previous edge has not been delivered due
239 * to masking. For level interrupts, the remote_irr field tells
240 * us if the interrupt is waiting for an EOI.
242 * RTC is special: it is edge-triggered, but userspace likes to know
243 * if it has been already ack-ed via EOI because coalesced RTC
244 * interrupts lead to time drift in Windows guests. So we track
245 * EOI manually for the RTC interrupt.
247 if (irq
== RTC_GSI
&& line_status
&&
248 rtc_irq_check_coalesced(ioapic
)) {
253 old_irr
= ioapic
->irr
;
256 ioapic
->irr_delivered
&= ~mask
;
257 if (old_irr
== ioapic
->irr
) {
263 ret
= ioapic_service(ioapic
, irq
, line_status
);
266 trace_kvm_ioapic_set_irq(entry
.bits
, irq
, ret
== 0);
270 static void kvm_ioapic_inject_all(struct kvm_ioapic
*ioapic
, unsigned long irr
)
274 rtc_irq_eoi_tracking_reset(ioapic
);
275 for_each_set_bit(idx
, &irr
, IOAPIC_NUM_PINS
)
276 ioapic_set_irq(ioapic
, idx
, 1, true);
278 kvm_rtc_eoi_tracking_restore_all(ioapic
);
282 void kvm_ioapic_scan_entry(struct kvm_vcpu
*vcpu
, ulong
*ioapic_handled_vectors
)
284 struct kvm_ioapic
*ioapic
= vcpu
->kvm
->arch
.vioapic
;
285 struct dest_map
*dest_map
= &ioapic
->rtc_status
.dest_map
;
286 union kvm_ioapic_redirect_entry
*e
;
289 spin_lock(&ioapic
->lock
);
291 /* Make sure we see any missing RTC EOI */
292 if (test_bit(vcpu
->vcpu_id
, dest_map
->map
))
293 __set_bit(dest_map
->vectors
[vcpu
->vcpu_id
],
294 ioapic_handled_vectors
);
296 for (index
= 0; index
< IOAPIC_NUM_PINS
; index
++) {
297 e
= &ioapic
->redirtbl
[index
];
298 if (e
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
||
299 kvm_irq_has_notifier(ioapic
->kvm
, KVM_IRQCHIP_IOAPIC
, index
) ||
301 u16 dm
= kvm_lapic_irq_dest_mode(!!e
->fields
.dest_mode
);
303 if (kvm_apic_match_dest(vcpu
, NULL
, APIC_DEST_NOSHORT
,
304 e
->fields
.dest_id
, dm
) ||
305 kvm_apic_pending_eoi(vcpu
, e
->fields
.vector
))
306 __set_bit(e
->fields
.vector
,
307 ioapic_handled_vectors
);
310 spin_unlock(&ioapic
->lock
);
313 void kvm_arch_post_irq_ack_notifier_list_update(struct kvm
*kvm
)
315 if (!ioapic_in_kernel(kvm
))
317 kvm_make_scan_ioapic_request(kvm
);
320 static void ioapic_write_indirect(struct kvm_ioapic
*ioapic
, u32 val
)
323 bool mask_before
, mask_after
;
324 union kvm_ioapic_redirect_entry
*e
;
325 unsigned long vcpu_bitmap
;
326 int old_remote_irr
, old_delivery_status
, old_dest_id
, old_dest_mode
;
328 switch (ioapic
->ioregsel
) {
329 case IOAPIC_REG_VERSION
:
330 /* Writes are ignored. */
333 case IOAPIC_REG_APIC_ID
:
334 ioapic
->id
= (val
>> 24) & 0xf;
337 case IOAPIC_REG_ARB_ID
:
341 index
= (ioapic
->ioregsel
- 0x10) >> 1;
343 if (index
>= IOAPIC_NUM_PINS
)
345 index
= array_index_nospec(index
, IOAPIC_NUM_PINS
);
346 e
= &ioapic
->redirtbl
[index
];
347 mask_before
= e
->fields
.mask
;
348 /* Preserve read-only fields */
349 old_remote_irr
= e
->fields
.remote_irr
;
350 old_delivery_status
= e
->fields
.delivery_status
;
351 old_dest_id
= e
->fields
.dest_id
;
352 old_dest_mode
= e
->fields
.dest_mode
;
353 if (ioapic
->ioregsel
& 1) {
354 e
->bits
&= 0xffffffff;
355 e
->bits
|= (u64
) val
<< 32;
357 e
->bits
&= ~0xffffffffULL
;
358 e
->bits
|= (u32
) val
;
360 e
->fields
.remote_irr
= old_remote_irr
;
361 e
->fields
.delivery_status
= old_delivery_status
;
364 * Some OSes (Linux, Xen) assume that Remote IRR bit will
365 * be cleared by IOAPIC hardware when the entry is configured
366 * as edge-triggered. This behavior is used to simulate an
367 * explicit EOI on IOAPICs that don't have the EOI register.
369 if (e
->fields
.trig_mode
== IOAPIC_EDGE_TRIG
)
370 e
->fields
.remote_irr
= 0;
372 mask_after
= e
->fields
.mask
;
373 if (mask_before
!= mask_after
)
374 kvm_fire_mask_notifiers(ioapic
->kvm
, KVM_IRQCHIP_IOAPIC
, index
, mask_after
);
375 if (e
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
376 && ioapic
->irr
& (1 << index
))
377 ioapic_service(ioapic
, index
, false);
378 if (e
->fields
.delivery_mode
== APIC_DM_FIXED
) {
379 struct kvm_lapic_irq irq
;
381 irq
.vector
= e
->fields
.vector
;
382 irq
.delivery_mode
= e
->fields
.delivery_mode
<< 8;
384 kvm_lapic_irq_dest_mode(!!e
->fields
.dest_mode
);
386 irq
.trig_mode
= e
->fields
.trig_mode
;
387 irq
.shorthand
= APIC_DEST_NOSHORT
;
388 irq
.dest_id
= e
->fields
.dest_id
;
389 irq
.msi_redir_hint
= false;
390 bitmap_zero(&vcpu_bitmap
, 16);
391 kvm_bitmap_or_dest_vcpus(ioapic
->kvm
, &irq
,
393 if (old_dest_mode
!= e
->fields
.dest_mode
||
394 old_dest_id
!= e
->fields
.dest_id
) {
396 * Update vcpu_bitmap with vcpus specified in
397 * the previous request as well. This is done to
398 * keep ioapic_handled_vectors synchronized.
400 irq
.dest_id
= old_dest_id
;
402 kvm_lapic_irq_dest_mode(
403 !!e
->fields
.dest_mode
);
404 kvm_bitmap_or_dest_vcpus(ioapic
->kvm
, &irq
,
407 kvm_make_scan_ioapic_request_mask(ioapic
->kvm
,
410 kvm_make_scan_ioapic_request(ioapic
->kvm
);
416 static int ioapic_service(struct kvm_ioapic
*ioapic
, int irq
, bool line_status
)
418 union kvm_ioapic_redirect_entry
*entry
= &ioapic
->redirtbl
[irq
];
419 struct kvm_lapic_irq irqe
;
422 if (entry
->fields
.mask
||
423 (entry
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
&&
424 entry
->fields
.remote_irr
))
427 irqe
.dest_id
= entry
->fields
.dest_id
;
428 irqe
.vector
= entry
->fields
.vector
;
429 irqe
.dest_mode
= kvm_lapic_irq_dest_mode(!!entry
->fields
.dest_mode
);
430 irqe
.trig_mode
= entry
->fields
.trig_mode
;
431 irqe
.delivery_mode
= entry
->fields
.delivery_mode
<< 8;
433 irqe
.shorthand
= APIC_DEST_NOSHORT
;
434 irqe
.msi_redir_hint
= false;
436 if (irqe
.trig_mode
== IOAPIC_EDGE_TRIG
)
437 ioapic
->irr_delivered
|= 1 << irq
;
439 if (irq
== RTC_GSI
&& line_status
) {
441 * pending_eoi cannot ever become negative (see
442 * rtc_status_pending_eoi_check_valid) and the caller
443 * ensures that it is only called if it is >= zero, namely
444 * if rtc_irq_check_coalesced returns false).
446 BUG_ON(ioapic
->rtc_status
.pending_eoi
!= 0);
447 ret
= kvm_irq_delivery_to_apic(ioapic
->kvm
, NULL
, &irqe
,
448 &ioapic
->rtc_status
.dest_map
);
449 ioapic
->rtc_status
.pending_eoi
= (ret
< 0 ? 0 : ret
);
451 ret
= kvm_irq_delivery_to_apic(ioapic
->kvm
, NULL
, &irqe
, NULL
);
453 if (ret
&& irqe
.trig_mode
== IOAPIC_LEVEL_TRIG
)
454 entry
->fields
.remote_irr
= 1;
459 int kvm_ioapic_set_irq(struct kvm_ioapic
*ioapic
, int irq
, int irq_source_id
,
460 int level
, bool line_status
)
464 BUG_ON(irq
< 0 || irq
>= IOAPIC_NUM_PINS
);
466 spin_lock(&ioapic
->lock
);
467 irq_level
= __kvm_irq_line_state(&ioapic
->irq_states
[irq
],
468 irq_source_id
, level
);
469 ret
= ioapic_set_irq(ioapic
, irq
, irq_level
, line_status
);
471 spin_unlock(&ioapic
->lock
);
476 void kvm_ioapic_clear_all(struct kvm_ioapic
*ioapic
, int irq_source_id
)
480 spin_lock(&ioapic
->lock
);
481 for (i
= 0; i
< KVM_IOAPIC_NUM_PINS
; i
++)
482 __clear_bit(irq_source_id
, &ioapic
->irq_states
[i
]);
483 spin_unlock(&ioapic
->lock
);
486 static void kvm_ioapic_eoi_inject_work(struct work_struct
*work
)
489 struct kvm_ioapic
*ioapic
= container_of(work
, struct kvm_ioapic
,
491 spin_lock(&ioapic
->lock
);
492 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
493 union kvm_ioapic_redirect_entry
*ent
= &ioapic
->redirtbl
[i
];
495 if (ent
->fields
.trig_mode
!= IOAPIC_LEVEL_TRIG
)
498 if (ioapic
->irr
& (1 << i
) && !ent
->fields
.remote_irr
)
499 ioapic_service(ioapic
, i
, false);
501 spin_unlock(&ioapic
->lock
);
504 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
505 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu
*vcpu
,
506 struct kvm_ioapic
*ioapic
,
510 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
511 union kvm_ioapic_redirect_entry
*ent
= &ioapic
->redirtbl
[pin
];
514 * We are dropping lock while calling ack notifiers because ack
515 * notifier callbacks for assigned devices call into IOAPIC
516 * recursively. Since remote_irr is cleared only after call
517 * to notifiers if the same vector will be delivered while lock
518 * is dropped it will be put into irr and will be delivered
519 * after ack notifier returns.
521 spin_unlock(&ioapic
->lock
);
522 kvm_notify_acked_irq(ioapic
->kvm
, KVM_IRQCHIP_IOAPIC
, pin
);
523 spin_lock(&ioapic
->lock
);
525 if (trigger_mode
!= IOAPIC_LEVEL_TRIG
||
526 kvm_lapic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
)
529 ASSERT(ent
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
);
530 ent
->fields
.remote_irr
= 0;
531 if (!ent
->fields
.mask
&& (ioapic
->irr
& (1 << pin
))) {
532 ++ioapic
->irq_eoi
[pin
];
533 if (ioapic
->irq_eoi
[pin
] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT
) {
535 * Real hardware does not deliver the interrupt
536 * immediately during eoi broadcast, and this
537 * lets a buggy guest make slow progress
538 * even if it does not correctly handle a
539 * level-triggered interrupt. Emulate this
540 * behavior if we detect an interrupt storm.
542 schedule_delayed_work(&ioapic
->eoi_inject
, HZ
/ 100);
543 ioapic
->irq_eoi
[pin
] = 0;
544 trace_kvm_ioapic_delayed_eoi_inj(ent
->bits
);
546 ioapic_service(ioapic
, pin
, false);
549 ioapic
->irq_eoi
[pin
] = 0;
553 void kvm_ioapic_update_eoi(struct kvm_vcpu
*vcpu
, int vector
, int trigger_mode
)
556 struct kvm_ioapic
*ioapic
= vcpu
->kvm
->arch
.vioapic
;
558 spin_lock(&ioapic
->lock
);
559 rtc_irq_eoi(ioapic
, vcpu
, vector
);
560 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
561 union kvm_ioapic_redirect_entry
*ent
= &ioapic
->redirtbl
[i
];
563 if (ent
->fields
.vector
!= vector
)
565 kvm_ioapic_update_eoi_one(vcpu
, ioapic
, trigger_mode
, i
);
567 spin_unlock(&ioapic
->lock
);
570 static inline struct kvm_ioapic
*to_ioapic(struct kvm_io_device
*dev
)
572 return container_of(dev
, struct kvm_ioapic
, dev
);
575 static inline int ioapic_in_range(struct kvm_ioapic
*ioapic
, gpa_t addr
)
577 return ((addr
>= ioapic
->base_address
&&
578 (addr
< ioapic
->base_address
+ IOAPIC_MEM_LENGTH
)));
581 static int ioapic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
582 gpa_t addr
, int len
, void *val
)
584 struct kvm_ioapic
*ioapic
= to_ioapic(this);
586 if (!ioapic_in_range(ioapic
, addr
))
589 ASSERT(!(addr
& 0xf)); /* check alignment */
592 spin_lock(&ioapic
->lock
);
594 case IOAPIC_REG_SELECT
:
595 result
= ioapic
->ioregsel
;
598 case IOAPIC_REG_WINDOW
:
599 result
= ioapic_read_indirect(ioapic
, addr
, len
);
606 spin_unlock(&ioapic
->lock
);
610 *(u64
*) val
= result
;
615 memcpy(val
, (char *)&result
, len
);
618 printk(KERN_WARNING
"ioapic: wrong length %d\n", len
);
623 static int ioapic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
624 gpa_t addr
, int len
, const void *val
)
626 struct kvm_ioapic
*ioapic
= to_ioapic(this);
628 if (!ioapic_in_range(ioapic
, addr
))
631 ASSERT(!(addr
& 0xf)); /* check alignment */
645 printk(KERN_WARNING
"ioapic: Unsupported size %d\n", len
);
650 spin_lock(&ioapic
->lock
);
652 case IOAPIC_REG_SELECT
:
653 ioapic
->ioregsel
= data
& 0xFF; /* 8-bit register */
656 case IOAPIC_REG_WINDOW
:
657 ioapic_write_indirect(ioapic
, data
);
663 spin_unlock(&ioapic
->lock
);
667 static void kvm_ioapic_reset(struct kvm_ioapic
*ioapic
)
671 cancel_delayed_work_sync(&ioapic
->eoi_inject
);
672 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
673 ioapic
->redirtbl
[i
].fields
.mask
= 1;
674 ioapic
->base_address
= IOAPIC_DEFAULT_BASE_ADDRESS
;
675 ioapic
->ioregsel
= 0;
677 ioapic
->irr_delivered
= 0;
679 memset(ioapic
->irq_eoi
, 0x00, sizeof(ioapic
->irq_eoi
));
680 rtc_irq_eoi_tracking_reset(ioapic
);
683 static const struct kvm_io_device_ops ioapic_mmio_ops
= {
684 .read
= ioapic_mmio_read
,
685 .write
= ioapic_mmio_write
,
688 int kvm_ioapic_init(struct kvm
*kvm
)
690 struct kvm_ioapic
*ioapic
;
693 ioapic
= kzalloc(sizeof(struct kvm_ioapic
), GFP_KERNEL_ACCOUNT
);
696 spin_lock_init(&ioapic
->lock
);
697 INIT_DELAYED_WORK(&ioapic
->eoi_inject
, kvm_ioapic_eoi_inject_work
);
698 kvm
->arch
.vioapic
= ioapic
;
699 kvm_ioapic_reset(ioapic
);
700 kvm_iodevice_init(&ioapic
->dev
, &ioapic_mmio_ops
);
702 mutex_lock(&kvm
->slots_lock
);
703 ret
= kvm_io_bus_register_dev(kvm
, KVM_MMIO_BUS
, ioapic
->base_address
,
704 IOAPIC_MEM_LENGTH
, &ioapic
->dev
);
705 mutex_unlock(&kvm
->slots_lock
);
707 kvm
->arch
.vioapic
= NULL
;
714 void kvm_ioapic_destroy(struct kvm
*kvm
)
716 struct kvm_ioapic
*ioapic
= kvm
->arch
.vioapic
;
721 cancel_delayed_work_sync(&ioapic
->eoi_inject
);
722 mutex_lock(&kvm
->slots_lock
);
723 kvm_io_bus_unregister_dev(kvm
, KVM_MMIO_BUS
, &ioapic
->dev
);
724 mutex_unlock(&kvm
->slots_lock
);
725 kvm
->arch
.vioapic
= NULL
;
729 void kvm_get_ioapic(struct kvm
*kvm
, struct kvm_ioapic_state
*state
)
731 struct kvm_ioapic
*ioapic
= kvm
->arch
.vioapic
;
733 spin_lock(&ioapic
->lock
);
734 memcpy(state
, ioapic
, sizeof(struct kvm_ioapic_state
));
735 state
->irr
&= ~ioapic
->irr_delivered
;
736 spin_unlock(&ioapic
->lock
);
739 void kvm_set_ioapic(struct kvm
*kvm
, struct kvm_ioapic_state
*state
)
741 struct kvm_ioapic
*ioapic
= kvm
->arch
.vioapic
;
743 spin_lock(&ioapic
->lock
);
744 memcpy(ioapic
, state
, sizeof(struct kvm_ioapic_state
));
746 ioapic
->irr_delivered
= 0;
747 kvm_make_scan_ioapic_request(kvm
);
748 kvm_ioapic_inject_all(ioapic
, state
->irr
);
749 spin_unlock(&ioapic
->lock
);