arch/x86/kvm/ioapic.c

   1 /*
   2  *  Copyright (C) 2001  MandrakeSoft S.A.
   3  *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
   4  *
   5  *    MandrakeSoft S.A.
   6  *    43, rue d'Aboukir
   7  *    75002 Paris - France
   8  *    http://www.linux-mandrake.com/
   9  *    http://www.mandrakesoft.com/
  10  *
  11  *  This library is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU Lesser General Public
  13  *  License as published by the Free Software Foundation; either
  14  *  version 2 of the License, or (at your option) any later version.
  15  *
  16  *  This library is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  *  Lesser General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU Lesser General Public
  22  *  License along with this library; if not, write to the Free Software
  23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24  *
  25  *  Yunhong Jiang <yunhong.jiang@intel.com>
  26  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27  *  Based on Xen 3.1 code.
  28  */
  29
  30 #include <linux/kvm_host.h>
  31 #include <linux/kvm.h>
  32 #include <linux/mm.h>
  33 #include <linux/highmem.h>
  34 #include <linux/smp.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/export.h>
  39 #include <linux/nospec.h>
  40 #include <asm/processor.h>
  41 #include <asm/page.h>
  42 #include <asm/current.h>
  43 #include <trace/events/kvm.h>
  44
  45 #include "ioapic.h"
  46 #include "lapic.h"
  47 #include "irq.h"
  48
  49 static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
  50                 bool line_status);
  51
  52 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
  53                                       struct kvm_ioapic *ioapic,
  54                                       int trigger_mode,
  55                                       int pin);
  56
  57 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  58                                           unsigned long addr,
  59                                           unsigned long length)
  60 {
  61         unsigned long result = 0;
  62
  63         switch (ioapic->ioregsel) {
  64         case IOAPIC_REG_VERSION:
  65                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  66                           | (IOAPIC_VERSION_ID & 0xff));
  67                 break;
  68
  69         case IOAPIC_REG_APIC_ID:
  70         case IOAPIC_REG_ARB_ID:
  71                 result = ((ioapic->id & 0xf) << 24);
  72                 break;
  73
  74         default:
  75                 {
  76                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  77                         u64 redir_content = ~0ULL;
  78
  79                         if (redir_index < IOAPIC_NUM_PINS) {
  80                                 u32 index = array_index_nospec(
  81                                         redir_index, IOAPIC_NUM_PINS);
  82
  83                                 redir_content = ioapic->redirtbl[index].bits;
  84                         }
  85
  86                         result = (ioapic->ioregsel & 0x1) ?
  87                             (redir_content >> 32) & 0xffffffff :
  88                             redir_content & 0xffffffff;
  89                         break;
  90                 }
  91         }
  92
  93         return result;
  94 }
  95
  96 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
  97 {
  98         ioapic->rtc_status.pending_eoi = 0;
  99         bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID);
 100 }
 101
 102 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
 103
 104 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
 105 {
 106         if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
 107                 kvm_rtc_eoi_tracking_restore_all(ioapic);
 108 }
 109
 110 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
 111 {
 112         bool new_val, old_val;
 113         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 114         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 115         union kvm_ioapic_redirect_entry *e;
 116
 117         e = &ioapic->redirtbl[RTC_GSI];
 118         if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 119                                  e->fields.dest_id,
 120                                  kvm_lapic_irq_dest_mode(!!e->fields.dest_mode)))
 121                 return;
 122
 123         new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
 124         old_val = test_bit(vcpu->vcpu_id, dest_map->map);
 125
 126         if (new_val == old_val)
 127                 return;
 128
 129         if (new_val) {
 130                 __set_bit(vcpu->vcpu_id, dest_map->map);
 131                 dest_map->vectors[vcpu->vcpu_id] = e->fields.vector;
 132                 ioapic->rtc_status.pending_eoi++;
 133         } else {
 134                 __clear_bit(vcpu->vcpu_id, dest_map->map);
 135                 ioapic->rtc_status.pending_eoi--;
 136                 rtc_status_pending_eoi_check_valid(ioapic);
 137         }
 138 }
 139
 140 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
 141 {
 142         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 143
 144         spin_lock(&ioapic->lock);
 145         __rtc_irq_eoi_tracking_restore_one(vcpu);
 146         spin_unlock(&ioapic->lock);
 147 }
 148
 149 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
 150 {
 151         struct kvm_vcpu *vcpu;
 152         int i;
 153
 154         if (RTC_GSI >= IOAPIC_NUM_PINS)
 155                 return;
 156
 157         rtc_irq_eoi_tracking_reset(ioapic);
 158         kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
 159             __rtc_irq_eoi_tracking_restore_one(vcpu);
 160 }
 161
 162 static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu,
 163                         int vector)
 164 {
 165         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 166
 167         /* RTC special handling */
 168         if (test_bit(vcpu->vcpu_id, dest_map->map) &&
 169             (vector == dest_map->vectors[vcpu->vcpu_id]) &&
 170             (test_and_clear_bit(vcpu->vcpu_id,
 171                                 ioapic->rtc_status.dest_map.map))) {
 172                 --ioapic->rtc_status.pending_eoi;
 173                 rtc_status_pending_eoi_check_valid(ioapic);
 174         }
 175 }
 176
 177 static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
 178 {
 179         if (ioapic->rtc_status.pending_eoi > 0)
 180                 return true; /* coalesced */
 181
 182         return false;
 183 }
 184
 185 static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq)
 186 {
 187         int i;
 188         struct kvm_vcpu *vcpu;
 189         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 190
 191         kvm_for_each_vcpu(i, vcpu, ioapic->kvm) {
 192                 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 193                                          entry->fields.dest_id,
 194                                          entry->fields.dest_mode) ||
 195                     kvm_apic_pending_eoi(vcpu, entry->fields.vector))
 196                         continue;
 197
 198                 /*
 199                  * If no longer has pending EOI in LAPICs, update
 200                  * EOI for this vetor.
 201                  */
 202                 rtc_irq_eoi(ioapic, vcpu, entry->fields.vector);
 203                 kvm_ioapic_update_eoi_one(vcpu, ioapic,
 204                                           entry->fields.trig_mode,
 205                                           irq);
 206                 break;
 207         }
 208 }
 209
 210 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
 211                 int irq_level, bool line_status)
 212 {
 213         union kvm_ioapic_redirect_entry entry;
 214         u32 mask = 1 << irq;
 215         u32 old_irr;
 216         int edge, ret;
 217
 218         entry = ioapic->redirtbl[irq];
 219         edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 220
 221         if (!irq_level) {
 222                 ioapic->irr &= ~mask;
 223                 ret = 1;
 224                 goto out;
 225         }
 226
 227         /*
 228          * AMD SVM AVIC accelerate EOI write and do not trap,
 229          * in-kernel IOAPIC will not be able to receive the EOI.
 230          * In this case, we do lazy update of the pending EOI when
 231          * trying to set IOAPIC irq.
 232          */
 233         if (kvm_apicv_activated(ioapic->kvm))
 234                 ioapic_lazy_update_eoi(ioapic, irq);
 235
 236         /*
 237          * Return 0 for coalesced interrupts; for edge-triggered interrupts,
 238          * this only happens if a previous edge has not been delivered due
 239          * to masking.  For level interrupts, the remote_irr field tells
 240          * us if the interrupt is waiting for an EOI.
 241          *
 242          * RTC is special: it is edge-triggered, but userspace likes to know
 243          * if it has been already ack-ed via EOI because coalesced RTC
 244          * interrupts lead to time drift in Windows guests.  So we track
 245          * EOI manually for the RTC interrupt.
 246          */
 247         if (irq == RTC_GSI && line_status &&
 248                 rtc_irq_check_coalesced(ioapic)) {
 249                 ret = 0;
 250                 goto out;
 251         }
 252
 253         old_irr = ioapic->irr;
 254         ioapic->irr |= mask;
 255         if (edge) {
 256                 ioapic->irr_delivered &= ~mask;
 257                 if (old_irr == ioapic->irr) {
 258                         ret = 0;
 259                         goto out;
 260                 }
 261         }
 262
 263         ret = ioapic_service(ioapic, irq, line_status);
 264
 265 out:
 266         trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
 267         return ret;
 268 }
 269
 270 static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
 271 {
 272         u32 idx;
 273
 274         rtc_irq_eoi_tracking_reset(ioapic);
 275         for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
 276                 ioapic_set_irq(ioapic, idx, 1, true);
 277
 278         kvm_rtc_eoi_tracking_restore_all(ioapic);
 279 }
 280
 281
 282 void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
 283 {
 284         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 285         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 286         union kvm_ioapic_redirect_entry *e;
 287         int index;
 288
 289         spin_lock(&ioapic->lock);
 290
 291         /* Make sure we see any missing RTC EOI */
 292         if (test_bit(vcpu->vcpu_id, dest_map->map))
 293                 __set_bit(dest_map->vectors[vcpu->vcpu_id],
 294                           ioapic_handled_vectors);
 295
 296         for (index = 0; index < IOAPIC_NUM_PINS; index++) {
 297                 e = &ioapic->redirtbl[index];
 298                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
 299                     kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
 300                     index == RTC_GSI) {
 301                         u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
 302
 303                         if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 304                                                 e->fields.dest_id, dm) ||
 305                             kvm_apic_pending_eoi(vcpu, e->fields.vector))
 306                                 __set_bit(e->fields.vector,
 307                                           ioapic_handled_vectors);
 308                 }
 309         }
 310         spin_unlock(&ioapic->lock);
 311 }
 312
 313 void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm)
 314 {
 315         if (!ioapic_in_kernel(kvm))
 316                 return;
 317         kvm_make_scan_ioapic_request(kvm);
 318 }
 319
 320 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 321 {
 322         unsigned index;
 323         bool mask_before, mask_after;
 324         union kvm_ioapic_redirect_entry *e;
 325         unsigned long vcpu_bitmap;
 326         int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode;
 327
 328         switch (ioapic->ioregsel) {
 329         case IOAPIC_REG_VERSION:
 330                 /* Writes are ignored. */
 331                 break;
 332
 333         case IOAPIC_REG_APIC_ID:
 334                 ioapic->id = (val >> 24) & 0xf;
 335                 break;
 336
 337         case IOAPIC_REG_ARB_ID:
 338                 break;
 339
 340         default:
 341                 index = (ioapic->ioregsel - 0x10) >> 1;
 342
 343                 if (index >= IOAPIC_NUM_PINS)
 344                         return;
 345                 index = array_index_nospec(index, IOAPIC_NUM_PINS);
 346                 e = &ioapic->redirtbl[index];
 347                 mask_before = e->fields.mask;
 348                 /* Preserve read-only fields */
 349                 old_remote_irr = e->fields.remote_irr;
 350                 old_delivery_status = e->fields.delivery_status;
 351                 old_dest_id = e->fields.dest_id;
 352                 old_dest_mode = e->fields.dest_mode;
 353                 if (ioapic->ioregsel & 1) {
 354                         e->bits &= 0xffffffff;
 355                         e->bits |= (u64) val << 32;
 356                 } else {
 357                         e->bits &= ~0xffffffffULL;
 358                         e->bits |= (u32) val;
 359                 }
 360                 e->fields.remote_irr = old_remote_irr;
 361                 e->fields.delivery_status = old_delivery_status;
 362
 363                 /*
 364                  * Some OSes (Linux, Xen) assume that Remote IRR bit will
 365                  * be cleared by IOAPIC hardware when the entry is configured
 366                  * as edge-triggered. This behavior is used to simulate an
 367                  * explicit EOI on IOAPICs that don't have the EOI register.
 368                  */
 369                 if (e->fields.trig_mode == IOAPIC_EDGE_TRIG)
 370                         e->fields.remote_irr = 0;
 371
 372                 mask_after = e->fields.mask;
 373                 if (mask_before != mask_after)
 374                         kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
 375                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
 376                     && ioapic->irr & (1 << index))
 377                         ioapic_service(ioapic, index, false);
 378                 if (e->fields.delivery_mode == APIC_DM_FIXED) {
 379                         struct kvm_lapic_irq irq;
 380
 381                         irq.vector = e->fields.vector;
 382                         irq.delivery_mode = e->fields.delivery_mode << 8;
 383                         irq.dest_mode =
 384                             kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
 385                         irq.level = false;
 386                         irq.trig_mode = e->fields.trig_mode;
 387                         irq.shorthand = APIC_DEST_NOSHORT;
 388                         irq.dest_id = e->fields.dest_id;
 389                         irq.msi_redir_hint = false;
 390                         bitmap_zero(&vcpu_bitmap, 16);
 391                         kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
 392                                                  &vcpu_bitmap);
 393                         if (old_dest_mode != e->fields.dest_mode ||
 394                             old_dest_id != e->fields.dest_id) {
 395                                 /*
 396                                  * Update vcpu_bitmap with vcpus specified in
 397                                  * the previous request as well. This is done to
 398                                  * keep ioapic_handled_vectors synchronized.
 399                                  */
 400                                 irq.dest_id = old_dest_id;
 401                                 irq.dest_mode =
 402                                     kvm_lapic_irq_dest_mode(
 403                                         !!e->fields.dest_mode);
 404                                 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
 405                                                          &vcpu_bitmap);
 406                         }
 407                         kvm_make_scan_ioapic_request_mask(ioapic->kvm,
 408                                                           &vcpu_bitmap);
 409                 } else {
 410                         kvm_make_scan_ioapic_request(ioapic->kvm);
 411                 }
 412                 break;
 413         }
 414 }
 415
 416 static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
 417 {
 418         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 419         struct kvm_lapic_irq irqe;
 420         int ret;
 421
 422         if (entry->fields.mask ||
 423             (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
 424             entry->fields.remote_irr))
 425                 return -1;
 426
 427         irqe.dest_id = entry->fields.dest_id;
 428         irqe.vector = entry->fields.vector;
 429         irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode);
 430         irqe.trig_mode = entry->fields.trig_mode;
 431         irqe.delivery_mode = entry->fields.delivery_mode << 8;
 432         irqe.level = 1;
 433         irqe.shorthand = APIC_DEST_NOSHORT;
 434         irqe.msi_redir_hint = false;
 435
 436         if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
 437                 ioapic->irr_delivered |= 1 << irq;
 438
 439         if (irq == RTC_GSI && line_status) {
 440                 /*
 441                  * pending_eoi cannot ever become negative (see
 442                  * rtc_status_pending_eoi_check_valid) and the caller
 443                  * ensures that it is only called if it is >= zero, namely
 444                  * if rtc_irq_check_coalesced returns false).
 445                  */
 446                 BUG_ON(ioapic->rtc_status.pending_eoi != 0);
 447                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
 448                                                &ioapic->rtc_status.dest_map);
 449                 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
 450         } else
 451                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
 452
 453         if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
 454                 entry->fields.remote_irr = 1;
 455
 456         return ret;
 457 }
 458
 459 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
 460                        int level, bool line_status)
 461 {
 462         int ret, irq_level;
 463
 464         BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
 465
 466         spin_lock(&ioapic->lock);
 467         irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
 468                                          irq_source_id, level);
 469         ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
 470
 471         spin_unlock(&ioapic->lock);
 472
 473         return ret;
 474 }
 475
 476 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
 477 {
 478         int i;
 479
 480         spin_lock(&ioapic->lock);
 481         for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
 482                 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
 483         spin_unlock(&ioapic->lock);
 484 }
 485
 486 static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
 487 {
 488         int i;
 489         struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
 490                                                  eoi_inject.work);
 491         spin_lock(&ioapic->lock);
 492         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 493                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 494
 495                 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
 496                         continue;
 497
 498                 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
 499                         ioapic_service(ioapic, i, false);
 500         }
 501         spin_unlock(&ioapic->lock);
 502 }
 503
 504 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
 505 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
 506                                       struct kvm_ioapic *ioapic,
 507                                       int trigger_mode,
 508                                       int pin)
 509 {
 510         struct kvm_lapic *apic = vcpu->arch.apic;
 511         union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin];
 512
 513         /*
 514          * We are dropping lock while calling ack notifiers because ack
 515          * notifier callbacks for assigned devices call into IOAPIC
 516          * recursively. Since remote_irr is cleared only after call
 517          * to notifiers if the same vector will be delivered while lock
 518          * is dropped it will be put into irr and will be delivered
 519          * after ack notifier returns.
 520          */
 521         spin_unlock(&ioapic->lock);
 522         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
 523         spin_lock(&ioapic->lock);
 524
 525         if (trigger_mode != IOAPIC_LEVEL_TRIG ||
 526             kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
 527                 return;
 528
 529         ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 530         ent->fields.remote_irr = 0;
 531         if (!ent->fields.mask && (ioapic->irr & (1 << pin))) {
 532                 ++ioapic->irq_eoi[pin];
 533                 if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
 534                         /*
 535                          * Real hardware does not deliver the interrupt
 536                          * immediately during eoi broadcast, and this
 537                          * lets a buggy guest make slow progress
 538                          * even if it does not correctly handle a
 539                          * level-triggered interrupt.  Emulate this
 540                          * behavior if we detect an interrupt storm.
 541                          */
 542                         schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
 543                         ioapic->irq_eoi[pin] = 0;
 544                         trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
 545                 } else {
 546                         ioapic_service(ioapic, pin, false);
 547                 }
 548         } else {
 549                 ioapic->irq_eoi[pin] = 0;
 550         }
 551 }
 552
 553 void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
 554 {
 555         int i;
 556         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 557
 558         spin_lock(&ioapic->lock);
 559         rtc_irq_eoi(ioapic, vcpu, vector);
 560         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 561                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 562
 563                 if (ent->fields.vector != vector)
 564                         continue;
 565                 kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i);
 566         }
 567         spin_unlock(&ioapic->lock);
 568 }
 569
 570 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 571 {
 572         return container_of(dev, struct kvm_ioapic, dev);
 573 }
 574
 575 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
 576 {
 577         return ((addr >= ioapic->base_address &&
 578                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 579 }
 580
 581 static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
 582                                 gpa_t addr, int len, void *val)
 583 {
 584         struct kvm_ioapic *ioapic = to_ioapic(this);
 585         u32 result;
 586         if (!ioapic_in_range(ioapic, addr))
 587                 return -EOPNOTSUPP;
 588
 589         ASSERT(!(addr & 0xf));  /* check alignment */
 590
 591         addr &= 0xff;
 592         spin_lock(&ioapic->lock);
 593         switch (addr) {
 594         case IOAPIC_REG_SELECT:
 595                 result = ioapic->ioregsel;
 596                 break;
 597
 598         case IOAPIC_REG_WINDOW:
 599                 result = ioapic_read_indirect(ioapic, addr, len);
 600                 break;
 601
 602         default:
 603                 result = 0;
 604                 break;
 605         }
 606         spin_unlock(&ioapic->lock);
 607
 608         switch (len) {
 609         case 8:
 610                 *(u64 *) val = result;
 611                 break;
 612         case 1:
 613         case 2:
 614         case 4:
 615                 memcpy(val, (char *)&result, len);
 616                 break;
 617         default:
 618                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 619         }
 620         return 0;
 621 }
 622
 623 static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
 624                                  gpa_t addr, int len, const void *val)
 625 {
 626         struct kvm_ioapic *ioapic = to_ioapic(this);
 627         u32 data;
 628         if (!ioapic_in_range(ioapic, addr))
 629                 return -EOPNOTSUPP;
 630
 631         ASSERT(!(addr & 0xf));  /* check alignment */
 632
 633         switch (len) {
 634         case 8:
 635         case 4:
 636                 data = *(u32 *) val;
 637                 break;
 638         case 2:
 639                 data = *(u16 *) val;
 640                 break;
 641         case 1:
 642                 data = *(u8  *) val;
 643                 break;
 644         default:
 645                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 646                 return 0;
 647         }
 648
 649         addr &= 0xff;
 650         spin_lock(&ioapic->lock);
 651         switch (addr) {
 652         case IOAPIC_REG_SELECT:
 653                 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
 654                 break;
 655
 656         case IOAPIC_REG_WINDOW:
 657                 ioapic_write_indirect(ioapic, data);
 658                 break;
 659
 660         default:
 661                 break;
 662         }
 663         spin_unlock(&ioapic->lock);
 664         return 0;
 665 }
 666
 667 static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 668 {
 669         int i;
 670
 671         cancel_delayed_work_sync(&ioapic->eoi_inject);
 672         for (i = 0; i < IOAPIC_NUM_PINS; i++)
 673                 ioapic->redirtbl[i].fields.mask = 1;
 674         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 675         ioapic->ioregsel = 0;
 676         ioapic->irr = 0;
 677         ioapic->irr_delivered = 0;
 678         ioapic->id = 0;
 679         memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
 680         rtc_irq_eoi_tracking_reset(ioapic);
 681 }
 682
 683 static const struct kvm_io_device_ops ioapic_mmio_ops = {
 684         .read     = ioapic_mmio_read,
 685         .write    = ioapic_mmio_write,
 686 };
 687
 688 int kvm_ioapic_init(struct kvm *kvm)
 689 {
 690         struct kvm_ioapic *ioapic;
 691         int ret;
 692
 693         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT);
 694         if (!ioapic)
 695                 return -ENOMEM;
 696         spin_lock_init(&ioapic->lock);
 697         INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
 698         kvm->arch.vioapic = ioapic;
 699         kvm_ioapic_reset(ioapic);
 700         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 701         ioapic->kvm = kvm;
 702         mutex_lock(&kvm->slots_lock);
 703         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
 704                                       IOAPIC_MEM_LENGTH, &ioapic->dev);
 705         mutex_unlock(&kvm->slots_lock);
 706         if (ret < 0) {
 707                 kvm->arch.vioapic = NULL;
 708                 kfree(ioapic);
 709         }
 710
 711         return ret;
 712 }
 713
 714 void kvm_ioapic_destroy(struct kvm *kvm)
 715 {
 716         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 717
 718         if (!ioapic)
 719                 return;
 720
 721         cancel_delayed_work_sync(&ioapic->eoi_inject);
 722         mutex_lock(&kvm->slots_lock);
 723         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
 724         mutex_unlock(&kvm->slots_lock);
 725         kvm->arch.vioapic = NULL;
 726         kfree(ioapic);
 727 }
 728
 729 void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 730 {
 731         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 732
 733         spin_lock(&ioapic->lock);
 734         memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
 735         state->irr &= ~ioapic->irr_delivered;
 736         spin_unlock(&ioapic->lock);
 737 }
 738
 739 void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 740 {
 741         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 742
 743         spin_lock(&ioapic->lock);
 744         memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
 745         ioapic->irr = 0;
 746         ioapic->irr_delivered = 0;
 747         kvm_make_scan_ioapic_request(kvm);
 748         kvm_ioapic_inject_all(ioapic, state->irr);
 749         spin_unlock(&ioapic->lock);
 750 }